<So, at first glance it looks like Bochs isn't doing floppy DMA when <the cpu is in the "hlt" state. This causes SeaBIOS to timeout the <transfer.
Right, Bochs CPU won't handle floppy DMA when halted. The CPU is just running busy loop until it finds pending INIT/NMI/SMI or INTR with EFLAGS.IF set. Should HRQ to take CPU out of halt state ? Or just handle the DEV_dma_raise_hlda and stay in halt state ?
Stanislav
-----Original Message----- From: Kevin O'Connor [mailto:kevin@koconnor.net] Sent: Tuesday, January 12, 2010 6:13 AM To: Sebastian Herbszt Cc: bochs-developers@lists.sourceforge.net; seabios@seabios.org Subject: Re: [Bochs-developers] [SeaBIOS] Bochs cvs + SeaBIOS git master + FreeDOS = slow load + invalid opcode
On Mon, Jan 11, 2010 at 10:28:49PM +0100, Sebastian Herbszt wrote:
The problem occurs on COMMAND: [e6] [04] [03] [01] [01] [02] [12] [00] [ff]
Debug output with Bochs BIOS
[...]
00131978879d[FDD ] read! 00131978879d[FDD ] floppy_xfer: drive=0, offset=64512, bytes=512,
direction=from floppy [...]
00135765306d[FDD ] floppy_xfer: drive=0, offset=73216, bytes=512,
direction=from floppy
00135988037d[FDD ] <<READ DONE>>
I'm guessing the first column is a timer - it shows a delta of 4009158 from floppy start to end.
Debug output with SeaBIOS
01484895591d[FDD ] read!
[...]
01484895591d[FDD ] floppy_xfer: drive=0, offset=64512, bytes=512,
direction=from floppy [...]
01643752509d[FDD ] floppy_xfer: drive=0, offset=70656, bytes=512,
direction=from floppy
01646422786d[FDD ] read(): during command 0xe6, port 0x03f2 returns 0x1c
The delta here is 161527195.
Also, if you count the "loop" reports you'll see there are 37 of them - the same number as FLOPPY_MOTOR_TICKS in src/floppy.c.
So, at first glance it looks like Bochs isn't doing floppy DMA when the cpu is in the "hlt" state. This causes SeaBIOS to timeout the transfer.
-Kevin
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