[SeaBIOS] [PATCH SeaBIOS v5] map 64-bit PCI BARs at location provided by emulator

[Igor Mammedov]

Currently 64-bit PCI BARs are unconditionally mapped by BIOS right
over 4G + RamSizeOver4G location, which doesn't allow to reserve
extra space before 64-bit PCI window. For memory hotplug an extra
RAM space might be reserved after present 64-bit RAM end and BIOS
should map 64-bit PCI BARs after it.

Introduce "etc/reserved-memory-end" romfile to provide BIOS a hint
where it should start mapping of 64-bit PCI BARs. If romfile is
missing, BIOS reverts to legacy behavior and starts mapping after
high memory.

Signed-off-by: Igor Mammedov 
---
Corresponding QEMU patch is here: http://patchwork.ozlabs.org/patch/291417/

v4,5:
  * rebasing on top of current master
v3:
  * s/pcimem64-start/reserved-memory-end/
v2:
  * place 64-bit window behind high RAM end if "etc/pcimem64-start"
    point below it.
---
 src/pciinit.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/pciinit.c b/src/pciinit.c
index 7e63c5e..5aef8a6 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -15,6 +15,7 @@
 #include "paravirt.h" // RamSize
 #include "dev-q35.h" // Q35_HOST_BRIDGE_PCIEXBAR_ADDR
 #include "list.h" // struct hlist_node
+#include "byteorder.h" // le64_to_cpu

/* PM Timer ticks per second (HZ) */
 #define PM_TIMER_FREQUENCY  3579545
@@ -762,6 +763,15 @@ static void pci_bios_map_devices(struct pci_bus *busses)
 {
     if (pci_bios_init_root_regions(busses)) {
         struct pci_region r64_mem, r64_pref;
+        u64 ram64_end = 0x100000000ULL + RamSizeOver4G;
+        u64 base64 = le64_to_cpu(romfile_loadint("etc/reserved-memory-end",
+                                 ram64_end));
+        if (base64 < ram64_end) {
+            dprintf(1, "ignorig etc/reserved-memory-end [0x%llx] below present"
+                       " RAM, placing 64-bit PCI window behind RAM end: %llx",
+                        base64, ram64_end);
+            base64 = ram64_end;
+        }
         r64_mem.list.first = NULL;
         r64_pref.list.first = NULL;
         pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_MEM],
@@ -777,7 +787,7 @@ static void pci_bios_map_devices(struct pci_bus *busses)
         u64 align_mem = pci_region_align(&r64_mem);
         u64 align_pref = pci_region_align(&r64_pref);

-        r64_mem.base = ALIGN(0x100000000LL + RamSizeOver4G, align_mem);
+        r64_mem.base = ALIGN(base64, align_mem);
         r64_pref.base = ALIGN(r64_mem.base + sum_mem, align_pref);
         pcimem64_start = r64_mem.base;
         pcimem64_end = r64_pref.base + sum_pref;