[SeaBIOS] Re: [PATCH 4/4] serialio: Support for pci serial ports

[Gerd Hoffmann]

Hi,
> Some Intel PCHs integrate pci uarts which are used for serial
> port debugging. For compatibility purpose, BIOS implementation
> may assign 0x3f8 to the pci uart's io bar at PEI stage, later
> during DXE stage the pci uart's bar is re-assigned to a different
> address.

What firmware you are running on this hardware?
Something tianocore based I guess?
Is the code public?
> As a result, we can't use the hard coded IO port 0x3f8
> in SeaBIOS for debugging. Instead, we need read the port base
> address from the pci uart's BAR, either an IO BAR, or a 32bit
> memory BAR.

Ok, but ...
> config DEBUG_SERIAL_PCI_BDF
>    depends on DEBUG_SERIAL_PCI_IO || DEBUG_SERIAL_PCI_MEM32
>    hex "Serial port PCI bus/device/function"

... hardcoding the BDF instead isn't that great either.  Can't we just
find the device while scanning for pci devices?

cheers,
  Gerd