Re: [SeaBIOS] [PATCH v2 3/3] tests: add testcase for TCO watchdog emulation

[Paolo Bonzini]

On 31/05/2015 00:04, Paulo Alcantara wrote:
> v1 -> v2:
> some cleanup
> added test for TCO_LOCK bit
> Signed-off-by: Paulo Alcantara
>
> tests/Makefile   |   2 +
>  tests/tco-test.c | 419 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 421 insertions(+)
>  create mode 100644 tests/tco-test.c
>
> diff --git a/tests/Makefile b/tests/Makefile
> index 729b969..43950d0 100644
> --- a/tests/Makefile
> +++ b/tests/Makefile
> @@ -150,6 +150,7 @@ check-qtest-i386-y += tests/i440fx-test$(EXESUF)
>  check-qtest-i386-y += tests/fw_cfg-test$(EXESUF)
>  check-qtest-i386-y += tests/drive_del-test$(EXESUF)
>  check-qtest-i386-y += tests/wdt_ib700-test$(EXESUF)
> +check-qtest-i386-y += tests/tco-test$(EXESUF)
>  gcov-files-i386-y += hw/watchdog/watchdog.c hw/watchdog/wdt_ib700.c
>  check-qtest-i386-y += $(check-qtest-pci-y)
>  gcov-files-i386-y += $(gcov-files-pci-y)
> @@ -363,6 +364,7 @@ tests/eepro100-test$(EXESUF): tests/eepro100-test.o
>  tests/vmxnet3-test$(EXESUF): tests/vmxnet3-test.o
>  tests/ne2000-test$(EXESUF): tests/ne2000-test.o
>  tests/wdt_ib700-test$(EXESUF): tests/wdt_ib700-test.o
> +tests/tco-test$(EXESUF): tests/tco-test.o $(libqos-pc-obj-y)
>  tests/virtio-balloon-test$(EXESUF): tests/virtio-balloon-test.o
>  tests/virtio-blk-test$(EXESUF): tests/virtio-blk-test.o $(libqos-virtio-obj-y)
>  tests/virtio-net-test$(EXESUF): tests/virtio-net-test.o $(libqos-pc-obj-y)
> diff --git a/tests/tco-test.c b/tests/tco-test.c
> new file mode 100644
> index 0000000..47c15c9
> --- /dev/null
> +++ b/tests/tco-test.c
> @@ -0,0 +1,419 @@
> +/*
> QEMU ICH9 TCO emulation tests
> Copyright (c) 2015 Paulo Alcantara
> Permission is hereby granted, free of charge, to any person obtaining a copy
> of this software and associated documentation files (the "Software"), to deal
> in the Software without restriction, including without limitation the rights
> to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> copies of the Software, and to permit persons to whom the Software is
> furnished to do so, subject to the following conditions:
> The above copyright notice and this permission notice shall be included in
> all copies or substantial portions of the Software.
> THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> THE SOFTWARE.
> */
>
> +#include <glib.h>
> +#include <string.h>
> +#include <stdio.h>
> +#include <stdlib.h>
>
> +#include "libqtest.h"
> +#include "libqos/pci.h"
> +#include "libqos/pci-pc.h"
> +#include "hw/pci/pci_regs.h"
> +#include "hw/i386/ich9.h"
> +#include "hw/acpi/ich9.h"
> +#include "hw/acpi/tco.h"
>
> +#define PM_IO_BASE_ADDR    0xb000
> +#define RCBA_BASE_ADDR     0xfed1c000
>
> +enum {
> TCO_RLD_DEFAULT         = 0x0000,
> TCO_DAT_IN_DEFAULT      = 0x00,
> TCO_DAT_OUT_DEFAULT     = 0x00,
> TCO1_STS_DEFAULT        = 0x0000,
> TCO2_STS_DEFAULT        = 0x0000,
> TCO1_CNT_DEFAULT        = 0x0000,
> TCO2_CNT_DEFAULT        = 0x0008,
> TCO_MESSAGE1_DEFAULT    = 0x00,
> TCO_MESSAGE2_DEFAULT    = 0x00,
> TCO_WDCNT_DEFAULT       = 0x00,
> TCO_TMR_DEFAULT         = 0x0004,
> SW_IRQ_GEN_DEFAULT      = 0x03,
>
> +};
>
> +#define TCO_SECS_TO_TICKS(secs)     (((secs) * 10) / 6)
> +#define TCO_TICKS_TO_SECS(ticks)    (((ticks) * 6) / 10)
>
> +typedef struct {
> const char *args;
> QPCIDevice *dev;
> void *lpc_base;
> void *tco_io_base;
>
> +} TestData;
>
> +static void test_init(TestData *d)
> +{
> QPCIBus *bus;
> QTestState *qs;
> char *s;
> s = g_strdup_printf("-machine q35 %s", !d->args ? "" : d->args);
> qs = qtest_start(s);
> qtest_irq_intercept_in(qs, "ioapic");
> g_free(s);
> bus = qpci_init_pc();
> d->dev = qpci_device_find(bus, QPCI_DEVFN(0x1f, 0x00));
> g_assert(d->dev != NULL);
> /* map PCI-to-LPC bridge interface BAR */
> d->lpc_base = qpci_iomap(d->dev, 0, NULL);
> qpci_device_enable(d->dev);
> g_assert(d->lpc_base != NULL);
> /* set ACPI PM I/O space base address */
> qpci_config_writel(d->dev, (uintptr_t)d->lpc_base + ICH9_LPC_PMBASE,
>                   PM_IO_BASE_ADDR | 0x1);
> /* enable ACPI I/O */
> qpci_config_writeb(d->dev, (uintptr_t)d->lpc_base + ICH9_LPC_ACPI_CTRL,
>                   0x80);
> /* set Root Complex BAR */
> qpci_config_writel(d->dev, (uintptr_t)d->lpc_base + ICH9_LPC_RCBA,
>                   RCBA_BASE_ADDR | 0x1);
> d->tco_io_base = (void *)((uintptr_t)PM_IO_BASE_ADDR + 0x60);
>
> +}
>
> +static void stop_tco(const TestData *d)
> +{
> uint32_t val;
> val = qpci_io_readw(d->dev, d->tco_io_base + TCO1_CNT);
> val |= TCO_TMR_HLT;
> qpci_io_writew(d->dev, d->tco_io_base + TCO1_CNT, val);
>
> +}
>
> +static void start_tco(const TestData *d)
> +{
> uint32_t val;
> val = qpci_io_readw(d->dev, d->tco_io_base + TCO1_CNT);
> val &= ~TCO_TMR_HLT;
> qpci_io_writew(d->dev, d->tco_io_base + TCO1_CNT, val);
>
> +}
>
> +static void load_tco(const TestData *d)
> +{
> qpci_io_writew(d->dev, d->tco_io_base + TCO_RLD, 4);
>
> +}
>
> +static void set_tco_timeout(const TestData *d, uint16_t ticks)
> +{
> qpci_io_writew(d->dev, d->tco_io_base + TCO_TMR, ticks);
>
> +}
>
> +static void clear_tco_status(const TestData *d)
> +{
> qpci_io_writew(d->dev, d->tco_io_base + TCO1_STS, 0x0008);
> qpci_io_writew(d->dev, d->tco_io_base + TCO2_STS, 0x0002);
> qpci_io_writew(d->dev, d->tco_io_base + TCO2_STS, 0x0004);
>
> +}
>
> +static void reset_on_second_timeout(bool enable)
> +{
> uint32_t val;
> val = readl(RCBA_BASE_ADDR + ICH9_LPC_RCBA_GCS);
> if (enable) {
>    val &= ~ICH9_LPC_RCBA_GCS_NO_REBOOT;
> } else {
>    val |= ICH9_LPC_RCBA_GCS_NO_REBOOT;
> }
> writel(RCBA_BASE_ADDR + ICH9_LPC_RCBA_GCS, val);
>
> +}
>
> +static void test_tco_defaults(void)
> +{
> TestData d;
> d.args = NULL;
> test_init(&d);
> g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_RLD), ==,
>                TCO_RLD_DEFAULT);
> /* TCO_DAT_IN & TCO_DAT_OUT */
> g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_DAT_IN), ==,
>                (TCO_DAT_OUT_DEFAULT << 8) | TCO_DAT_IN_DEFAULT);
> /* TCO1_STS & TCO2_STS */
> g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_base + TCO1_STS), ==,
>                (TCO2_STS_DEFAULT << 16) | TCO1_STS_DEFAULT);
> /* TCO1_CNT & TCO2_CNT */
> g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_base + TCO1_CNT), ==,
>                (TCO2_CNT_DEFAULT << 16) | TCO1_CNT_DEFAULT);
> /* TCO_MESSAGE1 & TCO_MESSAGE2 */
> g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_MESSAGE1), ==,
>                (TCO_MESSAGE2_DEFAULT << 8) | TCO_MESSAGE1_DEFAULT);
> g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_base + TCO_WDCNT), ==,
>                TCO_WDCNT_DEFAULT);
> g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_base + SW_IRQ_GEN), ==,
>                SW_IRQ_GEN_DEFAULT);
> g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_TMR), ==,
>                TCO_TMR_DEFAULT);
> qtest_end();
>
> +}
>
> +static void test_tco_timeout(void)
> +{
> TestData d;
> const uint16_t ticks = TCO_SECS_TO_TICKS(4);
> uint32_t val;
> int ret;
> d.args = NULL;
> test_init(&d);
> stop_tco(&d);
> clear_tco_status(&d);
> reset_on_second_timeout(false);
> set_tco_timeout(&d, ticks);
> load_tco(&d);
> start_tco(&d);
> clock_step(ticks * TCO_TICK_NSEC);
> /* test first timeout */
> val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
> ret = val & TCO_TIMEOUT ? 1 : 0;
> g_assert(ret == 1);
> /* test clearing timeout bit */
> val |= TCO_TIMEOUT;
> qpci_io_writew(d.dev, d.tco_io_base + TCO1_STS, val);
> val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
> ret = val & TCO_TIMEOUT ? 1 : 0;
> g_assert(ret == 0);
> /* test second timeout */
> clock_step(ticks * TCO_TICK_NSEC);
> val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
> ret = val & TCO_TIMEOUT ? 1 : 0;
> g_assert(ret == 1);
> val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
> ret = val & TCO_SECOND_TO_STS ? 1 : 0;
> g_assert(ret == 1);
> stop_tco(&d);
> qtest_end();
>
> +}
>
> +static void test_tco_max_timeout(void)
> +{
> TestData d;
> const uint16_t ticks = 0xffff;
> uint32_t val;
> int ret;
> d.args = NULL;
> test_init(&d);
> stop_tco(&d);
> clear_tco_status(&d);
> reset_on_second_timeout(false);
> set_tco_timeout(&d, ticks);
> load_tco(&d);
> start_tco(&d);
> clock_step(((ticks & TCO_TMR_MASK) - 1) * TCO_TICK_NSEC);
> val = qpci_io_readw(d.dev, d.tco_io_base + TCO_RLD);
> g_assert_cmpint(val & TCO_RLD_MASK, ==, 1);
> val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
> ret = val & TCO_TIMEOUT ? 1 : 0;
> g_assert(ret == 0);
> clock_step(TCO_TICK_NSEC);
> val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
> ret = val & TCO_TIMEOUT ? 1 : 0;
> g_assert(ret == 1);
> stop_tco(&d);
> qtest_end();
>
> +}
>
> +static QDict *get_watchdog_action(void)
> +{
> QDict *ev = qmp("");
> QDict *data;
> g_assert(!strcmp(qdict_get_str(ev, "event"), "WATCHDOG"));
> data = qdict_get_qdict(ev, "data");
> QINCREF(data);
> QDECREF(ev);
> return data;
>
> +}
>
> +static void test_tco_second_timeout_pause(void)
> +{
> TestData td;
> const uint16_t ticks = TCO_SECS_TO_TICKS(32);
> QDict *ad;
> td.args = "-watchdog-action pause";
> test_init(&td);
> stop_tco(&td);
> clear_tco_status(&td);
> reset_on_second_timeout(true);
> set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
> load_tco(&td);
> start_tco(&td);
> clock_step(ticks * TCO_TICK_NSEC * 2);
> ad = get_watchdog_action();
> g_assert(!strcmp(qdict_get_str(ad, "action"), "pause"));
> QDECREF(ad);
> stop_tco(&td);
> qtest_end();
>
> +}
>
> +static void test_tco_second_timeout_reset(void)
> +{
> TestData td;
> const uint16_t ticks = TCO_SECS_TO_TICKS(16);
> QDict *ad;
> td.args = "-watchdog-action reset";
> test_init(&td);
> stop_tco(&td);
> clear_tco_status(&td);
> reset_on_second_timeout(true);
> set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
> load_tco(&td);
> start_tco(&td);
> clock_step(ticks * TCO_TICK_NSEC * 2);
> ad = get_watchdog_action();
> g_assert(!strcmp(qdict_get_str(ad, "action"), "reset"));
> QDECREF(ad);
> stop_tco(&td);
> qtest_end();
>
> +}
>
> +static void test_tco_second_timeout_shutdown(void)
> +{
> TestData td;
> const uint16_t ticks = TCO_SECS_TO_TICKS(128);
> QDict *ad;
> td.args = "-watchdog-action shutdown";
> test_init(&td);
> stop_tco(&td);
> clear_tco_status(&td);
> reset_on_second_timeout(true);
> set_tco_timeout(&td, ticks);
> load_tco(&td);
> start_tco(&td);
> clock_step(ticks * TCO_TICK_NSEC * 2);
> ad = get_watchdog_action();
> g_assert(!strcmp(qdict_get_str(ad, "action"), "shutdown"));
> QDECREF(ad);
> stop_tco(&td);
> qtest_end();
>
> +}
>
> +static void test_tco_second_timeout_none(void)
> +{
> TestData td;
> const uint16_t ticks = TCO_SECS_TO_TICKS(256);
> QDict *ad;
> td.args = "-watchdog-action none";
> test_init(&td);
> stop_tco(&td);
> clear_tco_status(&td);
> reset_on_second_timeout(true);
> set_tco_timeout(&td, ticks);
> load_tco(&td);
> start_tco(&td);
> clock_step(ticks * TCO_TICK_NSEC * 2);
> ad = get_watchdog_action();
> g_assert(!strcmp(qdict_get_str(ad, "action"), "none"));
> QDECREF(ad);
> stop_tco(&td);
> qtest_end();
>
> +}
>
> +static void test_tco_ticks_counter(void)
> +{
> TestData d;
> uint16_t ticks = TCO_SECS_TO_TICKS(8);
> uint16_t rld;
> d.args = NULL;
> test_init(&d);
> stop_tco(&d);
> clear_tco_status(&d);
> reset_on_second_timeout(false);
> set_tco_timeout(&d, ticks);
> load_tco(&d);
> start_tco(&d);
> do {
>    rld = qpci_io_readw(d.dev, d.tco_io_base + TCO_RLD) & TCO_RLD_MASK;
>    g_assert_cmpint(rld, ==, ticks);
>    clock_step(TCO_TICK_NSEC);
>    ticks--;
> } while (!(qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS) & TCO_TIMEOUT));
> stop_tco(&d);
> qtest_end();
>
> +}
>
> +static void test_tco_lock_bit(void)
> +{
> TestData d;
> uint16_t val;
> d.args = NULL;
> test_init(&d);
> val = TCO_LOCK;
> qpci_io_writew(d.dev, d.tco_io_base + TCO1_CNT, val);
> val &= ~TCO_LOCK;
> qpci_io_writew(d.dev, d.tco_io_base + TCO1_CNT, val);
> g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO1_CNT), ==,
>                TCO_LOCK);
> qtest_end();
>
> +}
>
> +int main(int argc, char **argv)
> +{
> (void)test_tco_ticks_counter;
> g_test_init(&argc, &argv, NULL);
> qtest_add_func("tco/defaults", test_tco_defaults);
> qtest_add_func("tco/timeout/no_action", test_tco_timeout);
> qtest_add_func("tco/timeout/no_action/max", test_tco_max_timeout);
> qtest_add_func("tco/second_timeout/pause", test_tco_second_timeout_pause);
> qtest_add_func("tco/second_timeout/reset", test_tco_second_timeout_reset);
> qtest_add_func("tco/second_timeout/shutdown",
>               test_tco_second_timeout_shutdown);
> qtest_add_func("tco/second_timeout/none", test_tco_second_timeout_none);
> qtest_add_func("tco/counter", test_tco_ticks_counter);
> qtest_add_func("tco/lock_bit", test_tco_lock_bit);
> return g_test_run();
>
> +}

Looks good.

If you want, you can add a test for the reserved bits of the various
registers.

Paolo