On Thu, Aug 08, 2013 at 09:57:39AM +0200, Gerd Hoffmann wrote:
>> Huh? The 32bit window is sized according to the installed memory.
>> logic is in seabios and you'll try to move it to qemu, using pci-info.
>> It wasn't in qemu before ...
> The logic is in hw/i386/pc_piix.c and always was.
What exactly you are refering to?
pc_init1 which picks addresses and passes them on to
>> It is the job of the firmware to initialize the hardware.
IMO it should
>> work that way on qemu too to mimic real hardware.
> That's exactly what we have. However QEMU is the one that knows
> how hardware is configured (e.g. where's the
> PCI hole), so we report that to bios.
Memory configuration is in the cmos, firmware can figure where it can
place pci devices from that. There is no need for a new interface.
The assumption being that whatever is not memory is PCI?
I'm not sure that's right.
>> The firmware can initialize the hardware as it likes. For
the most part
>> the OS can simply read the configuration from the pci config space.
> Only for some hardware (Q35).
i440fx_init gets pci_hole_start and pci_hole_end.
This is in hardware (QEMU) and not configurable by firmware.
>> (3) mmconf xbar start (MCFG, q35 only, at 0xb0000000
>> (4) pmbase (FADT, at 0xb000 now).
>> Especially 3+4 tend to be compile-time constants in the firmware as they
>> are needed very early in the setup process.
> So we don't need them in pci-config, just stick constant in ACPI.
I don't want them be constant. I want allow the firmware pick them.
Our mmconfig xbar is 256M and can handle 256 busses. I'd like to have
the option to reduce that to 64M and place it somewhere else.
Also coreboot and seabios use different values for pmbase. coreboot on
q35 maps the pmbase below 0x1000. Which surely makes sense. When we
don't place chipset stuff at 0xb000 we can assign the 0xb000->0xbfff
window to a pci bridge instead.
> Another issue is where to start/end the 32 bit window for PIIX.
> That's really a PV thing for QEMU, hardcoded at the moment in bios
> and QEMU.
Hmm? --verbose please. What issue to we have with the 32bit window?
I refer to PCI hole starting at 0xe0000000.