SeaBIOS

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Re: [SeaBIOS] How to boot USB 3.0 devices with SeaBIOS
by diffusae 10 Oct '17

10 Oct '17

Hello, thanks for help. On 03.10.2017 18:15, Kevin O'Connor wrote: > Can you recompile SeaBIOS with the patch below applied? I don't have > a good way to test this, but I'm hopeful it will help detect the USB2 > disconnect and avoid the controller hang. I've applied the patch. But maybe I need some help with this. Coreboot will always overwrite these changes. error: Your local changes to the following files would be overwritten by checkout: src/hw/usb-xhci.c Please, commit your changes or stash them before you can switch branches. Aborting I've tried stash, but that really won't work. I went back to version rel-1.10.0-70-gf3d2a15, applied the patch and copy it to the master branch. Don't know, if I've done a "checkout -- <file>" or something else, but after all, I got it working and can compile with the patch. But I don't know how. :-) Now, I am on version: rel-1.10.0-72-gf703604-dirty-20171008_051220-x220. The controller doesn't hang any more and the device is detected at boot. I'm not sure, if it's only USB2. Because of the verbose logging, the cbmem console log is truncated. I've attached the debug files. Hopefully you can commit you're changes. If you need further testing, please send a message. Best regards, Reiner --

3 3

Jenkins build is back to normal : seabios #270
by Jenkins Build Host 06 Oct '17

06 Oct '17

See <http://jenkins.xeni.kraxel.org:8080/job/seabios/270/display/redirect?page=c…>

1 0

[PATCH] xhci: Build TRBs directly in xhci_trb_queue()
by Kevin O'Connor 06 Oct '17

06 Oct '17

Use the logic for building a 'struct xhci_trb' that was in xhci_xfer_queue() up so that command and ring TRBs can also use that functionality. This eliminates the need to manually generate the xhci_trb struct from those code paths. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/hw/usb-xhci.c | 162 +++++++++++++++++++----------------------------------- 1 file changed, 57 insertions(+), 105 deletions(-) diff --git a/src/hw/usb-xhci.c b/src/hw/usb-xhci.c index 50b3b86..a92a162 100644 --- a/src/hw/usb-xhci.c +++ b/src/hw/usb-xhci.c @@ -641,13 +641,16 @@ xhci_setup(void) * End point communication ****************************************************************/ +// Signal the hardware to process events on a TRB ring static void xhci_doorbell(struct usb_xhci_s *xhci, u32 slotid, u32 value) { + dprintf(5, "%s: slotid %d, epid %d\n", __func__, slotid, value); struct xhci_db *db = xhci->db; void *addr = &db[slotid].doorbell; writel(addr, value); } +// Dequeue events on the XHCI command ring generated by the hardware static void xhci_process_events(struct usb_xhci_s *xhci) { struct xhci_ring *evts = xhci->evts; @@ -712,6 +715,7 @@ static void xhci_process_events(struct usb_xhci_s *xhci) } } +// Check if a ring has any pending TRBs static int xhci_ring_busy(struct xhci_ring *ring) { u32 eidx = ring->eidx; @@ -719,6 +723,7 @@ static int xhci_ring_busy(struct xhci_ring *ring) return (eidx != nidx); } +// Wait for a ring to empty (all TRBs processed by hardware) static int xhci_event_wait(struct usb_xhci_s *xhci, struct xhci_ring *ring, u32 timeout) @@ -739,69 +744,54 @@ static int xhci_event_wait(struct usb_xhci_s *xhci, } } -static void xhci_trb_queue(struct xhci_ring *ring, - struct xhci_trb *trb) +// Add a TRB to the given ring +static void xhci_trb_fill(struct xhci_ring *ring + , void *data, u32 xferlen, u32 flags) { - u32 nidx = ring->nidx; - u32 cs = ring->cs; - struct xhci_trb *dst; - u32 control; - - if (nidx == XHCI_RING_ITEMS-1) { - dst = ring->ring + nidx; - control = (TR_LINK << 10); // trb type - control |= TRB_LK_TC; - control |= (cs ? TRB_C : 0); - dst->ptr_low = (u32)&ring[0]; + struct xhci_trb *dst = &ring->ring[ring->nidx]; + if (flags & TRB_TR_IDT) { + memcpy(&dst->ptr_low, data, xferlen); + } else { + dst->ptr_low = (u32)data; dst->ptr_high = 0; - dst->status = 0; - dst->control = control; - nidx = 0; - cs = cs ? 0 : 1; - ring->nidx = nidx; - ring->cs = cs; + } + dst->status = xferlen; + dst->control = flags | (ring->cs ? TRB_C : 0); +} +// Queue a TRB onto a ring, wrapping ring as needed +static void xhci_trb_queue(struct xhci_ring *ring, + void *data, u32 xferlen, u32 flags) +{ + if (ring->nidx >= ARRAY_SIZE(ring->ring) - 1) { + xhci_trb_fill(ring, ring->ring, 0, (TR_LINK << 10) | TRB_LK_TC); + ring->nidx = 0; + ring->cs ^= 1; dprintf(5, "%s: ring %p [linked]\n", __func__, ring); } - dst = ring->ring + nidx; - control = trb->control | (cs ? TRB_C : 0); - - dst->ptr_low = trb->ptr_low; - dst->ptr_high = trb->ptr_high; - dst->status = trb->status; - dst->control = control; - nidx++; - ring->nidx = nidx; - + xhci_trb_fill(ring, data, xferlen, flags); + ring->nidx++; dprintf(5, "%s: ring %p [nidx %d, len %d]\n", - __func__, ring, nidx, - trb->status & 0xffff); + __func__, ring, ring->nidx, xferlen); } -static int xhci_cmd_submit(struct usb_xhci_s *xhci, - struct xhci_trb *cmd) +// Submit a command to the xhci controller ring +static int xhci_cmd_submit(struct usb_xhci_s *xhci, struct xhci_inctx *inctx + , u32 flags) { - int rc; - mutex_lock(&xhci->cmds->lock); - xhci_trb_queue(xhci->cmds, cmd); + xhci_trb_queue(xhci->cmds, inctx, 0, flags); xhci_doorbell(xhci, 0, 0); - rc = xhci_event_wait(xhci, xhci->cmds, 1000); + int rc = xhci_event_wait(xhci, xhci->cmds, 1000); mutex_unlock(&xhci->cmds->lock); return rc; } static int xhci_cmd_enable_slot(struct usb_xhci_s *xhci) { - struct xhci_trb cmd = { - .ptr_low = 0, - .ptr_high = 0, - .status = 0, - .control = (CR_ENABLE_SLOT << 10) - }; dprintf(3, "%s:\n", __func__); - int cc = xhci_cmd_submit(xhci, &cmd); + int cc = xhci_cmd_submit(xhci, NULL, CR_ENABLE_SLOT << 10); if (cc != CC_SUCCESS) return -1; return (xhci->cmds->evt.control >> 24) & 0xff; @@ -809,55 +799,34 @@ static int xhci_cmd_enable_slot(struct usb_xhci_s *xhci) static int xhci_cmd_disable_slot(struct usb_xhci_s *xhci, u32 slotid) { - struct xhci_trb cmd = { - .ptr_low = 0, - .ptr_high = 0, - .status = 0, - .control = (slotid << 24) | (CR_DISABLE_SLOT << 10) - }; dprintf(3, "%s: slotid %d\n", __func__, slotid); - return xhci_cmd_submit(xhci, &cmd); + return xhci_cmd_submit(xhci, NULL, (CR_DISABLE_SLOT << 10) | (slotid << 24)); } static int xhci_cmd_address_device(struct usb_xhci_s *xhci, u32 slotid , struct xhci_inctx *inctx) { - struct xhci_trb cmd = { - .ptr_low = (u32)inctx, - .ptr_high = 0, - .status = 0, - .control = (slotid << 24) | (CR_ADDRESS_DEVICE << 10) - }; dprintf(3, "%s: slotid %d\n", __func__, slotid); - return xhci_cmd_submit(xhci, &cmd); + return xhci_cmd_submit(xhci, inctx + , (CR_ADDRESS_DEVICE << 10) | (slotid << 24)); } static int xhci_cmd_configure_endpoint(struct usb_xhci_s *xhci, u32 slotid , struct xhci_inctx *inctx) { - struct xhci_trb cmd = { - .ptr_low = (u32)inctx, - .ptr_high = 0, - .status = 0, - .control = (slotid << 24) | (CR_CONFIGURE_ENDPOINT << 10) - }; dprintf(3, "%s: slotid %d, add 0x%x, del 0x%x\n", __func__, slotid, inctx->add, inctx->del); - return xhci_cmd_submit(xhci, &cmd); + return xhci_cmd_submit(xhci, inctx + , (CR_CONFIGURE_ENDPOINT << 10) | (slotid << 24)); } static int xhci_cmd_evaluate_context(struct usb_xhci_s *xhci, u32 slotid , struct xhci_inctx *inctx) { - struct xhci_trb cmd = { - .ptr_low = (u32)inctx, - .ptr_high = 0, - .status = 0, - .control = (slotid << 24) | (CR_EVALUATE_CONTEXT << 10) - }; dprintf(3, "%s: slotid %d, add 0x%x, del 0x%x\n", __func__, slotid, inctx->add, inctx->del); - return xhci_cmd_submit(xhci, &cmd); + return xhci_cmd_submit(xhci, inctx + , (CR_EVALUATE_CONTEXT << 10) | (slotid << 24)); } static struct xhci_inctx * @@ -1092,37 +1061,29 @@ xhci_realloc_pipe(struct usbdevice_s *usbdev, struct usb_pipe *upipe return upipe; } -static void xhci_xfer_queue(struct xhci_pipe *pipe, - void *data, int datalen, u32 flags) -{ - struct xhci_trb trb; - memset(&trb, 0, sizeof(trb)); - if (flags & TRB_TR_IDT) - memcpy(&trb.ptr_low, data, datalen); - else - trb.ptr_low = (u32)data; - trb.status = datalen; - trb.control = flags; - xhci_trb_queue(&pipe->reqs, &trb); -} - -static void xhci_xfer_kick(struct xhci_pipe *pipe) +static void xhci_xfer_setup(struct xhci_pipe *pipe, int dir, void *cmd + , void *data, int datalen) { struct usb_xhci_s *xhci = container_of( pipe->pipe.cntl, struct usb_xhci_s, usb); - u32 slotid = pipe->slotid; - u32 epid = pipe->epid; - - dprintf(5, "%s: ring %p, slotid %d, epid %d\n", - __func__, &pipe->reqs, slotid, epid); - xhci_doorbell(xhci, slotid, epid); + xhci_trb_queue(&pipe->reqs, cmd, USB_CONTROL_SETUP_SIZE + , (TR_SETUP << 10) | TRB_TR_IDT + | ((datalen ? (dir ? 3 : 2) : 0) << 16)); + if (datalen) + xhci_trb_queue(&pipe->reqs, data, datalen, (TR_DATA << 10) + | ((dir ? 1 : 0) << 16)); + xhci_trb_queue(&pipe->reqs, NULL, 0, (TR_STATUS << 10) | TRB_TR_IOC + | ((dir ? 0 : 1) << 16)); + xhci_doorbell(xhci, pipe->slotid, pipe->epid); } static void xhci_xfer_normal(struct xhci_pipe *pipe, void *data, int datalen) { - xhci_xfer_queue(pipe, data, datalen, (TR_NORMAL << 10) | TRB_TR_IOC); - xhci_xfer_kick(pipe); + struct usb_xhci_s *xhci = container_of( + pipe->pipe.cntl, struct usb_xhci_s, usb); + xhci_trb_queue(&pipe->reqs, data, datalen, (TR_NORMAL << 10) | TRB_TR_IOC); + xhci_doorbell(xhci, pipe->slotid, pipe->epid); } int @@ -1140,16 +1101,7 @@ xhci_send_pipe(struct usb_pipe *p, int dir, const void *cmd if (req->bRequest == USB_REQ_SET_ADDRESS) // Set address command sent during xhci_alloc_pipe. return 0; - - xhci_xfer_queue(pipe, (void*)req, USB_CONTROL_SETUP_SIZE - , (TR_SETUP << 10) | TRB_TR_IDT - | ((datalen ? (dir ? 3 : 2) : 0) << 16)); - if (datalen) - xhci_xfer_queue(pipe, data, datalen, (TR_DATA << 10) - | ((dir ? 1 : 0) << 16)); - xhci_xfer_queue(pipe, NULL, 0, (TR_STATUS << 10) | TRB_TR_IOC - | ((dir ? 0 : 1) << 16)); - xhci_xfer_kick(pipe); + xhci_xfer_setup(pipe, dir, (void*)req, data, datalen); } else { xhci_xfer_normal(pipe, data, datalen); } -- 2.9.5

1 1

[PATCH] nvme: fix out of memory behavior
by Julian Stecklina 06 Oct '17

06 Oct '17

If the allocation of I/O queues ran out of memory, the code would fail to detect that and happily use these queues at address zero. For me this happens for systems with more than 7 NVMe controllers. Fix the out of memory handling to gracefully handle this case. Signed-off-by: Julian Stecklina <jsteckli(a)amazon.de> --- src/hw/nvme.c | 147 ++++++++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 111 insertions(+), 36 deletions(-) diff --git a/src/hw/nvme.c b/src/hw/nvme.c index 93c25f5..946487f 100644 --- a/src/hw/nvme.c +++ b/src/hw/nvme.c @@ -38,29 +38,43 @@ nvme_init_queue_common(struct nvme_ctrl *ctrl, struct nvme_queue *q, u16 q_idx, q->mask = length - 1; } -static void +static int nvme_init_sq(struct nvme_ctrl *ctrl, struct nvme_sq *sq, u16 q_idx, u16 length, struct nvme_cq *cq) { nvme_init_queue_common(ctrl, &sq->common, q_idx, length); sq->sqe = zalloc_page_aligned(&ZoneHigh, sizeof(*sq->sqe) * length); + + if (!sq->sqe) { + warn_noalloc(); + return -1; + } + dprintf(3, "sq %p q_idx %u sqe %p\n", sq, q_idx, sq->sqe); sq->cq = cq; sq->head = 0; sq->tail = 0; + + return 0; } -static void +static int nvme_init_cq(struct nvme_ctrl *ctrl, struct nvme_cq *cq, u16 q_idx, u16 length) { nvme_init_queue_common(ctrl, &cq->common, q_idx, length); cq->cqe = zalloc_page_aligned(&ZoneHigh, sizeof(*cq->cqe) * length); + if (!cq->cqe) { + warn_noalloc(); + return -1; + } cq->head = 0; /* All CQE phase bits are initialized to zero. This means initially we wait for the host controller to set these to 1. */ cq->phase = 1; + + return 0; } static int @@ -76,7 +90,6 @@ nvme_is_cqe_success(struct nvme_cqe const *cqe) return ((cqe->status >> 1) & 0xFF) == 0; } - static struct nvme_cqe nvme_error_cqe(void) { @@ -278,22 +291,44 @@ nvme_probe_ns(struct nvme_ctrl *ctrl, struct nvme_namespace *ns, u32 ns_id) dprintf(3, "%s", desc); boot_add_hd(&ns->drive, desc, bootprio_find_pci_device(ctrl->pci)); - free_buffer: +free_buffer: free (id); - } +} + + +/* Release memory allocated for a completion queue */ +static void +nvme_destroy_cq(struct nvme_cq *cq) +{ + free(cq->cqe); + cq->cqe = NULL; +} + +/* Release memory allocated for a submission queue */ +static void +nvme_destroy_sq(struct nvme_sq *sq) +{ + free(sq->sqe); + sq->sqe = NULL; +} /* Returns 0 on success. */ static int nvme_create_io_cq(struct nvme_ctrl *ctrl, struct nvme_cq *cq, u16 q_idx) { + int rc; struct nvme_sqe *cmd_create_cq; - nvme_init_cq(ctrl, cq, q_idx, NVME_PAGE_SIZE / sizeof(struct nvme_cqe)); + rc = nvme_init_cq(ctrl, cq, q_idx, NVME_PAGE_SIZE / sizeof(struct nvme_cqe)); + if (rc) { + goto err; + } + cmd_create_cq = nvme_get_next_sqe(&ctrl->admin_sq, NVME_SQE_OPC_ADMIN_CREATE_IO_CQ, NULL, cq->cqe); if (!cmd_create_cq) { - return -1; + goto err_destroy_cq; } cmd_create_cq->dword[10] = (cq->common.mask << 16) | (q_idx >> 1); @@ -307,24 +342,34 @@ nvme_create_io_cq(struct nvme_ctrl *ctrl, struct nvme_cq *cq, u16 q_idx) dprintf(2, "create io cq failed: %08x %08x %08x %08x\n", cqe.dword[0], cqe.dword[1], cqe.dword[2], cqe.dword[3]); - return -1; + goto err_destroy_cq; } return 0; + +err_destroy_cq: + nvme_destroy_cq(cq); +err: + return -1; } /* Returns 0 on success. */ static int nvme_create_io_sq(struct nvme_ctrl *ctrl, struct nvme_sq *sq, u16 q_idx, struct nvme_cq *cq) { + int rc; struct nvme_sqe *cmd_create_sq; - nvme_init_sq(ctrl, sq, q_idx, NVME_PAGE_SIZE / sizeof(struct nvme_cqe), cq); + rc = nvme_init_sq(ctrl, sq, q_idx, NVME_PAGE_SIZE / sizeof(struct nvme_cqe), cq); + if (rc) { + goto err; + } + cmd_create_sq = nvme_get_next_sqe(&ctrl->admin_sq, NVME_SQE_OPC_ADMIN_CREATE_IO_SQ, NULL, sq->sqe); if (!cmd_create_sq) { - return -1; + goto err_destroy_sq; } cmd_create_sq->dword[10] = (sq->common.mask << 16) | (q_idx >> 1); @@ -339,10 +384,15 @@ nvme_create_io_sq(struct nvme_ctrl *ctrl, struct nvme_sq *sq, u16 q_idx, struct if (!nvme_is_cqe_success(&cqe)) { dprintf(2, "create io sq failed: %08x %08x %08x %08x\n", cqe.dword[0], cqe.dword[1], cqe.dword[2], cqe.dword[3]); - return -1; + goto err_destroy_sq; } return 0; + +err_destroy_sq: + nvme_destroy_sq(sq); +err: + return -1; } /* Reads count sectors into buf. Returns DISK_RET_*. The buffer cannot cross @@ -384,17 +434,28 @@ nvme_io_readwrite(struct nvme_namespace *ns, u64 lba, char *buf, u16 count, return DISK_RET_SUCCESS; } - static int nvme_create_io_queues(struct nvme_ctrl *ctrl) { if (nvme_create_io_cq(ctrl, &ctrl->io_cq, 3)) - return -1; + goto err; if (nvme_create_io_sq(ctrl, &ctrl->io_sq, 2, &ctrl->io_cq)) - return -1; + goto err_free_cq; return 0; + + err_free_cq: + nvme_destroy_cq(&ctrl->io_cq); + err: + return -1; +} + +static void +nvme_destroy_io_queues(struct nvme_ctrl *ctrl) +{ + nvme_destroy_sq(&ctrl->io_sq); + nvme_destroy_cq(&ctrl->io_cq); } /* Waits for CSTS.RDY to match rdy. Returns 0 on success. */ @@ -426,6 +487,8 @@ nvme_wait_csts_rdy(struct nvme_ctrl *ctrl, unsigned rdy) static int nvme_controller_enable(struct nvme_ctrl *ctrl) { + int rc; + pci_enable_busmaster(ctrl->pci); /* Turn the controller off. */ @@ -437,18 +500,21 @@ nvme_controller_enable(struct nvme_ctrl *ctrl) ctrl->doorbell_stride = 4U << ((ctrl->reg->cap >> 32) & 0xF); - nvme_init_cq(ctrl, &ctrl->admin_cq, 1, - NVME_PAGE_SIZE / sizeof(struct nvme_cqe)); + rc = nvme_init_cq(ctrl, &ctrl->admin_cq, 1, + NVME_PAGE_SIZE / sizeof(struct nvme_cqe)); + if (rc) { + return -1; + } - nvme_init_sq(ctrl, &ctrl->admin_sq, 0, - NVME_PAGE_SIZE / sizeof(struct nvme_sqe), &ctrl->admin_cq); + rc = nvme_init_sq(ctrl, &ctrl->admin_sq, 0, + NVME_PAGE_SIZE / sizeof(struct nvme_sqe), &ctrl->admin_cq); + if (rc) { + goto err_destroy_admin_cq; + } ctrl->reg->aqa = ctrl->admin_cq.common.mask << 16 | ctrl->admin_sq.common.mask; - /* Create the admin queue pair */ - if (!ctrl->admin_sq.sqe || !ctrl->admin_cq.cqe) goto out_of_memory; - ctrl->reg->asq = (u32)ctrl->admin_sq.sqe; ctrl->reg->acq = (u32)ctrl->admin_cq.cqe; @@ -460,8 +526,9 @@ nvme_controller_enable(struct nvme_ctrl *ctrl) if (nvme_wait_csts_rdy(ctrl, 1)) { dprintf(2, "NVMe fatal error while enabling controller\n"); - goto failed; + goto err_destroy_admin_sq; } + /* The admin queue is set up and the controller is ready. Let's figure out what namespaces we have. */ @@ -469,10 +536,9 @@ nvme_controller_enable(struct nvme_ctrl *ctrl) if (!identify) { dprintf(2, "NVMe couldn't identify controller.\n"); - goto failed; + goto err_destroy_admin_sq; } - /* TODO Print model/serial info. */ dprintf(3, "NVMe has %u namespace%s.\n", identify->nn, (identify->nn == 1) ? "" : "s"); @@ -482,11 +548,14 @@ nvme_controller_enable(struct nvme_ctrl *ctrl) if ((ctrl->ns_count == 0) || nvme_create_io_queues(ctrl)) { /* No point to continue, if the controller says it doesn't have namespaces or we couldn't create I/O queues. */ - goto failed; + goto err_destroy_admin_sq; } ctrl->ns = malloc_fseg(sizeof(*ctrl->ns) * ctrl->ns_count); - if (!ctrl->ns) goto out_of_memory; + if (!ctrl->ns) { + warn_noalloc(); + goto err_destroy_ioq; + } memset(ctrl->ns, 0, sizeof(*ctrl->ns) * ctrl->ns_count); /* Populate namespace IDs */ @@ -498,12 +567,12 @@ nvme_controller_enable(struct nvme_ctrl *ctrl) dprintf(3, "NVMe initialization complete!\n"); return 0; - out_of_memory: - warn_noalloc(); - failed: - free(ctrl->admin_sq.sqe); - free(ctrl->admin_cq.cqe); - free(ctrl->ns); + err_destroy_ioq: + nvme_destroy_io_queues(ctrl); + err_destroy_admin_sq: + nvme_destroy_sq(&ctrl->admin_sq); + err_destroy_admin_cq: + nvme_destroy_cq(&ctrl->admin_cq); return -1; } @@ -524,13 +593,13 @@ nvme_controller_setup(void *opaque) if (~reg->cap & NVME_CAP_CSS_NVME) { dprintf(3, "Controller doesn't speak NVMe command set. Skipping.\n"); - return; + goto err; } struct nvme_ctrl *ctrl = malloc_high(sizeof(*ctrl)); if (!ctrl) { warn_noalloc(); - return; + goto err; } memset(ctrl, 0, sizeof(*ctrl)); @@ -539,9 +608,15 @@ nvme_controller_setup(void *opaque) ctrl->pci = pci; if (nvme_controller_enable(ctrl)) { - /* Initialization failed */ - free(ctrl); + goto err_free_ctrl; } + + return; + + err_free_ctrl: + free(ctrl); + err: + dprintf(2, "Failed to enable NVMe controller.\n"); } // Locate and init NVMe controllers -- 2.7.4

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Re: [SeaBIOS] How to build seabios(coreboot style) with manually specified entry_elf() address ?
by Tang Rong 04 Oct '17

04 Oct '17

Modify the onboard firmware by myself is too risky. If anything goes wrong with my customized depthcharge, I'll need to reprogram the SPI, right? Any way to test it on qemu? On Wed, Oct 4, 2017 at 11:02 AM, Matt DeVillier <matt.devillier(a)gmail.com> wrote: > given what you're trying to do, I'd think it would be easier to modify > depthcharge to jump to RW_LEGACY later / after doing the other init normally > done when booting ChromeOS, than to try and shoehorn SeaBIOS into something > depthcharge would load like a kernel > > On Tue, Oct 3, 2017 at 9:42 PM, Tang Rong <phtr071(a)gmail.com> wrote: >> >> Hi Matt, we chated about kexec booting chromeos for Acer C710 on IRC, >> thanks a lot for your help. >> >> I digged to into depthcharge code, and found they did quite a lot of >> work, including patching the SMBIOS for fwid, redirecting ehci to >> xhci, etc. However, SeaBios on RW_LEGACY can not enjoy these work as >> legacy mode got started very early. In addition, flash >> seabios/tianocore on ssd (pretending to be linux kernel) would be much >> safer option. > >

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Re: [SeaBIOS] How to build seabios(coreboot style) with manually specified entry_elf() address ?
by Matt DeVillier 04 Oct '17

04 Oct '17

given what you're trying to do, I'd think it would be easier to modify depthcharge to jump to RW_LEGACY later / after doing the other init normally done when booting ChromeOS, than to try and shoehorn SeaBIOS into something depthcharge would load like a kernel On Tue, Oct 3, 2017 at 9:42 PM, Tang Rong <phtr071(a)gmail.com> wrote: > Hi Matt, we chated about kexec booting chromeos for Acer C710 on IRC, > thanks a lot for your help. > > I digged to into depthcharge code, and found they did quite a lot of > work, including patching the SMBIOS for fwid, redirecting ehci to > xhci, etc. However, SeaBios on RW_LEGACY can not enjoy these work as > legacy mode got started very early. In addition, flash > seabios/tianocore on ssd (pretending to be linux kernel) would be much > safer option. >

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Re: [SeaBIOS] How to build seabios(coreboot style) with manually specified entry_elf() address ?
by Tang Rong 04 Oct '17

04 Oct '17

Hi Matt, we chated about kexec booting chromeos for Acer C710 on IRC, thanks a lot for your help. I digged to into depthcharge code, and found they did quite a lot of work, including patching the SMBIOS for fwid, redirecting ehci to xhci, etc. However, SeaBios on RW_LEGACY can not enjoy these work as legacy mode got started very early. In addition, flash seabios/tianocore on ssd (pretending to be linux kernel) would be much safer option.

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Re: [SeaBIOS] How to build seabios(coreboot style) with manually specified entry_elf() address ?
by Matt DeVillier 04 Oct '17

04 Oct '17

what device are you targeting? John Lewis and I both offer firmware for Intel-based ChromeOS devices that boots directly to either SeaBIOS (for legacy boot) or Tianocore (for UEFI boot). If you just need SeaBIOS as a RW_LEGACY payload which will be loaded by depthcharge, we offer that too. See: https://mrchromebox.tech https://johnlewis.ie cheers, Matt On Tue, Oct 3, 2017 at 9:02 PM, Tang Rong <phtr071(a)gmail.com> wrote: > Hi SeaBios developers: > > I would like to build SeaBios as payload of chromebook Depthcharge > instead of coreboot, because Depthcharge seems to have some additional > device initialization on per-board basis. I did some search and found > SeaBios could be used as Grub2 payload, so I guess this is not mission > impossible. > > According to google's doc here: > http://dev.chromium.org/chromium-os/developer-information-for-chrome-os- > devices/custom-firmware > , depthcharge can copy any 32-bit blob into 0x100000, and directly > jump to it. So I will need the entry_elf to be 0x100000, and in > addition, anything instruction below 0x100000 should be safely > descarded without impacting seabios's functionality(because > depthcharge always jump to the beginning of the blob). > > Is it possible to build such a seabios raw blob with entry point as > 0x100000? If not, maybe I can use some 2-step jump: let depthcharge > jump to 0x100000 first, then jump to the real entry_elf? As I know > nothing about linkerscript or assembly, maybe some of you could help > me figure out. > > Thanks! > > _______________________________________________ > SeaBIOS mailing list > SeaBIOS(a)seabios.org > https://mail.coreboot.org/mailman/listinfo/seabios >

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How to build seabios(coreboot style) with manually specified entry_elf() address ?
by Tang Rong 04 Oct '17

04 Oct '17

Hi SeaBios developers: I would like to build SeaBios as payload of chromebook Depthcharge instead of coreboot, because Depthcharge seems to have some additional device initialization on per-board basis. I did some search and found SeaBios could be used as Grub2 payload, so I guess this is not mission impossible. According to google's doc here: http://dev.chromium.org/chromium-os/developer-information-for-chrome-os-dev… , depthcharge can copy any 32-bit blob into 0x100000, and directly jump to it. So I will need the entry_elf to be 0x100000, and in addition, anything instruction below 0x100000 should be safely descarded without impacting seabios's functionality(because depthcharge always jump to the beginning of the blob). Is it possible to build such a seabios raw blob with entry point as 0x100000? If not, maybe I can use some 2-step jump: let depthcharge jump to 0x100000 first, then jump to the real entry_elf? As I know nothing about linkerscript or assembly, maybe some of you could help me figure out. Thanks!

1 0

How to build seabios(coreboot style) with manually specified entry_elf() address ?
by Tang Rong 03 Oct '17

03 Oct '17

1 0

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