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[PATCH v7 0/4] Generic PCIE-PCI Bridge
by Aleksandr Bezzubikov 20 Sep '17

20 Sep '17

This series introduces a new device - Generic PCI Express to PCI bridge, and also makes all necessary changes to enable hotplug of the bridge itself and any device into the bridge. Changes v6->v7: Change IO/MEM/PREF reservation properties type to SIZE. Changes v5->v6: 1. Fix indentation in the cap creation function (addresses Marcel's comment) 2. Simplify capability pref_mem_* fields assignment (addresses Marcel's comment) 3. Documentation fixes: - fix mutually exclusive fields definition (addresses Laszlo's comment) - fix pcie-pci-bridge usage example (addresses Marcel's comment) Changes v4->v5: 1. Change PCIE-PCI Bridge license (addresses Marcel's comment) 2. The capability layout changes (adress Laszlo' comments): - separate pref_mem into pref_mem_32 and pref_mem_64 fields (SeaBIOS side has the same changes) - accordingly change the Generic Root Port's properties 3. Do not add the capability to the root port if no valid values are provided (adresses Michael's comment) 4. Rename the capability type to 'RESOURCE_RESERVE' (addresses Marcel's comment) 5. Remove shpc_present check function (addresses Marcel's comment) 6. Fix the 4th patch message (adresses Michael's comment) 7. Patch for SHPC enabling in _OSC method has been already merged Changes v3->v4: 1. PCIE-PCI Bridge device: "msi_enable"->"msi", "shpc"->"shpc_bar", remove local_err, make "msi" property OnOffAuto, shpc_present() is still here to avoid SHPC_VMSTATE refactoring (address Marcel's comments). 2. Change QEMU PCI capability layout (SeaBIOS side has the same changes): - change reservation fields types: bus_res - uint32_t, others - uint64_t - rename 'non_pref' and 'pref' fields - interpret -1 value as 'ignore' 3. Use parent_realize in Generic PCI Express Root Port properly. 4. Fix documentation: fully replace the DMI-PCI bridge references with the new PCIE-PCI bridge, "PCIE"->"PCI Express", small mistakes and typos - address Laszlo's and Marcel's comments. 5. Rename QEMU PCI cap creation fucntion - addresses Marcel's comment. Changes v2->v3: (0). 'do_not_use' capability field flag is still _not_ in here since we haven't come to consesus on it yet. 1. Merge commits 5 (bus_reserve property creation) and 6 (property usage) together - addresses Michael's comment. 2. Add 'bus_reserve' property and QEMU PCI capability only to Generic PCIE Root Port - addresses Michael's and Marcel's comments. 3. Change 'bus_reserve' property's default value to 0 - addresses Michael's comment. 4. Rename QEMU bridge-specific PCI capability creation function - addresses Michael's comment. 5. Init the whole QEMU PCI capability with zeroes - addresses Michael's and Laszlo's comments. 6. Change QEMU PCI capability layout (SeaBIOS side has the same changes) - add 'type' field to distinguish multiple RedHat-specific capabilities - addresses Michael's comment - do not mimiс PCI Config space register layout, but use mutually exclusive differently sized fields for IO and prefetchable memory limits - addresses Laszlo's comment 7. Correct error handling in PCIE-PCI bridge realize function. 8. Replace a '2' constant with PCI_CAP_FLAGS in the capability creation function - addresses Michael's comment. 9. Remove a comment on _OSC which isn't correct anymore - address Marcel's comment. 10. Add documentation for the Generic PCIE-PCI Bridge and QEMU PCI capability - addresses Michael's comment. Changes v1->v2: 1. Enable SHPC for the bridge. 2. Enable SHPC support for the Q35 machine (ACPI stuff). 3. Introduce PCI capability to help firmware on the system init. This allows the bridge to be hotpluggable. Now it's supported only for pcie-root-port. Now it's supposed to used with SeaBIOS only, look at the SeaBIOS corresponding series "Allow RedHat PCI bridges reserve more buses than necessary during init". Aleksandr Bezzubikov (4): hw/pci: introduce pcie-pci-bridge device hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware hw/pci: add QEMU-specific PCI capability to the Generic PCI Express Root Port docs: update documentation considering PCIE-PCI bridge docs/pcie.txt | 49 +++++----- docs/pcie_pci_bridge.txt | 114 ++++++++++++++++++++++ hw/pci-bridge/Makefile.objs | 2 +- hw/pci-bridge/gen_pcie_root_port.c | 36 +++++++ hw/pci-bridge/pcie_pci_bridge.c | 192 +++++++++++++++++++++++++++++++++++++ hw/pci/pci_bridge.c | 46 +++++++++ include/hw/pci/pci.h | 1 + include/hw/pci/pci_bridge.h | 25 +++++ include/hw/pci/pcie_port.h | 1 + 9 files changed, 442 insertions(+), 24 deletions(-) create mode 100644 docs/pcie_pci_bridge.txt create mode 100644 hw/pci-bridge/pcie_pci_bridge.c -- 2.7.4

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Re: [SeaBIOS] [PATCH RESEND v7 0/3] Red Hat PCI bridge resource reserve capability
by Kevin O'Connor 15 Sep '17

15 Sep '17

On Thu, Sep 14, 2017 at 11:15:43AM +0300, Aleksandr Bezzubikov wrote: > 2017-09-10 22:40 GMT+03:00 Marcel Apfelbaum <marcel(a)redhat.com>: > > On 10/09/2017 21:34, Aleksandr Bezzubikov wrote: > >> And what about this series? The matching QEMU series has been applied, > >> that's why there should be no problems with picking this series up for > >> SeaBIOS > >> > > > > Hi Aleksandr, > > > > Since SeaBIOS is a different project, we need to monitor the QEMU > > patches by ourselves and only then ask the maintainer to merge the > > patches if he has no objections, of course. (no automated process) > > > > Can you please verify the series still applies to SeaBIOS AS IS > > and run a quick test against today's QEMU master branch? > > Can you please give Kevin your OK before he proceeds with the merge? > > Just did it, it's sitll OK and works fine. That's why this series can > be merged AS IS. Thanks. I committed this series. (I did prune some spurious trailing newlines during the commit). -Kevin

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[PATCH v2 0/6] add serial console support
by Gerd Hoffmann 15 Sep '17

15 Sep '17

This patch series adds serial console support to seabios. Patches 1-3 add some bits the serial console patch depends on. Patch 4 adds the actual serial console support, for both primary display mode and splitmode (running in parallel to a vga display). The recommended way to activate the serial console is "qemu -machine graphics=no". Patch 5 adds support for a cbfs config file, to make the iobase configurable. Patch 6 is just for testing convenience and will not be merged. It makes the seabios serial console a drop-in replacement for sgabios, i.e. it is possible to activate it using "qemu -device sga". Gerd Hoffmann (6): std: add cp437 to unicode map kbd: make enqueue_key public, add ascii_to_keycode paravirt: read QEMU_CFG_NOGRAPHIC, store in etc/sercon-enable romfile add serial console support add support for etc/sercon-iobase cbfs file [hack] ignore sgabios, enable sercon instead Makefile | 3 +- src/config.h | 1 - src/cp437.h | 1 + src/util.h | 5 + src/clock.c | 1 + src/cp437.c | 275 ++++++++++++++++++++++ src/fw/paravirt.c | 2 + src/kbd.c | 18 +- src/misc.c | 8 - src/optionroms.c | 28 ++- src/sercon.c | 668 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/Kconfig | 5 + src/romlayout.S | 50 +++- 13 files changed, 1052 insertions(+), 13 deletions(-) create mode 100644 src/cp437.h create mode 100644 src/cp437.c create mode 100644 src/sercon.c -- 2.9.3

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Re: [SeaBIOS] [PATCH RESEND v7 0/3] Red Hat PCI bridge resource reserve capability
by Marcel Apfelbaum 14 Sep '17

14 Sep '17

On 10/09/2017 21:34, Aleksandr Bezzubikov wrote: > > пт, 18 авг. 2017 г. в 2:33, Aleksandr Bezzubikov <zuban32s(a)gmail.com > <mailto:zuban32s@gmail.com>>: > > Now PCI bridges get a bus range number on a system init, > basing on currently plugged devices. That's why when one wants to > hotplug another bridge, > it needs his child bus, which the parent is unable to provide > (speaking about virtual device). > The suggested workaround is to have vendor-specific capability in > Red Hat PCI bridges > that contains number of additional bus to reserve (as well as > IO/MEM/PREF space limit hints) > on BIOS PCI init. > So this capability is intended only for pure QEMU->SeaBIOS usage. > > Considering all aforesaid, this series is directly connected with > QEMU series "Generic PCIE-PCI Bridge". > > Although the new PCI capability is supposed to contain various > limits along with > bus number to reserve, now only its full layout is proposed. And > only bus_reserve field is used in QEMU and BIOS. Limits usage > is still a subject for implementation as now > the main goal of this series to provide necessary support from the > firmware side to PCIE-PCI bridge hotplug. > > Changes v6->v7: > 0. Resend - fix a bug with incorrect subordinate bus default value. > 1. Do not use alignment in case of IO reservation cap usage. > 2. Log additional buses reservation events. > > Changes v5->v6: > 1. Remove unnecessary indents and line breaks (addresses Marcel's > comments) > 2. Count IO/MEM/PREF region size as a maximum of necessary size and > one provide in > RESOURCE_RESERVE capability (addresses Marcel's comment). > 3. Make the cap debug message more detailed (addresses Marcel's > comment). > 4. Change pref_32 and pref_64 cap fields comment. > > Changes v4->v5: > 1. Rename capability-related #defines > 2. Move capability IO/MEM/PREF fields values usage to the regions > creation stage (addresses Marcel's comment) > 3. The capability layout change: separate pref_mem into pref_mem_32 > and pref_mem_64 fields (QEMU side has the same changes) (addresses > Laszlo's comment) > 4. Extract the capability lookup and check to the separate function > (addresses Marcel's comment) > - despite of Marcel's comment do not extract field check > for -1 since it increases code length > and doesn't look nice because of different field types > 5. Fix the capability's comment (addresses Marcel's comment) > 6. Fix the 3rd patch message > > Changes v3->v4: > 1. Use all QEMU PCI capability fields - addresses Michael's comment > 2. Changes of the capability layout (QEMU side has the same changes): > - change reservation fields types: bus_res - uint32_t, > others - uint64_t > - interpret -1 value as 'ignore' > > Changes v2->v3: > 1. Merge commit 2 (Red Hat vendor ID) into commit 4 - addresses > Marcel's comment, > and add Generic PCIE Root Port device ID - addresses > Michael's comment. > 2. Changes of the capability layout (QEMU side has the same changes): > - add 'type' field to distinguish multiple > RedHat-specific capabilities - addresses Michael's > comment > - do not mimiс PCI Config space register layout, but use > mutually exclusive differently > sized fields for IO and prefetchable memory limits > - addresses Laszlo's comment > - use defines instead of structure and offsetof - addresses > Michael's comment > 3. Interpret 'bus_reserve' field as a minimum necessary > range to reserve - addresses Gerd's comment > 4. pci_find_capability moved to pci.c - addresses Kevin's comment > 5. Move capability layout header to src/fw/dev-pci.h - addresses > Kevin's comment > 6. Add the capability documentation - addresses Michael's comment > 7. Add capability length and bus_reserve field sanity checks - > addresses Michael's comment > > Changes v1->v2: > 1. New #define for Red Hat vendor added (addresses Konrad's comment). > 2. Refactored pci_find_capability function (addresses Marcel's comment). > 3. Capability reworked: > - data type added; > - reserve space in a structure for IO, memory and > prefetchable memory limits. > > > Aleksandr Bezzubikov (3): > pci: refactor pci_find_capapibilty to get bdf as the first argument > instead of the whole pci_device > pci: add QEMU-specific PCI capability structure > pci: enable RedHat PCI bridges to reserve additional resources on PCI > init > > src/fw/dev-pci.h | 53 ++++++++++++++++++++++++++ > src/fw/pciinit.c | 108 > +++++++++++++++++++++++++++++++++++++++++++++++++--- > src/hw/pci.c | 25 ++++++++++++ > src/hw/pci.h | 1 + > src/hw/pci_ids.h | 3 ++ > src/hw/pcidevice.c | 24 ------------ > src/hw/pcidevice.h | 1 - > src/hw/virtio-pci.c | 6 +-- > 8 files changed, 188 insertions(+), 33 deletions(-) > create mode 100644 src/fw/dev-pci.h > > -- > 2.7.4 > > > And what about this series? The matching QEMU series has been applied, > that's why there should be no problems with picking this series up for > SeaBIOS > Hi Aleksandr, Since SeaBIOS is a different project, we need to monitor the QEMU patches by ourselves and only then ask the maintainer to merge the patches if he has no objections, of course. (no automated process) Can you please verify the series still applies to SeaBIOS AS IS and run a quick test against today's QEMU master branch? Can you please give Kevin your OK before he proceeds with the merge? Thanks, Marcel > > -- > Aleksandr Bezzubikov

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[PATCH 0/6] add serial console support
by Gerd Hoffmann 13 Sep '17

13 Sep '17

This patch series adds serial console support to seabios. Patches 1-3 add some bits the serial console patch depends on. Patch 4 adds the actual serial console support, where the serial console can be used in case no display adapter is present. Patch 5 is the most tricky one and implements splitmode, i.e. the serial console and vga console are active at the same time, output shows up on both serial and vga, input is accepted from both serial and keyboard. The recommended way to activate the serial console is "qemu -machine graphics=no". Patch 6 is just for testing convenience and will not be merged. It makes the seabios serial console a drop-in replacement for sgabios, i.e. it is possible to activate it using "qemu -device sga". Gerd Hoffmann (6): std: add cp437 to unicode map kbd: make enqueue_key public, add ascii_to_keycode paravirt: read QEMU_CFG_NOGRAPHIC, store in etc/sercon-enable romfile add serial console support sercon: split-output implementation [hack] ignore sgabios, enable sercon instead Makefile | 3 +- src/cp437.h | 1 + src/util.h | 5 + src/clock.c | 1 + src/cp437.c | 275 ++++++++++++++++++++++ src/fw/paravirt.c | 2 + src/kbd.c | 18 +- src/misc.c | 2 + src/optionroms.c | 17 +- src/sercon.c | 668 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/Kconfig | 5 + src/romlayout.S | 46 ++++ 12 files changed, 1039 insertions(+), 4 deletions(-) create mode 100644 src/cp437.h create mode 100644 src/cp437.c create mode 100644 src/sercon.c -- 2.9.3

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[PATCH RESEND v7 0/3] Red Hat PCI bridge resource reserve capability
by Aleksandr Bezzubikov 11 Sep '17

11 Sep '17

Now PCI bridges get a bus range number on a system init, basing on currently plugged devices. That's why when one wants to hotplug another bridge, it needs his child bus, which the parent is unable to provide (speaking about virtual device). The suggested workaround is to have vendor-specific capability in Red Hat PCI bridges that contains number of additional bus to reserve (as well as IO/MEM/PREF space limit hints) on BIOS PCI init. So this capability is intended only for pure QEMU->SeaBIOS usage. Considering all aforesaid, this series is directly connected with QEMU series "Generic PCIE-PCI Bridge". Although the new PCI capability is supposed to contain various limits along with bus number to reserve, now only its full layout is proposed. And only bus_reserve field is used in QEMU and BIOS. Limits usage is still a subject for implementation as now the main goal of this series to provide necessary support from the firmware side to PCIE-PCI bridge hotplug. Changes v6->v7: 0. Resend - fix a bug with incorrect subordinate bus default value. 1. Do not use alignment in case of IO reservation cap usage. 2. Log additional buses reservation events. Changes v5->v6: 1. Remove unnecessary indents and line breaks (addresses Marcel's comments) 2. Count IO/MEM/PREF region size as a maximum of necessary size and one provide in RESOURCE_RESERVE capability (addresses Marcel's comment). 3. Make the cap debug message more detailed (addresses Marcel's comment). 4. Change pref_32 and pref_64 cap fields comment. Changes v4->v5: 1. Rename capability-related #defines 2. Move capability IO/MEM/PREF fields values usage to the regions creation stage (addresses Marcel's comment) 3. The capability layout change: separate pref_mem into pref_mem_32 and pref_mem_64 fields (QEMU side has the same changes) (addresses Laszlo's comment) 4. Extract the capability lookup and check to the separate function (addresses Marcel's comment) - despite of Marcel's comment do not extract field check for -1 since it increases code length and doesn't look nice because of different field types 5. Fix the capability's comment (addresses Marcel's comment) 6. Fix the 3rd patch message Changes v3->v4: 1. Use all QEMU PCI capability fields - addresses Michael's comment 2. Changes of the capability layout (QEMU side has the same changes): - change reservation fields types: bus_res - uint32_t, others - uint64_t - interpret -1 value as 'ignore' Changes v2->v3: 1. Merge commit 2 (Red Hat vendor ID) into commit 4 - addresses Marcel's comment, and add Generic PCIE Root Port device ID - addresses Michael's comment. 2. Changes of the capability layout (QEMU side has the same changes): - add 'type' field to distinguish multiple RedHat-specific capabilities - addresses Michael's comment - do not mimiс PCI Config space register layout, but use mutually exclusive differently sized fields for IO and prefetchable memory limits - addresses Laszlo's comment - use defines instead of structure and offsetof - addresses Michael's comment 3. Interpret 'bus_reserve' field as a minimum necessary range to reserve - addresses Gerd's comment 4. pci_find_capability moved to pci.c - addresses Kevin's comment 5. Move capability layout header to src/fw/dev-pci.h - addresses Kevin's comment 6. Add the capability documentation - addresses Michael's comment 7. Add capability length and bus_reserve field sanity checks - addresses Michael's comment Changes v1->v2: 1. New #define for Red Hat vendor added (addresses Konrad's comment). 2. Refactored pci_find_capability function (addresses Marcel's comment). 3. Capability reworked: - data type added; - reserve space in a structure for IO, memory and prefetchable memory limits. Aleksandr Bezzubikov (3): pci: refactor pci_find_capapibilty to get bdf as the first argument instead of the whole pci_device pci: add QEMU-specific PCI capability structure pci: enable RedHat PCI bridges to reserve additional resources on PCI init src/fw/dev-pci.h | 53 ++++++++++++++++++++++++++ src/fw/pciinit.c | 108 +++++++++++++++++++++++++++++++++++++++++++++++++--- src/hw/pci.c | 25 ++++++++++++ src/hw/pci.h | 1 + src/hw/pci_ids.h | 3 ++ src/hw/pcidevice.c | 24 ------------ src/hw/pcidevice.h | 1 - src/hw/virtio-pci.c | 6 +-- 8 files changed, 188 insertions(+), 33 deletions(-) create mode 100644 src/fw/dev-pci.h -- 2.7.4

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[PATCH 0/3] SeaVGABIOS serial console test
by Kevin O'Connor 06 Sep '17

06 Sep '17

Hi Gerd, I was curious to see what the "sercon" stuff would look like in SeaVGABIOS instead of in SeaBIOS. So, I put together a quick prototype. The code is also at: https://github.com/KevinOConnor/seabios/tree/testing This is just a proof-of-concept thing - I didn't implement any of the useful features you have in your series. Specifically, it doesn't unclutter the serial output, doesn't implement cp437 translations, and doesn't handle multi-byte input. It does does have basic input, output, and split-output handling though. I'm not sure if this is better than a SeaBIOS implementation. I suspect it will be easier to handle vga quirks this way. However, handling exotic serial outputs (eg, mmio and usb based) would be better suited in SeaBIOS. Thoughts? -Kevin Kevin O'Connor (3): sercon: Initial support for VGA emulation over serial port sercon: Add basic keyboard input support sercon: Support "split output" mode Makefile | 2 +- vgasrc/Kconfig | 6 + vgasrc/sercon.c | 356 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ vgasrc/vgabios.c | 15 ++- vgasrc/vgabios.h | 5 + vgasrc/vgaentry.S | 7 ++ vgasrc/vgahw.h | 72 ++++++++++- vgasrc/vgainit.c | 12 +- vgasrc/vgautil.h | 24 ++++ 9 files changed, 482 insertions(+), 17 deletions(-) create mode 100644 vgasrc/sercon.c -- 2.5.5

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[PATCH] docs: Fix typos in Memory_Model.md
by Kevin O'Connor 30 Aug '17

30 Aug '17

Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- docs/Memory_Model.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/Memory_Model.md b/docs/Memory_Model.md index 0668bd8..1ebe865 100644 --- a/docs/Memory_Model.md +++ b/docs/Memory_Model.md @@ -192,7 +192,7 @@ There are three low-level memory access macros: * GET_FARVAR / SET_FARVAR : Assigns the extra segment (%es) to the given segment id and then performs the given memory access via %es. -* GET_FLATVAR / SET_FLATVAR : These macros take a 32bit pointer, +* GET_FLATPTR / SET_FLATPTR : These macros take a 32bit pointer, construct a segment/offset pair valid in real mode, and then perform the given access. These macros must not be used in 16bit protected mode or 32bit segmented mode. @@ -209,11 +209,11 @@ macros are also available. * GET_LOW / SET_LOW : Access internal variables marked with VARLOW. (There are also related macros GET_LOWFLAT / SET_LOWFLAT for - accessing storage allocated with malloc_low). + accessing storage allocated with malloc_low.) * GET_GLOBAL : Access internal variables marked with the VAR16 or VARFSEG flags. (There is also the related macro GET_GLOBALFLAT for - accessing storage allocated with malloc_fseg). + accessing storage allocated with malloc_fseg.) Memory available during initialization ====================================== -- 2.9.5

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Seabios unable to boot Fedora-based instances
by Maciej Józefczyk 30 Aug '17

30 Aug '17

Hello, Environment: Seabios master dd9bba5b9c1d5175a2757f3fdc9d554b4c8eea3a Qemu: 1:2.5+dfsg-5ubuntu10.14 OS: Ubuntu 16.04 We found that newest Seabios (dd9bba5b9c1d5175a2757f3fdc9d554b4c8eea3a) is not working with latest Fedora 26 - image taken from: https://download.fedoraproject.org/pub/fedora/linux/releases/26/CloudImages… Each time it hangs on "Probing EDD (edd=off to disable)... OK". We discovered that rollback to version 4902b8a7 solves the problem. It seems that something is wrong with 4902b8a7. After fetch lastest master and rollback of 4902b8a7 - Fedora is able to boot. Ubuntu is booting all the time without problem. Could you take a look on this? Best regards Maciej -- ---- Maciej Józefczyk maciej.jozefczyk(a)corp.ovh.com

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[PATCH v2 1/2] usb: add hub portmap
by Gerd Hoffmann 29 Aug '17

29 Aug '17

Allow usb hubs to map (software) ports to physical ports via op callback. This is needed to make bootorder work in case there isn't a simple linear mapping. Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/hw/usb.h | 1 + src/boot.c | 13 ++++++++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/hw/usb.h b/src/hw/usb.h index 94e12b20dd..2cfb572177 100644 --- a/src/hw/usb.h +++ b/src/hw/usb.h @@ -56,6 +56,7 @@ struct usbhub_s { struct usbhub_op_s { int (*detect)(struct usbhub_s *hub, u32 port); int (*reset)(struct usbhub_s *hub, u32 port); + int (*portmap)(struct usbhub_s *hub, u32 port); void (*disconnect)(struct usbhub_s *hub, u32 port); }; diff --git a/src/boot.c b/src/boot.c index 59623fb63d..834ac3f3c5 100644 --- a/src/boot.c +++ b/src/boot.c @@ -207,6 +207,13 @@ int bootprio_find_named_rom(const char *name, int instance) return find_prio(desc); } +static int usb_portmap(struct usbdevice_s *usbdev) +{ + if (usbdev->hub->op->portmap) + return usbdev->hub->op->portmap(usbdev->hub, usbdev->port); + return usbdev->port + 1; +} + static char * build_usb_path(char *buf, int max, struct usbhub_s *hub) { @@ -214,7 +221,7 @@ build_usb_path(char *buf, int max, struct usbhub_s *hub) // Root hub - nothing to add. return buf; char *p = build_usb_path(buf, max, hub->usbdev->hub); - p += snprintf(p, buf+max-p, "/hub@%x", hub->usbdev->port+1); + p += snprintf(p, buf+max-p, "/hub@%x", usb_portmap(hub->usbdev)); return p; } @@ -227,12 +234,12 @@ int bootprio_find_usb(struct usbdevice_s *usbdev, int lun) p = build_pci_path(desc, sizeof(desc), "usb", usbdev->hub->cntl->pci); p = build_usb_path(p, desc+sizeof(desc)-p, usbdev->hub); snprintf(p, desc+sizeof(desc)-p, "/storage@%x/*@0/*@0,%x" - , usbdev->port+1, lun); + , usb_portmap(usbdev), lun); int ret = find_prio(desc); if (ret >= 0) return ret; // Try usb-host/redir - for example: /pci@i0cf8/usb@1,2/usb-host@1 - snprintf(p, desc+sizeof(desc)-p, "/usb-*@%x", usbdev->port+1); + snprintf(p, desc+sizeof(desc)-p, "/usb-*@%x", usb_portmap(usbdev)); return find_prio(desc); } -- 2.9.3

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