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3801 discussions

How to Debug read operation on hda
by Daniel Castro 29 Feb '12

29 Feb '12

Greeting, As part of the xen code for PV-Drivers in Seabios I am trying to boot from a PV drive. The two ends are connected, and it should be working, but when I try to boot from the harddrive it fails. Inside the code I treat the cdrom as a drive, except I register it in seabios with the cdrom function, but also it fails to boot from cdrom with Error 003. This could mean that maybe I am adding the drives incorrectly, or that my read/write opertaion is wrong. Since the operation runs in 16bit how can I debug it to see what is being done? Thanks for the answers. Daniel -- +-=====---------------------------+ | +---------------------------------+ | This space intentionally blank for notetaking. | | | Daniel Castro, | | | | Consultant/Programmer.| | | | U Andes | +-------------------------------------+

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Re: [SeaBIOS] Coreboot, Geode LX and VGA
by Nils 24 Feb '12

24 Feb '12

Op woensdag 22-02-2012 om 23:52 uur [tijdzone +0100], schreef Christian Gmeiner: > ping > -- The only thing that comes to my mind is that you could try coreboot version 4.0-1975-g1b785c7 because that's the last version that i used. According to the coreboot mailinglist there seems to be a problem in recent versions with vbios and option rom init in seabios. See 'Fix multipleVGA cards resource conflict on Windows' . Maybe it affects your board also. Greetings, Nils.

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usb ohci pipe free fix
by Kevin O'Connor 23 Feb '12

23 Feb '12

Hi Nils, I put together a patch to modify the way the OHCI controller does pipe free'ing. This is a preliminary patch (similar batch free'ing should be done for the other controllers as well). However, it might help with the USB issues you've been having. -Kevin commit fa43976172295d3bad9209374bd68469c10ec918 Author: Kevin O'Connor <kevin(a)koconnor.net> Date: Mon Feb 20 12:54:49 2012 -0500 Batch free USB pipes on OHCI controllers. Instead of unregistering each control "endpoint descriptor" after it is used, keep them around for later users. Free all unused descriptors in one batch at the end of initialization. This should slightly optimize boot time, and it requires less overall interaction with the controller. This also makes the descriptor free code more compliant with the spec. The descriptor lists will only be modified after the list processing has been disabled on the controller. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> diff --git a/src/usb-ohci.c b/src/usb-ohci.c index 9107db2..7a437ad 100644 --- a/src/usb-ohci.c +++ b/src/usb-ohci.c @@ -19,6 +19,14 @@ struct usb_ohci_s { struct ohci_regs *regs; }; +struct ohci_pipe { + struct ohci_ed ed; + struct usb_pipe pipe; + void *data; + int count; + struct ohci_td *tds; +}; + /**************************************************************** * Root hub @@ -109,6 +117,56 @@ check_ohci_ports(struct usb_ohci_s *cntl) * Setup ****************************************************************/ +// Wait for next USB frame to start - for ensuring safe memory release. +static void +ohci_waittick(struct usb_ohci_s *cntl) +{ + barrier(); + struct ohci_hcca *hcca = (void*)cntl->regs->hcca; + u32 startframe = hcca->frame_no; + u64 end = calc_future_tsc(1000 * 5); + for (;;) { + if (hcca->frame_no != startframe) + break; + if (check_tsc(end)) { + warn_timeout(); + return; + } + yield(); + } +} + +static void +ohci_free_pipes(struct usb_ohci_s *cntl) +{ + dprintf(7, "ohci_free_pipes %p\n", cntl); + + u32 creg = readl(&cntl->regs->control); + if (creg & (OHCI_CTRL_CLE|OHCI_CTRL_BLE)) { + writel(&cntl->regs->control, creg & ~(OHCI_CTRL_CLE|OHCI_CTRL_BLE)); + ohci_waittick(cntl); + } + + u32 *pos = &cntl->regs->ed_controlhead; + for (;;) { + struct ohci_ed *next = (void*)*pos; + if (!next) + break; + struct ohci_pipe *pipe = container_of(next, struct ohci_pipe, ed); + if (pipe->pipe.cntl != &cntl->usb) { + *pos = next->hwNextED; + free(pipe); + } else { + pos = &next->hwNextED; + } + } + + writel(&cntl->regs->ed_controlcurrent, 0); + writel(&cntl->regs->ed_bulkcurrent, 0); + writel(&cntl->regs->control, creg); + cntl->usb.freelist = NULL; +} + static int start_ohci(struct usb_ohci_s *cntl, struct ohci_hcca *hcca) { @@ -192,6 +250,7 @@ configure_ohci(void *data) int count = check_ohci_ports(cntl); free_pipe(cntl->usb.defaultpipe); + ohci_free_pipes(cntl); if (! count) goto err; return; @@ -260,74 +319,13 @@ wait_ed(struct ohci_ed *ed) } } -// Wait for next USB frame to start - for ensuring safe memory release. -static void -ohci_waittick(struct usb_ohci_s *cntl) -{ - barrier(); - struct ohci_hcca *hcca = (void*)cntl->regs->hcca; - u32 startframe = hcca->frame_no; - u64 end = calc_future_tsc(1000 * 5); - for (;;) { - if (hcca->frame_no != startframe) - break; - if (check_tsc(end)) { - warn_timeout(); - return; - } - yield(); - } -} - -static void -signal_freelist(struct usb_ohci_s *cntl) -{ - u32 v = readl(&cntl->regs->control); - if (v & OHCI_CTRL_CLE) { - writel(&cntl->regs->control, v & ~(OHCI_CTRL_CLE|OHCI_CTRL_BLE)); - ohci_waittick(cntl); - writel(&cntl->regs->ed_controlcurrent, 0); - writel(&cntl->regs->ed_bulkcurrent, 0); - writel(&cntl->regs->control, v); - } else { - ohci_waittick(cntl); - } -} - -struct ohci_pipe { - struct ohci_ed ed; - struct usb_pipe pipe; - void *data; - int count; - struct ohci_td *tds; -}; - void -ohci_free_pipe(struct usb_pipe *p) +ohci_free_pipe(struct usb_pipe *pipe) { - if (! CONFIG_USB_OHCI) - return; - dprintf(7, "ohci_free_pipe %p\n", p); - struct ohci_pipe *pipe = container_of(p, struct ohci_pipe, pipe); - struct usb_ohci_s *cntl = container_of( - pipe->pipe.cntl, struct usb_ohci_s, usb); - - u32 *pos = &cntl->regs->ed_controlhead; - for (;;) { - struct ohci_ed *next = (void*)*pos; - if (!next) { - // Not found?! Exit without freeing. - warn_internalerror(); - return; - } - if (next == &pipe->ed) { - *pos = next->hwNextED; - signal_freelist(cntl); - free(pipe); - return; - } - pos = &next->hwNextED; - } + // Add to controller's free list. + struct usb_s *cntl = pipe->cntl; + pipe->freenext = cntl->freelist; + cntl->freelist = pipe; } struct usb_pipe * @@ -339,7 +337,17 @@ ohci_alloc_control_pipe(struct usb_pipe *dummy) dummy->cntl, struct usb_ohci_s, usb); dprintf(7, "ohci_alloc_control_pipe %p\n", &cntl->usb); - // Allocate a queue head. + if (cntl->usb.freelist) { + // Use previously allocated queue head. + struct ohci_pipe *pipe = container_of(cntl->usb.freelist + , struct ohci_pipe, pipe); + cntl->usb.freelist = pipe->pipe.freenext; + + memcpy(&pipe->pipe, dummy, sizeof(pipe->pipe)); + return &pipe->pipe; + } + + // Allocate a new queue head. struct ohci_pipe *pipe = malloc_tmphigh(sizeof(*pipe)); if (!pipe) { warn_noalloc(); diff --git a/src/usb.h b/src/usb.h index 8b2af40..cc32eb7 100644 --- a/src/usb.h +++ b/src/usb.h @@ -6,7 +6,10 @@ // Information on a USB end point. struct usb_pipe { - struct usb_s *cntl; + union { + struct usb_s *cntl; + struct usb_pipe *freenext; + }; u64 path; u8 type; u8 ep; @@ -20,6 +23,7 @@ struct usb_pipe { // Common information for usb controllers. struct usb_s { struct usb_pipe *defaultpipe; + struct usb_pipe *freelist; struct mutex_s resetlock; struct pci_device *pci; int busid;

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[PATCH] src/bootsplash.c: Fix displaying VGA bootsplash
by Gerhard Wiesinger 23 Feb '12

23 Feb '12

VGA bootsplash isn't displayed because video mode is set which clears the display. Video mode has already been set by some VGA BIOS. User can choose by config option to disable setting of VGA video mode by seabios (CONFIG_BOOT_SET_VIDEO_MODE). Works well under QEMU/KVM with VGA BIOS and seabios. Default behaviour is the same as before where VGA mode is set by seabios. Signed-off-by: Gerhard Wiesinger <lists(a)wiesinger.com> --- src/Kconfig | 5 +++++ src/bootsplash.c | 13 ++++++++----- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 250663a..08325cc 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -52,6 +52,11 @@ menu "General Features" default y help Support showing a graphical boot splash screen. + config BOOT_SET_VIDEO_MODE + bool "Set video mode on initialization" + default y + help + Option should not be set when the VGA init string should be displayed. config BOOTORDER depends on BOOT bool "Boot ordering" diff --git a/src/bootsplash.c b/src/bootsplash.c index 76b72c1..09ad0a1 100644 --- a/src/bootsplash.c +++ b/src/bootsplash.c @@ -38,12 +38,15 @@ void enable_vga_console(void) { dprintf(1, "Turning on vga text mode console\n"); - struct bregs br; - /* Enable VGA text mode */ - memset(&br, 0, sizeof(br)); - br.ax = 0x0003; - call16_int10(&br); + if (CONFIG_BOOT_SET_VIDEO_MODE) { + struct bregs br; + + /* Enable VGA text mode */ + memset(&br, 0, sizeof(br)); + br.ax = 0x0003; + call16_int10(&br); + } // Write to screen. printf("SeaBIOS (version %s)\n\n", VERSION); -- 1.7.7.6

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RFE: Print amount of RAM
by Igor Galić 23 Feb '12

23 Feb '12

Hello happy people, I'm back from a two day goose-chase where I was wondering very much why my VMs don't boot. https://www.redhat.com/archives/libvirt-users/2012-February/msg00106.html In that process I upgraded my entire stack (libvirt, qemu, seabios) but found that the boot hung at SeaBIOS trying to boot from ROM. After stepping through all the arguments libvirt supplied to I found that my <memory>2048</memory> the qemu argument -m 2 (megs) -- which wasn't quite enough. (Similarly, my previously supplied <memory>20480</memory> weren't too much they too were too little to boot a Linux kernel). I've already talked to the libvirt folks, and they'll try to get in a feature to supply a <memory unit="M"> or similar. Now I'd like to ask you guys if you could print the amount of RAM available -- like most other BIOSes out there already do - it would be extremely helpful to aid troubleshooting. Thank you very much in advance. So long, i -- Igor Galić Tel: +43 (0) 664 886 22 883 Mail: i.galic(a)brainsware.org URL: http://brainsware.org/ GPG: 6880 4155 74BD FD7C B515 2EA5 4B1D 9E08 A097 C9AE

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Re: [SeaBIOS] Coreboot, Geode LX and VGA
by Peter Stuge 23 Feb '12

23 Feb '12

Christian Gmeiner wrote: > ping I think the ball is in your corner. Experiment further with the various options for graphics drivers, which can run either directly as payloads or as part of something after the payload. When you find one which works, then compare that with the SeaVGABIOS which doesn't work for you, and send a patch. :) //Peter

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Re: [SeaBIOS] Coreboot, Geode LX and VGA
by Christian Gmeiner 22 Feb '12

22 Feb '12

ping -- Christian Gmeiner, MSc Am 21. Februar 2012 09:17 schrieb Christian Gmeiner <christian.gmeiner(a)gmail.com>: > 2012/2/21 Nils <njacobs8(a)adsltotaal.nl>: >> Op maandag 20-02-2012 om 18:54 uur [tijdzone +0100], schreef Christian >> Gmeiner: >>> 2012/2/20 Christian Gmeiner <christian.gmeiner(a)gmail.com>: >>> > 2012/2/20 Christian Gmeiner <christian.gmeiner(a)gmail.com>: >>> >> 2012/2/20 Kevin O'Connor <kevin(a)koconnor.net>: >>> >>> On Mon, Feb 20, 2012 at 02:39:27PM +0100, Christian Gmeiner wrote: >>> >>>> Hi all, >>> >>>> >>> >>>> I am trying my luck with coreboot and seabios to get VGA working on an LX800 >>> >>>> platform. At the moment I am not sure what options I need to enable in coreboot >>> >>>> and seabios to enable VGA. >>> >>> >>> >>> Nils recently reported success using the SeaVGABIOS on his Geode GX2 >>> >>> based machine. I don't think anyone has tried recently on the Geode >>> >>> LX. >>> >>> >>> >>>> Coreboot does its jobs and starts SeaBIOS, but VGA seems not to work. >>> >>>> >>> >>>> thanks for every hint >>> >>> >>> >>> Please send the coreboot plus seabios log (with debugging set to 8) to >>> >>> the mail list. >>> >> >>> >> Here it is http://nopaste.info/10545252c4.html >>> >> >>> > >>> > After some tipps on irc I get this results: >>> > http://nopaste.info/f22222d6d8.html >> >> It is not clear to me if you get some text on your screen now that vga >> bios loading is working. > > It does not work.. any hints how to debug it. I can say, that linux lxfb works. > >> >> For your boot problem you could try enabling CONFIG_ATA_DMA if i >> remember correct it doesn't boot without it on my target also.( i always >> set it) > > On some of your devices UDMA is broken due some wrong schematics. So I > enabled PIO32 > > Greets > -- > Christian Gmeiner, MSc

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[PATCH 0/5] pci: 64bit support
by Gerd Hoffmann 22 Feb '12

22 Feb '12

Hi, The effort to add support for 64bit pci bars to qemu seems to have stalled somehow. Lets resume it ;) Here is a patch collection, largely rewritten from scratch, which improves seabios 64bit support. One big patch (#3) adds 64bit math everythere. The other big patch (#5) adds support for ressource allocation above 4G. The remaining patches carry bugfixes and little bits such as support for printing 64bit hex numbers. cheers, Gerd Gerd Hoffmann (5): 64bit hex printf support pci: split device discovery into multiple steps pci: 64bit support. pci: bridges can have two regions too pci: add prefmem64 region type. src/acpi-dsdt.dsl | 7 ++ src/config.h | 2 + src/output.c | 32 ++++++-- src/pci.h | 14 ++- src/pciinit.c | 245 +++++++++++++++++++++++++++++++++++++---------------- 5 files changed, 217 insertions(+), 83 deletions(-)

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Re: [SeaBIOS] Coreboot, Geode LX and VGA
by Nils 21 Feb '12

21 Feb '12

Op maandag 20-02-2012 om 18:54 uur [tijdzone +0100], schreef Christian Gmeiner: > 2012/2/20 Christian Gmeiner <christian.gmeiner(a)gmail.com>: > > 2012/2/20 Christian Gmeiner <christian.gmeiner(a)gmail.com>: > >> 2012/2/20 Kevin O'Connor <kevin(a)koconnor.net>: > >>> On Mon, Feb 20, 2012 at 02:39:27PM +0100, Christian Gmeiner wrote: > >>>> Hi all, > >>>> > >>>> I am trying my luck with coreboot and seabios to get VGA working on an LX800 > >>>> platform. At the moment I am not sure what options I need to enable in coreboot > >>>> and seabios to enable VGA. > >>> > >>> Nils recently reported success using the SeaVGABIOS on his Geode GX2 > >>> based machine. I don't think anyone has tried recently on the Geode > >>> LX. > >>> > >>>> Coreboot does its jobs and starts SeaBIOS, but VGA seems not to work. > >>>> > >>>> thanks for every hint > >>> > >>> Please send the coreboot plus seabios log (with debugging set to 8) to > >>> the mail list. > >> > >> Here it is http://nopaste.info/10545252c4.html > >> > > > > After some tipps on irc I get this results: > > http://nopaste.info/f22222d6d8.html It is not clear to me if you get some text on your screen now that vga bios loading is working. For your boot problem you could try enabling CONFIG_ATA_DMA if i remember correct it doesn't boot without it on my target also.( i always set it) Greetings, Nils.

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Re: [SeaBIOS] Coreboot, Geode LX and VGA
by Christian Gmeiner 20 Feb '12

20 Feb '12

2012/2/20 Christian Gmeiner <christian.gmeiner(a)gmail.com>: > 2012/2/20 Christian Gmeiner <christian.gmeiner(a)gmail.com>: >> 2012/2/20 Kevin O'Connor <kevin(a)koconnor.net>: >>> On Mon, Feb 20, 2012 at 02:39:27PM +0100, Christian Gmeiner wrote: >>>> Hi all, >>>> >>>> I am trying my luck with coreboot and seabios to get VGA working on an LX800 >>>> platform. At the moment I am not sure what options I need to enable in coreboot >>>> and seabios to enable VGA. >>> >>> Nils recently reported success using the SeaVGABIOS on his Geode GX2 >>> based machine. I don't think anyone has tried recently on the Geode >>> LX. >>> >>>> Coreboot does its jobs and starts SeaBIOS, but VGA seems not to work. >>>> >>>> thanks for every hint >>> >>> Please send the coreboot plus seabios log (with debugging set to 8) to >>> the mail list. >> >> Here it is http://nopaste.info/10545252c4.html >> > > After some tipps on irc I get this results: > http://nopaste.info/f22222d6d8.html > And here are my used config files Greets, -- Christian Gmeiner, MSc

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