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[RFC PATCH v4 13/30] piix_pci and pc_piix: refactor
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

Refactor code so that chipset initialization is similar to q35. This will allow memory map initialization at chipset qdev init time for both machines, as well as more similar code structure overall. Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- hw/pc_piix.c | 57 ++++++++++++--- hw/piix_pci.c | 225 ++++++++++++++------------------------------------------- 2 files changed, 100 insertions(+), 182 deletions(-) diff --git a/hw/pc_piix.c b/hw/pc_piix.c index 19e342a..6a9b508 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -47,6 +47,7 @@ #ifdef CONFIG_XEN # include <xen/hvm/hvm_info_table.h> #endif +#include "piix_pci.h" #define MAX_IDE_BUS 2 @@ -85,6 +86,8 @@ static void pc_init1(MemoryRegion *system_memory, MemoryRegion *pci_memory; MemoryRegion *rom_memory; void *fw_cfg = NULL; + I440FXState *i440fx_host; + PIIX3State *piix3; pc_cpus_init(cpu_model); @@ -127,21 +130,53 @@ static void pc_init1(MemoryRegion *system_memory, } if (pci_enabled) { - pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, &isa_bus, gsi, - system_memory, system_io, ram_size, - below_4g_mem_size, - 0x100000000ULL - below_4g_mem_size, - 0x100000000ULL + above_4g_mem_size, - (sizeof(hwaddr) == 4 - ? 0 - : ((uint64_t)1 << 62)), - pci_memory, ram_memory); + i440fx_host = I440FX_HOST_DEVICE(qdev_create(NULL, + TYPE_I440FX_HOST_DEVICE)); + i440fx_host->mch.ram_memory = ram_memory; + i440fx_host->mch.pci_address_space = pci_memory; + i440fx_host->mch.system_memory = get_system_memory(); + i440fx_host->mch.address_space_io = get_system_io();; + i440fx_host->mch.below_4g_mem_size = below_4g_mem_size; + i440fx_host->mch.above_4g_mem_size = above_4g_mem_size; + + qdev_init_nofail(DEVICE(i440fx_host)); + i440fx_state = &i440fx_host->mch; + pci_bus = i440fx_host->parent_obj.bus; + /* Xen supports additional interrupt routes from the PCI devices to + * the IOAPIC: the four pins of each PCI device on the bus are also + * connected to the IOAPIC directly. + * These additional routes can be discovered through ACPI. */ + if (xen_enabled()) { + piix3 = DO_UPCAST(PIIX3State, dev, + pci_create_simple_multifunction(pci_bus, -1, true, + "PIIX3-xen")); + pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq, + piix3, XEN_PIIX_NUM_PIRQS); + } else { + piix3 = DO_UPCAST(PIIX3State, dev, + pci_create_simple_multifunction(pci_bus, -1, true, + "PIIX3")); + pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, piix3, + PIIX_NUM_PIRQS); + pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); + } + piix3->pic = gsi; + isa_bus = DO_UPCAST(ISABus, qbus, + qdev_get_child_bus(&piix3->dev.qdev, "isa.0")); + + piix3_devfn = piix3->dev.devfn; + + ram_size = ram_size / 8 / 1024 / 1024; + if (ram_size > 255) { + ram_size = 255; + } + i440fx_state->dev.config[0x57] = ram_size; } else { pci_bus = NULL; - i440fx_state = NULL; isa_bus = isa_bus_new(NULL, system_io); no_hpet = 1; } + isa_bus_irqs(isa_bus, gsi); if (kvm_irqchip_in_kernel()) { @@ -157,7 +192,7 @@ static void pc_init1(MemoryRegion *system_memory, gsi_state->i8259_irq[i] = i8259[i]; } if (pci_enabled) { - ioapic_init_gsi(gsi_state, "i440fx"); + ioapic_init_gsi(gsi_state, NULL); } pc_register_ferr_irq(gsi[13]); diff --git a/hw/piix_pci.c b/hw/piix_pci.c index ba1b3de..7ca3c73 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -31,70 +31,15 @@ #include "range.h" #include "xen.h" #include "pam.h" +#include "piix_pci.h" -/* - * I440FX chipset data sheet. - * http://download.intel.com/design/chipsets/datashts/29054901.pdf - */ - -typedef struct I440FXState { - PCIHostState parent_obj; -} I440FXState; - -#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ -#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ -#define XEN_PIIX_NUM_PIRQS 128ULL -#define PIIX_PIRQC 0x60 - -typedef struct PIIX3State { - PCIDevice dev; - - /* - * bitmap to track pic levels. - * The pic level is the logical OR of all the PCI irqs mapped to it - * So one PIC level is tracked by PIIX_NUM_PIRQS bits. - * - * PIRQ is mapped to PIC pins, we track it by - * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with - * pic_irq * PIIX_NUM_PIRQS + pirq - */ -#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 -#error "unable to encode pic state in 64bit in pic_levels." -#endif - uint64_t pic_levels; - - qemu_irq *pic; - - /* This member isn't used. Just for save/load compatibility */ - int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; -} PIIX3State; - -struct PCII440FXState { - PCIDevice dev; - MemoryRegion *system_memory; - MemoryRegion *pci_address_space; - MemoryRegion *ram_memory; - MemoryRegion pci_hole; - MemoryRegion pci_hole_64bit; - PAMMemoryRegion pam_regions[13]; - MemoryRegion smram_region; - uint8_t smm_enabled; -}; - - -#define I440FX_PAM 0x59 -#define I440FX_PAM_SIZE 7 -#define I440FX_SMRAM 0x72 - -static void piix3_set_irq(void *opaque, int pirq, int level); -static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx); static void piix3_write_config_xen(PCIDevice *dev, uint32_t address, uint32_t val, int len); /* return the global irq number corresponding to a given device irq pin. We could also use the bus number to have a more precise mapping. */ -static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) +int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) { int slot_addend; slot_addend = (pci_dev->devfn >> 3) - 1; @@ -180,149 +125,86 @@ static const VMStateDescription vmstate_i440fx = { } }; -static int i440fx_pcihost_initfn(SysBusDevice *dev) +static void i440fx_pcihost_initfn(Object *obj) { - PCIHostState *s = PCI_HOST_BRIDGE(dev); + I440FXState *s = I440FX_HOST_DEVICE(obj); + object_initialize(&s->mch, TYPE_I440FX_PCI_DEVICE); + object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); +} - memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s, - "pci-conf-idx", 4); - sysbus_add_io(dev, 0xcf8, &s->conf_mem); - sysbus_init_ioports(&s->busdev, 0xcf8, 4); +static int i440fx_pcihost_init(SysBusDevice *dev) +{ + PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev); + I440FXState *s = I440FX_HOST_DEVICE(&dev->qdev); + PCIBus *b; + + memory_region_init_io(&pci->conf_mem, &pci_host_conf_le_ops, pci, + "pci-conf-idx", 4); + sysbus_add_io(dev, 0xcf8, &pci->conf_mem); + sysbus_init_ioports(&pci->busdev, 0xcf8, 4); + memory_region_init_io(&pci->data_mem, &pci_host_data_le_ops, pci, + "pci-conf-data", 4); - memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s, - "pci-conf-data", 4); - sysbus_add_io(dev, 0xcfc, &s->data_mem); - sysbus_init_ioports(&s->busdev, 0xcfc, 4); + sysbus_add_io(dev, 0xcfc, &pci->data_mem); + sysbus_init_ioports(&pci->busdev, 0xcfc, 4); + + b = pci_bus_new(&s->parent_obj.busdev.qdev, NULL, s->mch.pci_address_space, + s->mch.address_space_io, 0); + s->parent_obj.bus = b; + qdev_set_parent_bus(DEVICE(&s->mch), BUS(b)); + qdev_init_nofail(DEVICE(&s->mch)); return 0; } static int i440fx_initfn(PCIDevice *dev) { - PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); + int i; + PCII440FXState *f = DO_UPCAST(PCII440FXState, dev, dev); + hwaddr pci_hole64_size; - d->dev.config[I440FX_SMRAM] = 0x02; + f->dev.config[I440FX_SMRAM] = 0x02; - cpu_smm_register(&i440fx_set_smm, d); - return 0; -} + cpu_smm_register(&i440fx_set_smm, f); -static PCIBus *i440fx_common_init(const char *device_name, - PCII440FXState **pi440fx_state, - int *piix3_devfn, - ISABus **isa_bus, qemu_irq *pic, - MemoryRegion *address_space_mem, - MemoryRegion *address_space_io, - ram_addr_t ram_size, - hwaddr pci_hole_start, - hwaddr pci_hole_size, - hwaddr pci_hole64_start, - hwaddr pci_hole64_size, - MemoryRegion *pci_address_space, - MemoryRegion *ram_memory) -{ - DeviceState *dev; - PCIBus *b; - PCIDevice *d; - PCIHostState *s; - PIIX3State *piix3; - PCII440FXState *f; - unsigned i; - - dev = qdev_create(NULL, "i440FX-pcihost"); - s = PCI_HOST_BRIDGE(dev); - s->address_space = address_space_mem; - b = pci_bus_new(dev, NULL, pci_address_space, - address_space_io, 0); - s->bus = b; - object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL); - qdev_init_nofail(dev); - - d = pci_create_simple(b, 0, device_name); - *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d); - f = *pi440fx_state; - f->system_memory = address_space_mem; - f->pci_address_space = pci_address_space; - f->ram_memory = ram_memory; + pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 : + ((uint64_t)1 << 62)); memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space, - pci_hole_start, pci_hole_size); - memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole); + f->below_4g_mem_size, + 0x100000000LL - f->below_4g_mem_size); + memory_region_add_subregion(f->system_memory, f->below_4g_mem_size, + &f->pci_hole); memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64", f->pci_address_space, - pci_hole64_start, pci_hole64_size); + 0x100000000LL + f->above_4g_mem_size, + pci_hole64_size); if (pci_hole64_size) { - memory_region_add_subregion(f->system_memory, pci_hole64_start, + memory_region_add_subregion(f->system_memory, + 0x100000000LL + f->above_4g_mem_size, &f->pci_hole_64bit); } + memory_region_init_alias(&f->smram_region, "smram-region", f->pci_address_space, 0xa0000, 0x20000); memory_region_add_subregion_overlap(f->system_memory, 0xa0000, &f->smram_region, 1); memory_region_set_enabled(&f->smram_region, false); + init_pam(f->ram_memory, f->system_memory, f->pci_address_space, &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); for (i = 0; i < 12; ++i) { init_pam(f->ram_memory, f->system_memory, f->pci_address_space, - &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, + &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); } - - /* Xen supports additional interrupt routes from the PCI devices to - * the IOAPIC: the four pins of each PCI device on the bus are also - * connected to the IOAPIC directly. - * These additional routes can be discovered through ACPI. */ - if (xen_enabled()) { - piix3 = DO_UPCAST(PIIX3State, dev, - pci_create_simple_multifunction(b, -1, true, "PIIX3-xen")); - pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq, - piix3, XEN_PIIX_NUM_PIRQS); - } else { - piix3 = DO_UPCAST(PIIX3State, dev, - pci_create_simple_multifunction(b, -1, true, "PIIX3")); - pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, - PIIX_NUM_PIRQS); - pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq); - } - piix3->pic = pic; - *isa_bus = DO_UPCAST(ISABus, qbus, - qdev_get_child_bus(&piix3->dev.qdev, "isa.0")); - - *piix3_devfn = piix3->dev.devfn; - - ram_size = ram_size / 8 / 1024 / 1024; - if (ram_size > 255) - ram_size = 255; - (*pi440fx_state)->dev.config[0x57]=ram_size; - + f->dev.config[0x57] = f->below_4g_mem_size; i440fx_update_memory_mappings(f); - return b; -} - -PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, - ISABus **isa_bus, qemu_irq *pic, - MemoryRegion *address_space_mem, - MemoryRegion *address_space_io, - ram_addr_t ram_size, - hwaddr pci_hole_start, - hwaddr pci_hole_size, - hwaddr pci_hole64_start, - hwaddr pci_hole64_size, - MemoryRegion *pci_memory, MemoryRegion *ram_memory) - -{ - PCIBus *b; - - b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, isa_bus, pic, - address_space_mem, address_space_io, ram_size, - pci_hole_start, pci_hole_size, - pci_hole64_start, pci_hole64_size, - pci_memory, ram_memory); - return b; + return 0; } /* PIIX3 PCI to ISA bridge */ -static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) +void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) { qemu_set_irq(piix3->pic[pic_irq], !!(piix3->pic_levels & @@ -347,13 +229,13 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) piix3_set_irq_pic(piix3, pic_irq); } -static void piix3_set_irq(void *opaque, int pirq, int level) +void piix3_set_irq(void *opaque, int pirq, int level) { PIIX3State *piix3 = opaque; piix3_set_irq_level(piix3, pirq, level); } -static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) +PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { PIIX3State *piix3 = opaque; int irq = piix3->dev.config[PIIX_PIRQC + pin]; @@ -550,7 +432,7 @@ static void i440fx_class_init(ObjectClass *klass, void *data) } static const TypeInfo i440fx_info = { - .name = "i440FX", + .name = TYPE_I440FX_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PCII440FXState), .class_init = i440fx_class_init, @@ -561,15 +443,16 @@ static void i440fx_pcihost_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - k->init = i440fx_pcihost_initfn; + k->init = i440fx_pcihost_init; dc->fw_name = "pci"; dc->no_user = 1; } static const TypeInfo i440fx_pcihost_info = { - .name = "i440FX-pcihost", + .name = TYPE_I440FX_HOST_DEVICE, .parent = TYPE_PCI_HOST_BRIDGE, .instance_size = sizeof(I440FXState), + .instance_init = i440fx_pcihost_initfn, .class_init = i440fx_pcihost_class_init, }; -- 1.7.9

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[RFC PATCH v4 12/30] acpi_ich9 : Implement memory device hotplug registers
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

This implements acpi dimm hot-add capability for q35 (ich9). The logic is the same as for the pc machine (piix4). TODO: Fix acpi irq delivery bug. Currently there is a flood of irqs when delivering an acpi interrupt (should be just one). Guest complains as follows: "irq 9: nobody cared [...] Disabling IRQ #9" where #9 is the acpi irq Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- hw/acpi_ich9.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++-- hw/acpi_ich9.h | 7 +++++- hw/lpc_ich9.c | 2 +- 3 files changed, 65 insertions(+), 5 deletions(-) diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c index c5978d3..abafbb5 100644 --- a/hw/acpi_ich9.c +++ b/hw/acpi_ich9.c @@ -48,11 +48,14 @@ static void pm_update_sci(ICH9LPCPMRegs *pm) pm1a_sts = acpi_pm1_evt_get_sts(&pm->acpi_regs); - sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) & + sci_level = ((((pm1a_sts & pm->acpi_regs.pm1.evt.en) & (ACPI_BITMASK_RT_CLOCK_ENABLE | ACPI_BITMASK_POWER_BUTTON_ENABLE | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | - ACPI_BITMASK_TIMER_ENABLE)) != 0); + ACPI_BITMASK_TIMER_ENABLE)) != 0) || + (((pm->acpi_regs.gpe.sts[0] & pm->acpi_regs.gpe.en[0]) & + (ICH9_MEM_HOTPLUG_STATUS)) != 0)); + qemu_set_irq(pm->irq, sci_level); /* schedule a timer interruption if needed */ @@ -90,6 +93,29 @@ static const MemoryRegionOps ich9_gpe_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; +static uint32_t memhp_readb(void *opaque, uint32_t addr) +{ + ICH9LPCPMRegs *s = opaque; + uint32_t val = 0; + struct gpe_regs *g = &s->gperegs; + if (addr < DIMM_BITMAP_BYTES) { + val = (uint32_t) g->mems_sts[addr]; + } + ICH9_DEBUG("memhp read %x == %x\n", addr, val); + return val; +} + +static const MemoryRegionOps ich9_memhp_ops = { + .old_portio = (MemoryRegionPortio[]) { + { + .offset = 0, .len = DIMM_BITMAP_BYTES, .size = 1, + .read = memhp_readb, + }, + PORTIO_END_OF_LIST() + }, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width) { ICH9LPCPMRegs *pm = opaque; @@ -201,8 +227,31 @@ static void pm_powerdown_req(Notifier *n, void *opaque) acpi_pm1_evt_power_down(&pm->acpi_regs); } -void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3) +static void enable_mem_device(ICH9LPCState *s, int memdevice) { + struct gpe_regs *g = &s->pm.gperegs; + s->pm.acpi_regs.gpe.sts[0] |= ICH9_MEM_HOTPLUG_STATUS; + g->mems_sts[memdevice/8] |= (1 << (memdevice%8)); +} + +static int ich9_dimm_hotplug(DeviceState *qdev, DimmDevice *dev, int + add) +{ + PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, qdev); + ICH9LPCState *s = DO_UPCAST(ICH9LPCState, d, pci_dev); + DimmDevice *slot = DIMM(dev); + + if (add) { + enable_mem_device(s, slot->idx); + } + pm_update_sci(&s->pm); + return 0; +} + +void ich9_pm_init(void *device, qemu_irq sci_irq, qemu_irq cmos_s3) +{ + ICH9LPCState *lpc = (ICH9LPCState *)device; + ICH9LPCPMRegs *pm = &lpc->pm; memory_region_init(&pm->io, "ich9-pm", ICH9_PMIO_SIZE); memory_region_set_enabled(&pm->io, false); memory_region_add_subregion(get_system_io(), 0, &pm->io); @@ -220,6 +269,12 @@ void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3) 8); memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi); + memory_region_init_io(&pm->io_memhp, &ich9_memhp_ops, pm, "apci-memhp0", + DIMM_BITMAP_BYTES); + memory_region_add_subregion(get_system_io(), ICH9_MEM_BASE, &pm->io_memhp); + + dimm_bus_hotplug(ich9_dimm_hotplug, &lpc->d.qdev); + pm->irq = sci_irq; qemu_register_reset(pm_reset, pm); pm->powerdown_notifier.notify = pm_powerdown_req; diff --git a/hw/acpi_ich9.h b/hw/acpi_ich9.h index bc221d3..4419247 100644 --- a/hw/acpi_ich9.h +++ b/hw/acpi_ich9.h @@ -23,6 +23,9 @@ #include "acpi.h" +#define ICH9_MEM_BASE 0xaf80 +#define ICH9_MEM_HOTPLUG_STATUS 8 + typedef struct ICH9LPCPMRegs { /* * In ich9 spec says that pm1_cnt register is 32bit width and @@ -33,16 +36,18 @@ typedef struct ICH9LPCPMRegs { MemoryRegion io; MemoryRegion io_gpe; MemoryRegion io_smi; + MemoryRegion io_memhp; uint32_t smi_en; uint32_t smi_sts; qemu_irq irq; /* SCI */ + struct gpe_regs gperegs; uint32_t pm_io_base; Notifier powerdown_notifier; } ICH9LPCPMRegs; -void ich9_pm_init(ICH9LPCPMRegs *pm, +void ich9_pm_init(void *lpc, qemu_irq sci_irq, qemu_irq cmos_s3_resume); void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base); extern const VMStateDescription vmstate_ich9_pm; diff --git a/hw/lpc_ich9.c b/hw/lpc_ich9.c index 878a43e..0ef7af6 100644 --- a/hw/lpc_ich9.c +++ b/hw/lpc_ich9.c @@ -352,7 +352,7 @@ void ich9_lpc_pm_init(PCIDevice *lpc_pci, qemu_irq cmos_s3) qemu_irq *sci_irq; sci_irq = qemu_allocate_irqs(ich9_set_sci, lpc, 1); - ich9_pm_init(&lpc->pm, sci_irq[0], cmos_s3); + ich9_pm_init(lpc, sci_irq[0], cmos_s3); ich9_lpc_reset(&lpc->d.qdev); } -- 1.7.9

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[RFC PATCH v4 11/30] acpi_piix4 : Implement memory device hotplug registers
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

A 32-byte register is used to present up to 256 hotplug-able memory devices to BIOS and OSPM. Hot-add and hot-remove functions trigger an ACPI hotplug event through these. Only reads are allowed from these registers. An ACPI hot-remove event but needs to wait for OSPM to eject the device. We use a single-byte register to know when OSPM has called the _EJ function for a particular dimm. A write to this byte will depopulate the respective dimm. Only writes are allowed to this byte. v1->v2: mems_sts address moved from 0xaf20 to 0xaf80 (to accomodate more space for cpu-hotplugging in the future). _EJ array is reduced to a single byte. Add documentation in docs/specs/acpi_hotplug.txt v3->v4: Removed hot-remove functions, will be added separately. Updated for memory API. Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- docs/specs/acpi_hotplug.txt | 14 +++++++++ hw/acpi.h | 5 +++ hw/acpi_piix4.c | 65 +++++++++++++++++++++++++++++++++++++++++- 3 files changed, 82 insertions(+), 2 deletions(-) create mode 100644 docs/specs/acpi_hotplug.txt diff --git a/docs/specs/acpi_hotplug.txt b/docs/specs/acpi_hotplug.txt new file mode 100644 index 0000000..8391713 --- /dev/null +++ b/docs/specs/acpi_hotplug.txt @@ -0,0 +1,14 @@ +QEMU<->ACPI BIOS hotplug interface +-------------------------------------- +This document describes the interface between QEMU and the ACPI BIOS for non-PCI +space. For the PCI interface please look at docs/specs/acpi_pci_hotplug.txt + +QEMU<->ACPI BIOS memory hotplug interface +-------------------------------------- + +Memory Dimm status array (IO port 0xaf80-0xaf9f, 1-byte access): +--------------------------------------------------------------- +Dimm hot-plug notification pending. One bit per slot. + +Read by ACPI BIOS GPE.3 handler to notify OS of memory hot-add or hot-remove +events. Read-only. diff --git a/hw/acpi.h b/hw/acpi.h index afda153..dc617d3 100644 --- a/hw/acpi.h +++ b/hw/acpi.h @@ -120,6 +120,11 @@ struct ACPIREGS { Notifier wakeup; }; +#include "dimm.h" +struct gpe_regs { + uint8_t mems_sts[DIMM_BITMAP_BYTES]; +}; + /* PM_TMR */ void acpi_pm_tmr_update(ACPIREGS *ar, bool enable); void acpi_pm_tmr_calc_overflow_time(ACPIREGS *ar); diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c index 0b5b0d3..879d8a0 100644 --- a/hw/acpi_piix4.c +++ b/hw/acpi_piix4.c @@ -29,6 +29,8 @@ #include "ioport.h" #include "fw_cfg.h" #include "exec-memory.h" +#include "sysbus.h" +#include "dimm.h" //#define DEBUG @@ -47,7 +49,9 @@ #define PCI_DOWN_BASE 0xae04 #define PCI_EJ_BASE 0xae08 #define PCI_RMV_BASE 0xae0c +#define MEM_BASE 0xaf80 +#define PIIX4_MEM_HOTPLUG_STATUS 8 #define PIIX4_PCI_HOTPLUG_STATUS 2 struct pci_status { @@ -60,6 +64,7 @@ typedef struct PIIX4PMState { MemoryRegion io; MemoryRegion io_gpe; MemoryRegion io_pci; + MemoryRegion io_memhp; ACPIREGS ar; APMState apm; @@ -74,6 +79,7 @@ typedef struct PIIX4PMState { Notifier powerdown_notifier; /* for pci hotplug */ + struct gpe_regs gperegs; struct pci_status pci0_status; uint32_t pci0_hotplug_enable; uint32_t pci0_slot_device_present; @@ -98,8 +104,8 @@ static void pm_update_sci(PIIX4PMState *s) ACPI_BITMASK_POWER_BUTTON_ENABLE | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | ACPI_BITMASK_TIMER_ENABLE)) != 0) || - (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) - & PIIX4_PCI_HOTPLUG_STATUS) != 0); + (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) & + (PIIX4_PCI_HOTPLUG_STATUS | PIIX4_MEM_HOTPLUG_STATUS)) != 0); qemu_set_irq(s->irq, sci_level); /* schedule a timer interruption if needed */ @@ -526,6 +532,29 @@ static const MemoryRegionOps piix4_gpe_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; +static uint32_t memhp_readb(void *opaque, uint32_t addr) +{ + PIIX4PMState *s = opaque; + uint32_t val = 0; + struct gpe_regs *g = &s->gperegs; + if (addr < DIMM_BITMAP_BYTES) { + val = (uint32_t) g->mems_sts[addr]; + } + PIIX4_DPRINTF(stderr, "memhp read %x == %x\n", addr, val); + return val; +} + +static const MemoryRegionOps piix4_memhp_ops = { + .old_portio = (MemoryRegionPortio[]) { + { + .offset = 0, .len = DIMM_BITMAP_BYTES, .size = 1, + .read = memhp_readb, + }, + PORTIO_END_OF_LIST() + }, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + static uint32_t pci_up_read(void *opaque, uint32_t addr) { PIIX4PMState *s = opaque; @@ -592,9 +621,11 @@ static const MemoryRegionOps piix4_pci_ops = { static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, PCIHotplugState state); +static int piix4_dimm_hotplug(DeviceState *qdev, DimmDevice *dev, int add); static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) { + int i = 0; memory_region_init_io(&s->io_gpe, &piix4_gpe_ops, s, "apci-gpe0", GPE_LEN); memory_region_add_subregion(get_system_io(), GPE_BASE, &s->io_gpe); @@ -603,7 +634,16 @@ static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) PCI_HOTPLUG_SIZE); memory_region_add_subregion(get_system_io(), PCI_HOTPLUG_ADDR, &s->io_pci); + memory_region_init_io(&s->io_memhp, &piix4_memhp_ops, s, "apci-memhp0", + DIMM_BITMAP_BYTES); + memory_region_add_subregion(get_system_io(), MEM_BASE, &s->io_memhp); + + for (i = 0; i < DIMM_BITMAP_BYTES; i++) { + s->gperegs.mems_sts[i] = 0; + } + pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev); + dimm_bus_hotplug(piix4_dimm_hotplug, &s->dev.qdev); } static void enable_device(PIIX4PMState *s, int slot) @@ -618,6 +658,27 @@ static void disable_device(PIIX4PMState *s, int slot) s->pci0_status.down |= (1U << slot); } +static void enable_mem_device(PIIX4PMState *s, int memdevice) +{ + struct gpe_regs *g = &s->gperegs; + s->ar.gpe.sts[0] |= PIIX4_MEM_HOTPLUG_STATUS; + g->mems_sts[memdevice/8] |= (1 << (memdevice%8)); +} + +static int piix4_dimm_hotplug(DeviceState *qdev, DimmDevice *dev, int + add) +{ + PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, qdev); + PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, pci_dev); + DimmDevice *slot = DIMM(dev); + + if (add) { + enable_mem_device(s, slot->idx); + } + pm_update_sci(s); + return 0; +} + static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, PCIHotplugState state) { -- 1.7.9

1 0

[RFC PATCH v4 10/30] vl: handle "-device dimm"
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- vl.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 51 insertions(+), 0 deletions(-) diff --git a/vl.c b/vl.c index a3ab384..8406933 100644 --- a/vl.c +++ b/vl.c @@ -169,6 +169,7 @@ int main(int argc, char **argv) #include "ui/qemu-spice.h" #include "qapi/string-input-visitor.h" +#include "hw/dimm.h" //#define DEBUG_NET //#define DEBUG_SLIRP @@ -249,6 +250,7 @@ static QTAILQ_HEAD(, FWBootEntry) fw_boot_order = int nb_numa_nodes; uint64_t node_mem[MAX_NODES]; unsigned long *node_cpumask[MAX_NODES]; +int nb_hp_dimms; uint8_t qemu_uuid[16]; @@ -2065,6 +2067,50 @@ static int chardev_init_func(QemuOpts *opts, void *opaque) return 0; } +static int dimmcfg_init_func(QemuOpts *opts, void *opaque) +{ + const char *driver; + const char *id; + uint64_t node, size; + uint32_t populated; + const char *buf, *busbuf; + + /* DimmDevice configuration needs to be known in order to initialize chipset + * with correct memory and pci ranges. But all devices are created after + * chipset / machine initialization. In * order to avoid this problem, we + * parse dimm information earlier into dimmcfg structs. */ + + driver = qemu_opt_get(opts, "driver"); + if (!strcmp(driver, "dimm")) { + + id = qemu_opts_id(opts); + buf = qemu_opt_get(opts, "size"); + parse_option_size("size", buf, &size, NULL); + buf = qemu_opt_get(opts, "node"); + parse_option_number("node", buf, &node, NULL); + busbuf = qemu_opt_get(opts, "bus"); + buf = qemu_opt_get(opts, "populated"); + if (!buf) { + populated = 0; + } else { + populated = strcmp(buf, "on") ? 0 : 1; + } + + dimm_config_create((char *)id, size, busbuf ? busbuf : "membus.0", + node, nb_hp_dimms, populated); + + /* if !populated, we just keep the config. The real device + * will be created in the future with a normal device_add + * command. */ + if (!populated) { + qemu_opts_del(opts); + } + nb_hp_dimms++; + } + + return 0; +} + #ifdef CONFIG_VIRTFS static int fsdev_init_func(QemuOpts *opts, void *opaque) { @@ -3859,6 +3905,11 @@ int main(int argc, char **argv, char **envp) } qemu_add_globals(); + /* init generic devices */ + if (qemu_opts_foreach(qemu_find_opts("device"), + dimmcfg_init_func, NULL, 1) != 0) { + exit(1); + } qdev_machine_init(); QEMUMachineInitArgs args = { .ram_size = ram_size, -- 1.7.9

1 0

[RFC PATCH v4 09/30] Implement dimm device abstraction
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

Each hotplug-able memory slot is a DimmDevice. All DimmDevices are attached to a new bus called DimmBus. This bus is introduced so that we no longer depend on hotplug-capability of main system bus (the main bus does not allow hotplugging). The DimmBus should be attached to a chipset Device (i440fx in case of the pc) A hot-add operation for a particular dimm: - creates a new DimmDevice and attaches it to the DimmBus - creates a new MemoryRegion of the given physical address offset, size and node proximity, and attaches it to main system memory as a sub_region. Hotplug operations are done through normal device_add commands. Also add properties to DimmDevice. v3->v4: Removed hot-remove functions. Will be offered in separate patches. Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- hw/Makefile.objs | 2 +- hw/dimm.c | 245 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/dimm.h | 89 ++++++++++++++++++++ 3 files changed, 335 insertions(+), 1 deletions(-) create mode 100644 hw/dimm.c create mode 100644 hw/dimm.h diff --git a/hw/Makefile.objs b/hw/Makefile.objs index d581d8d..51494c9 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -29,7 +29,7 @@ common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o common-obj-$(CONFIG_PCSPK) += pcspk.o common-obj-$(CONFIG_PCKBD) += pckbd.o common-obj-$(CONFIG_FDC) += fdc.o -common-obj-$(CONFIG_ACPI) += acpi.o acpi_piix4.o acpi_ich9.o smbus_ich9.o +common-obj-$(CONFIG_ACPI) += acpi.o acpi_piix4.o acpi_ich9.o smbus_ich9.o dimm.o common-obj-$(CONFIG_APM) += pm_smbus.o apm.o common-obj-$(CONFIG_DMA) += dma.o common-obj-$(CONFIG_I82374) += i82374.o diff --git a/hw/dimm.c b/hw/dimm.c new file mode 100644 index 0000000..e384952 --- /dev/null +++ b/hw/dimm.c @@ -0,0 +1,245 @@ +/* + * Dimm device for Memory Hotplug + * + * Copyright ProfitBricks GmbH 2012 + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/> + */ + +#include "trace.h" +#include "qdev.h" +#include "dimm.h" +#include <time.h> +#include "../exec-memory.h" +#include "qmp-commands.h" + +/* the following list is used to hold dimm config info before machine + * is initialized. After machine init, the list is not used anymore.*/ +static DimmConfiglist dimmconfig_list = + QTAILQ_HEAD_INITIALIZER(dimmconfig_list); + +/* the list of memory buses */ +static QLIST_HEAD(, DimmBus) memory_buses; + +static void dimmbus_dev_print(Monitor *mon, DeviceState *dev, int indent); +static char *dimmbus_get_fw_dev_path(DeviceState *dev); + +static Property dimm_properties[] = { + DEFINE_PROP_UINT64("start", DimmDevice, start, 0), + DEFINE_PROP_SIZE("size", DimmDevice, size, DEFAULT_DIMMSIZE), + DEFINE_PROP_UINT32("node", DimmDevice, node, 0), + DEFINE_PROP_BIT("populated", DimmDevice, populated, 0, false), + DEFINE_PROP_END_OF_LIST(), +}; + +static void dimmbus_dev_print(Monitor *mon, DeviceState *dev, int indent) +{ +} + +static char *dimmbus_get_fw_dev_path(DeviceState *dev) +{ + char path[40]; + + snprintf(path, sizeof(path), "%s", qdev_fw_name(dev)); + return strdup(path); +} + +static void dimm_bus_class_init(ObjectClass *klass, void *data) +{ + BusClass *k = BUS_CLASS(klass); + + k->print_dev = dimmbus_dev_print; + k->get_fw_dev_path = dimmbus_get_fw_dev_path; +} + +static void dimm_bus_initfn(Object *obj) +{ + DimmBus *bus = DIMM_BUS(obj); + QTAILQ_INIT(&bus->dimmconfig_list); + QTAILQ_INIT(&bus->dimmlist); +} + +static const TypeInfo dimm_bus_info = { + .name = TYPE_DIMM_BUS, + .parent = TYPE_BUS, + .instance_size = sizeof(DimmBus), + .instance_init = dimm_bus_initfn, + .class_init = dimm_bus_class_init, +}; + +DimmBus *dimm_bus_create(Object *parent, const char *name, uint32_t max_dimms, + dimm_calcoffset_fn pmc_set_offset) +{ + DimmBus *memory_bus; + DimmConfig *dimm_cfg, *next_cfg; + uint32_t num_dimms = 0; + + memory_bus = g_malloc0(dimm_bus_info.instance_size); + memory_bus->qbus.name = name ? g_strdup(name) : "membus.0"; + qbus_create_inplace(&memory_bus->qbus, TYPE_DIMM_BUS, DEVICE(parent), + name); + + QTAILQ_FOREACH_SAFE(dimm_cfg, &dimmconfig_list, nextdimmcfg, next_cfg) { + if (!strcmp(memory_bus->qbus.name, dimm_cfg->bus_name)) { + if (max_dimms && (num_dimms == max_dimms)) { + fprintf(stderr, "Bus %s can only accept %u number of DIMMs\n", + name, max_dimms); + } + QTAILQ_REMOVE(&dimmconfig_list, dimm_cfg, nextdimmcfg); + QTAILQ_INSERT_TAIL(&memory_bus->dimmconfig_list, dimm_cfg, + nextdimmcfg); + + dimm_cfg->start = pmc_set_offset(DEVICE(parent), dimm_cfg->size); + num_dimms++; + } + } + QLIST_INSERT_HEAD(&memory_buses, memory_bus, next); + return memory_bus; +} + +static void dimm_populate(DimmDevice *s) +{ + DeviceState *dev = (DeviceState *)s; + MemoryRegion *new = NULL; + + new = g_malloc(sizeof(MemoryRegion)); + memory_region_init_ram(new, dev->id, s->size); + vmstate_register_ram_global(new); + memory_region_add_subregion(get_system_memory(), s->start, new); + s->populated = true; + s->mr = new; +} + +void dimm_config_create(char *id, uint64_t size, const char *bus, uint64_t node, + uint32_t dimm_idx, uint32_t populated) +{ + DimmConfig *dimm_cfg; + dimm_cfg = (DimmConfig *) g_malloc0(sizeof(DimmConfig)); + dimm_cfg->name = strdup(id); + dimm_cfg->bus_name = strdup(bus); + dimm_cfg->idx = dimm_idx; + dimm_cfg->start = 0; + dimm_cfg->size = size; + dimm_cfg->node = node; + dimm_cfg->populated = populated; + + QTAILQ_INSERT_TAIL(&dimmconfig_list, dimm_cfg, nextdimmcfg); +} + +void dimm_bus_hotplug(dimm_hotplug_fn hotplug, DeviceState *qdev) +{ + DimmBus *bus; + QLIST_FOREACH(bus, &memory_buses, next) { + assert(bus); + bus->qbus.allow_hotplug = 1; + bus->dimm_hotplug_qdev = qdev; + bus->dimm_hotplug = hotplug; + } +} + +static void dimm_plug_device(DimmDevice *slot) +{ + DimmBus *bus = DIMM_BUS(qdev_get_parent_bus(&slot->qdev)); + + dimm_populate(slot); + if (bus->dimm_hotplug) { + bus->dimm_hotplug(bus->dimm_hotplug_qdev, slot, 1); + } +} + +static int dimm_unplug_device(DeviceState *qdev) +{ + return 1; +} + +static DimmConfig *dimmcfg_find_from_name(DimmBus *bus, const char *name) +{ + DimmConfig *slot; + + QTAILQ_FOREACH(slot, &bus->dimmconfig_list, nextdimmcfg) { + if (!strcmp(slot->name, name)) { + return slot; + } + } + return NULL; +} + +void dimm_setup_fwcfg_layout(uint64_t *fw_cfg_slots) +{ + DimmConfig *slot; + DimmBus *bus; + + QLIST_FOREACH(bus, &memory_buses, next) { + QTAILQ_FOREACH(slot, &bus->dimmconfig_list, nextdimmcfg) { + assert(slot->start); + fw_cfg_slots[3 * slot->idx] = cpu_to_le64(slot->start); + fw_cfg_slots[3 * slot->idx + 1] = cpu_to_le64(slot->size); + fw_cfg_slots[3 * slot->idx + 2] = cpu_to_le64(slot->node); + } + } +} + +static int dimm_init(DeviceState *s) +{ + DimmBus *bus = DIMM_BUS(qdev_get_parent_bus(s)); + DimmDevice *slot; + DimmConfig *slotcfg; + + slot = DIMM(s); + slot->mr = NULL; + + slotcfg = dimmcfg_find_from_name(bus, s->id); + + if (!slotcfg) { + fprintf(stderr, "%s no config for slot %s found\n", + __func__, s->id); + return 1; + } + + slot->idx = slotcfg->idx; + assert(slotcfg->start); + slot->start = slotcfg->start; + slot->size = slotcfg->size; + slot->node = slotcfg->node; + + QTAILQ_INSERT_TAIL(&bus->dimmlist, slot, nextdimm); + dimm_plug_device(slot); + + return 0; +} + + +static void dimm_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->props = dimm_properties; + dc->unplug = dimm_unplug_device; + dc->init = dimm_init; + dc->bus_type = TYPE_DIMM_BUS; +} + +static TypeInfo dimm_info = { + .name = TYPE_DIMM, + .parent = TYPE_DEVICE, + .instance_size = sizeof(DimmDevice), + .class_init = dimm_class_init, +}; + +static void dimm_register_types(void) +{ + type_register_static(&dimm_bus_info); + type_register_static(&dimm_info); +} + +type_init(dimm_register_types) diff --git a/hw/dimm.h b/hw/dimm.h new file mode 100644 index 0000000..75a6911 --- /dev/null +++ b/hw/dimm.h @@ -0,0 +1,89 @@ +#ifndef QEMU_DIMM_H +#define QEMU_DIMM_H + +#include "qemu-common.h" +#include "memory.h" +#include "sysbus.h" +#include "qapi-types.h" +#include "qemu-queue.h" +#include "cpus.h" +#define MAX_DIMMS 255 +#define DIMM_BITMAP_BYTES ((MAX_DIMMS + 7) / 8) +#define DEFAULT_DIMMSIZE (1024*1024*1024) + +typedef enum { + DIMM_REMOVE_SUCCESS = 0, + DIMM_REMOVE_FAIL = 1, + DIMM_ADD_SUCCESS = 2, + DIMM_ADD_FAIL = 3 +} dimm_hp_result_code; + +#define TYPE_DIMM "dimm" +#define DIMM(obj) \ + OBJECT_CHECK(DimmDevice, (obj), TYPE_DIMM) +#define DIMM_CLASS(klass) \ + OBJECT_CLASS_CHECK(DimmDeviceClass, (klass), TYPE_DIMM) +#define DIMM_GET_CLASS(obj) \ + OBJECT_GET_CLASS(DimmDeviceClass, (obj), TYPE_DIMM) + +typedef struct DimmDevice DimmDevice; +typedef QTAILQ_HEAD(DimmConfiglist, DimmConfig) DimmConfiglist; + +typedef struct DimmDeviceClass { + DeviceClass parent_class; + + int (*init)(DimmDevice *dev); +} DimmDeviceClass; + +struct DimmDevice { + DeviceState qdev; + uint32_t idx; /* index in memory hotplug register/bitmap */ + ram_addr_t start; /* starting physical address */ + ram_addr_t size; + uint32_t node; /* numa node proximity */ + uint32_t populated; /* 1 means device has been hotplugged. Default is 0. */ + MemoryRegion *mr; /* MemoryRegion for this slot. !NULL only if populated */ + QTAILQ_ENTRY(DimmDevice) nextdimm; +}; + +typedef struct DimmConfig { + const char *name; + uint32_t idx; /* index in linear memory hotplug bitmap */ + const char *bus_name; + ram_addr_t start; /* starting physical address */ + ram_addr_t size; + uint32_t node; /* numa node proximity */ + uint32_t populated; /* 1 means device has been hotplugged. Default is 0. */ + QTAILQ_ENTRY(DimmConfig) nextdimmcfg; +} DimmConfig; + +typedef int (*dimm_hotplug_fn)(DeviceState *qdev, DimmDevice *dev, int add); +typedef hwaddr(*dimm_calcoffset_fn)(DeviceState *dev, uint64_t size); + +#define TYPE_DIMM_BUS "dimmbus" +#define DIMM_BUS(obj) OBJECT_CHECK(DimmBus, (obj), TYPE_DIMM_BUS) + +typedef struct DimmBus { + BusState qbus; + DeviceState *dimm_hotplug_qdev; + dimm_hotplug_fn dimm_hotplug; + DimmConfiglist dimmconfig_list; + QTAILQ_HEAD(Dimmlist, DimmDevice) dimmlist; + QLIST_ENTRY(DimmBus) next; +} DimmBus; + +struct dimm_hp_result { + const char *dimmname; + dimm_hp_result_code ret; + QTAILQ_ENTRY(dimm_hp_result) next; +}; + +void dimm_bus_hotplug(dimm_hotplug_fn hotplug, DeviceState *qdev); +void dimm_setup_fwcfg_layout(uint64_t *fw_cfg_slots); +int dimm_add(char *id); +DimmBus *dimm_bus_create(Object *parent, const char *name, uint32_t max_dimms, + dimm_calcoffset_fn pmc_set_offset); +void dimm_config_create(char *id, uint64_t size, const char *bus, uint64_t node, + uint32_t dimm_idx, uint32_t populated); + +#endif -- 1.7.9

1 0

[RFC PATCH v4 08/30] qemu-option: export parse_option_number
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- qemu-option.c | 2 +- qemu-option.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletions(-) diff --git a/qemu-option.c b/qemu-option.c index 38e0a11..88fd370 100644 --- a/qemu-option.c +++ b/qemu-option.c @@ -185,7 +185,7 @@ static void parse_option_bool(const char *name, const char *value, bool *ret, } } -static void parse_option_number(const char *name, const char *value, +void parse_option_number(const char *name, const char *value, uint64_t *ret, Error **errp) { char *postfix; diff --git a/qemu-option.h b/qemu-option.h index b8ee5b3..8b7235f 100644 --- a/qemu-option.h +++ b/qemu-option.h @@ -154,5 +154,7 @@ int qemu_opts_foreach(QemuOptsList *list, qemu_opts_loopfunc func, void *opaque, int abort_on_failure); void parse_option_size(const char *name, const char *value, uint64_t *ret, Error **errp); +void parse_option_number(const char *name, const char *value, + uint64_t *ret, Error **errp); #endif -- 1.7.9

1 0

[RFC PATCH v4 07/30] Add SIZE type to qdev properties
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

This patch adds a 'SIZE' type property to qdev. It will make dimm description more convenient by allowing sizes to be specified with K,M,G,T prefixes instead of number of bytes e.g.: -device dimm,id=mem0,size=2G,bus=membus.0 Credits go to Ian Molton for original patch. See: http://patchwork.ozlabs.org/patch/38835/ Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- hw/qdev-properties.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++ hw/qdev-properties.h | 3 ++ qemu-option.c | 2 +- qemu-option.h | 2 + 4 files changed, 66 insertions(+), 1 deletions(-) diff --git a/hw/qdev-properties.c b/hw/qdev-properties.c index 81d901c..a77f760 100644 --- a/hw/qdev-properties.c +++ b/hw/qdev-properties.c @@ -1279,3 +1279,63 @@ void qemu_add_globals(void) { qemu_opts_foreach(qemu_find_opts("global"), qdev_add_one_global, NULL, 0); } + +/* --- 64bit unsigned int 'size' type --- */ + +static void get_size(Object *obj, Visitor *v, void *opaque, + const char *name, Error **errp) +{ + DeviceState *dev = DEVICE(obj); + Property *prop = opaque; + uint64_t *ptr = qdev_get_prop_ptr(dev, prop); + + visit_type_size(v, ptr, name, errp); +} + +static void set_size(Object *obj, Visitor *v, void *opaque, + const char *name, Error **errp) +{ + DeviceState *dev = DEVICE(obj); + Property *prop = opaque; + uint64_t *ptr = qdev_get_prop_ptr(dev, prop); + + if (dev->state != DEV_STATE_CREATED) { + error_set(errp, QERR_PERMISSION_DENIED); + return; + } + + visit_type_size(v, ptr, name, errp); +} + +static int parse_size(DeviceState *dev, Property *prop, const char *str) +{ + uint64_t *ptr = qdev_get_prop_ptr(dev, prop); + Error *errp = NULL; + + if (str != NULL) { + parse_option_size(prop->name, str, ptr, &errp); + } + assert_no_error(errp); + return 0; +} + +static int print_size(DeviceState *dev, Property *prop, char *dest, size_t len) +{ + uint64_t *ptr = qdev_get_prop_ptr(dev, prop); + char suffixes[] = {'T', 'G', 'M', 'K', 'B'}; + int i = 0; + uint64_t div; + + for (div = (long int)1 << 40; !(*ptr / div) ; div >>= 10) { + i++; + } + return snprintf(dest, len, "%0.03f%c", (double)*ptr/div, suffixes[i]); +} + +PropertyInfo qdev_prop_size = { + .name = "size", + .parse = parse_size, + .print = print_size, + .get = get_size, + .set = set_size, +}; diff --git a/hw/qdev-properties.h b/hw/qdev-properties.h index 5b046ab..0182bef 100644 --- a/hw/qdev-properties.h +++ b/hw/qdev-properties.h @@ -14,6 +14,7 @@ extern PropertyInfo qdev_prop_uint64; extern PropertyInfo qdev_prop_hex8; extern PropertyInfo qdev_prop_hex32; extern PropertyInfo qdev_prop_hex64; +extern PropertyInfo qdev_prop_size; extern PropertyInfo qdev_prop_string; extern PropertyInfo qdev_prop_chr; extern PropertyInfo qdev_prop_ptr; @@ -67,6 +68,8 @@ extern PropertyInfo qdev_prop_pci_host_devaddr; DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_hex32, uint32_t) #define DEFINE_PROP_HEX64(_n, _s, _f, _d) \ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_hex64, uint64_t) +#define DEFINE_PROP_SIZE(_n, _s, _f, _d) \ + DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_size, uint64_t) #define DEFINE_PROP_PCI_DEVFN(_n, _s, _f, _d) \ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_pci_devfn, int32_t) diff --git a/qemu-option.c b/qemu-option.c index 27891e7..38e0a11 100644 --- a/qemu-option.c +++ b/qemu-option.c @@ -203,7 +203,7 @@ static void parse_option_number(const char *name, const char *value, } } -static void parse_option_size(const char *name, const char *value, +void parse_option_size(const char *name, const char *value, uint64_t *ret, Error **errp) { char *postfix; diff --git a/qemu-option.h b/qemu-option.h index ca72986..b8ee5b3 100644 --- a/qemu-option.h +++ b/qemu-option.h @@ -152,5 +152,7 @@ typedef int (*qemu_opts_loopfunc)(QemuOpts *opts, void *opaque); int qemu_opts_print(QemuOpts *opts, void *dummy); int qemu_opts_foreach(QemuOptsList *list, qemu_opts_loopfunc func, void *opaque, int abort_on_failure); +void parse_option_size(const char *name, const char *value, + uint64_t *ret, Error **errp); #endif -- 1.7.9

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[RFC PATCH v4 06/30] qapi: make visit_type_size fallback to type_int
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

Currently visit_type_size checks if the visitor's type_size function pointer is NULL. If not, it calls it, otherwise it calls v->type_uint64(). But neither of these pointers are ever set. Fallback to calling v->type_int() in this third (default) case. Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- qapi/qapi-visit-core.c | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/qapi/qapi-visit-core.c b/qapi/qapi-visit-core.c index 7a82b63..497e693 100644 --- a/qapi/qapi-visit-core.c +++ b/qapi/qapi-visit-core.c @@ -236,8 +236,17 @@ void visit_type_int64(Visitor *v, int64_t *obj, const char *name, Error **errp) void visit_type_size(Visitor *v, uint64_t *obj, const char *name, Error **errp) { + int64_t value; if (!error_is_set(errp)) { - (v->type_size ? v->type_size : v->type_uint64)(v, obj, name, errp); + if (v->type_size) { + v->type_size(v, obj, name, errp); + } else if (v->type_uint64) { + v->type_uint64(v, obj, name, errp); + } else { + value = *obj; + v->type_int(v, &value, name, errp); + *obj = value; + } } } -- 1.7.9

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[RFC PATCH v4 05/30] q35: Add memory hotplug handler
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

--- src/q35-acpi-dsdt.dsl | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/q35-acpi-dsdt.dsl b/src/q35-acpi-dsdt.dsl index c031d83..5b28d72 100644 --- a/src/q35-acpi-dsdt.dsl +++ b/src/q35-acpi-dsdt.dsl @@ -403,7 +403,7 @@ DefinitionBlock ( } #include "acpi-dsdt-cpu-hotplug.dsl" - +#include "acpi-dsdt-mem-hotplug.dsl" /**************************************************************** * General purpose events @@ -418,7 +418,9 @@ DefinitionBlock ( // CPU hotplug event \_SB.PRSC() } - Method(_L02) { + Method(_E02) { + // Memory hotplug event + \_SB.MESC() } Method(_L03) { } -- 1.7.9

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[RFC PATCH v4 04/30] acpi: generate hotplug memory devices
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

The memory device generation is guided by qemu paravirt info. Seabios first uses the info to setup SRAT entries for the hotplug-able memory slots. Afterwards, build_memssdt uses the created SRAT entries to generate appropriate memory device objects. One memory device (and corresponding SRAT entry) is generated for each hotplug-able qemu memslot. Currently no SSDT memory device is created for initial system memory. We only support up to 255 DIMMs for now (PackageOp used for the MEON array can only describe an array of at most 255 elements. VarPackageOp would be needed to support more than 255 devices) v1->v2: Seabios reads mems_sts from qemu to build e820_map SSDT size and some offsets are calculated with extraction macros. --- src/acpi.c | 158 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 files changed, 152 insertions(+), 6 deletions(-) diff --git a/src/acpi.c b/src/acpi.c index 6267d7b..82231da 100644 --- a/src/acpi.c +++ b/src/acpi.c @@ -14,6 +14,7 @@ #include "ioport.h" // inl #include "paravirt.h" // qemu_cfg_irq0_override #include "dev-q35.h" // qemu_cfg_irq0_override +#include "memmap.h" /****************************************************/ /* ACPI tables init */ @@ -446,11 +447,26 @@ encodeLen(u8 *ssdt_ptr, int length, int bytes) #define PCIHP_AML (ssdp_pcihp_aml + *ssdt_pcihp_start) #define PCI_SLOTS 32 +/* 0x5B 0x82 DeviceOp PkgLength NameString DimmID */ +#define MEM_BASE 0xaf80 +#define MEM_AML (ssdm_mem_aml + *ssdt_mem_start) +#define MEM_SIZEOF (*ssdt_mem_end - *ssdt_mem_start) +#define MEM_OFFSET_HEX (*ssdt_mem_name - *ssdt_mem_start + 2) +#define MEM_OFFSET_ID (*ssdt_mem_id - *ssdt_mem_start) +#define MEM_OFFSET_PXM 31 +#define MEM_OFFSET_START 55 +#define MEM_OFFSET_END 63 +#define MEM_OFFSET_SIZE 79 + +u64 nb_hp_memslots = 0; +struct srat_memory_affinity *mem; + #define SSDT_SIGNATURE 0x54445353 // SSDT #define SSDT_HEADER_LENGTH 36 #include "ssdt-susp.hex" #include "ssdt-pcihp.hex" +#include "ssdt-mem.hex" #define PCI_RMV_BASE 0xae0c @@ -502,6 +518,111 @@ static void patch_pcihp(int slot, u8 *ssdt_ptr, u32 eject) } } +static void build_memdev(u8 *ssdt_ptr, int i, u64 mem_base, u64 mem_len, u8 node) +{ + memcpy(ssdt_ptr, MEM_AML, MEM_SIZEOF); + ssdt_ptr[MEM_OFFSET_HEX] = getHex(i >> 4); + ssdt_ptr[MEM_OFFSET_HEX+1] = getHex(i); + ssdt_ptr[MEM_OFFSET_ID] = i; + ssdt_ptr[MEM_OFFSET_PXM] = node; + *(u64*)(ssdt_ptr + MEM_OFFSET_START) = mem_base; + *(u64*)(ssdt_ptr + MEM_OFFSET_END) = mem_base + mem_len; + *(u64*)(ssdt_ptr + MEM_OFFSET_SIZE) = mem_len; +} + +static void* +build_memssdt(void) +{ + u64 mem_base; + u64 mem_len; + u8 node; + int i; + struct srat_memory_affinity *entry = mem; + u64 nb_memdevs = nb_hp_memslots; + u8 memslot_status, enabled; + + int length = ((1+3+4) + + (nb_memdevs * MEM_SIZEOF) + + (1+2+5+(12*nb_memdevs)) + + (6+2+1+(1*nb_memdevs))); + u8 *ssdt = malloc_high(sizeof(struct acpi_table_header) + length); + if (! ssdt) { + warn_noalloc(); + return NULL; + } + u8 *ssdt_ptr = ssdt + sizeof(struct acpi_table_header); + + // build Scope(_SB_) header + *(ssdt_ptr++) = 0x10; // ScopeOp + ssdt_ptr = encodeLen(ssdt_ptr, length-1, 3); + *(ssdt_ptr++) = '_'; + *(ssdt_ptr++) = 'S'; + *(ssdt_ptr++) = 'B'; + *(ssdt_ptr++) = '_'; + + for (i = 0; i < nb_memdevs; i++) { + mem_base = (((u64)(entry->base_addr_high) << 32 )| entry->base_addr_low); + mem_len = (((u64)(entry->length_high) << 32 )| entry->length_low); + node = entry->proximity[0]; + build_memdev(ssdt_ptr, i, mem_base, mem_len, node); + ssdt_ptr += MEM_SIZEOF; + entry++; + } + + // build "Method(MTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CM00, Arg1)} ...}" + *(ssdt_ptr++) = 0x14; // MethodOp + ssdt_ptr = encodeLen(ssdt_ptr, 2+5+(12*nb_memdevs), 2); + *(ssdt_ptr++) = 'M'; + *(ssdt_ptr++) = 'T'; + *(ssdt_ptr++) = 'F'; + *(ssdt_ptr++) = 'Y'; + *(ssdt_ptr++) = 0x02; + for (i=0; i<nb_memdevs; i++) { + *(ssdt_ptr++) = 0xA0; // IfOp + ssdt_ptr = encodeLen(ssdt_ptr, 11, 1); + *(ssdt_ptr++) = 0x93; // LEqualOp + *(ssdt_ptr++) = 0x68; // Arg0Op + *(ssdt_ptr++) = 0x0A; // BytePrefix + *(ssdt_ptr++) = i; + *(ssdt_ptr++) = 0x86; // NotifyOp + *(ssdt_ptr++) = 'M'; + *(ssdt_ptr++) = 'P'; + *(ssdt_ptr++) = getHex(i >> 4); + *(ssdt_ptr++) = getHex(i); + *(ssdt_ptr++) = 0x69; // Arg1Op + } + + // build "Name(MEON, Package() { One, One, ..., Zero, Zero, ... })" + *(ssdt_ptr++) = 0x08; // NameOp + *(ssdt_ptr++) = 'M'; + *(ssdt_ptr++) = 'E'; + *(ssdt_ptr++) = 'O'; + *(ssdt_ptr++) = 'N'; + *(ssdt_ptr++) = 0x12; // PackageOp + ssdt_ptr = encodeLen(ssdt_ptr, 2+1+(1*nb_memdevs), 2); + *(ssdt_ptr++) = nb_memdevs; + + entry = mem; + memslot_status = 0; + + for (i = 0; i < nb_memdevs; i++) { + enabled = 0; + if (i % 8 == 0) + memslot_status = inb(MEM_BASE + i/8); + enabled = memslot_status & 1; + mem_base = (((u64)(entry->base_addr_high) << 32 )| entry->base_addr_low); + mem_len = (((u64)(entry->length_high) << 32 )| entry->length_low); + *(ssdt_ptr++) = enabled ? 0x01 : 0x00; + if (enabled) + add_e820(mem_base, mem_len, E820_RAM); + memslot_status = memslot_status >> 1; + entry++; + } + build_header((void*)ssdt, SSDT_SIGNATURE, ssdt_ptr - ssdt, 1); + + return ssdt; +} + static void* build_ssdt(void) { @@ -674,9 +795,6 @@ build_srat(void) { int nb_numa_nodes = qemu_cfg_get_numa_nodes(); - if (nb_numa_nodes == 0) - return NULL; - u64 *numadata = malloc_tmphigh(sizeof(u64) * (MaxCountCPUs + nb_numa_nodes)); if (!numadata) { warn_noalloc(); @@ -685,10 +803,11 @@ build_srat(void) qemu_cfg_get_numa_data(numadata, MaxCountCPUs + nb_numa_nodes); + qemu_cfg_get_numa_data(&nb_hp_memslots, 1); struct system_resource_affinity_table *srat; int srat_size = sizeof(*srat) + sizeof(struct srat_processor_affinity) * MaxCountCPUs + - sizeof(struct srat_memory_affinity) * (nb_numa_nodes + 2); + sizeof(struct srat_memory_affinity) * (nb_numa_nodes + nb_hp_memslots + 2); srat = malloc_high(srat_size); if (!srat) { @@ -723,7 +842,7 @@ build_srat(void) * from 640k-1M and possibly another one from 3.5G-4G. */ struct srat_memory_affinity *numamem = (void*)core; - int slots = 0; + int slots = 0, node; u64 mem_len, mem_base, next_base = 0; acpi_build_srat_memory(numamem, 0, 640*1024, 0, 1); @@ -750,10 +869,36 @@ build_srat(void) next_base += (1ULL << 32) - RamSize; } acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1); + numamem++; slots++; + } - for (; slots < nb_numa_nodes + 2; slots++) { + mem = (void*)numamem; + + if (nb_hp_memslots) { + u64 *hpmemdata = malloc_tmphigh(sizeof(u64) * (3 * nb_hp_memslots)); + if (!hpmemdata) { + warn_noalloc(); + free(hpmemdata); + free(numadata); + return NULL; + } + + qemu_cfg_get_numa_data(hpmemdata, 3 * nb_hp_memslots); + + for (i = 1; i < nb_hp_memslots + 1; ++i) { + mem_base = *hpmemdata++; + mem_len = *hpmemdata++; + node = *hpmemdata++; + acpi_build_srat_memory(numamem, mem_base, mem_len, node, 1); + numamem++; + slots++; + } + free(hpmemdata); + } + + for (; slots < nb_numa_nodes + nb_hp_memslots + 2; slots++) { acpi_build_srat_memory(numamem, 0, 0, 0, 0); numamem++; } @@ -825,6 +970,7 @@ acpi_bios_init(void) ACPI_INIT_TABLE(build_madt()); ACPI_INIT_TABLE(build_hpet()); ACPI_INIT_TABLE(build_srat()); + ACPI_INIT_TABLE(build_memssdt()); if (pci->device == PCI_DEVICE_ID_INTEL_ICH9_LPC) ACPI_INIT_TABLE(build_mcfg_q35()); -- 1.7.9

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