SeaBIOS

seabios@seabios.org

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3802 discussions

Re: [SeaBIOS] [coreboot] Patch number 4 for floppy in SeaBIOS
by Gelip 07 Dec '13

07 Dec '13

Disk I/O error 08.176: Booting from Floppy... 08.176: check_recal_drive 0 08.176: floppy_drive_recal 0 08.196: floppy_media_sense 0 ftype=4 08.196: floppy_drive_readid 0 rate=0 head=0 08.553: floppy_media_sense finish 0 data_rate=0 fms=17 stype=4 08.749: Booting from 0000:7c00 09.327: floppy error: 40 04 10 01 00 01 02 09.327: invalid basic_access:96: 09.327: a=00000200 b=00000d00 c=00000101 d=00000000 ds=0000 es=0000 ss=dd80 09.328: si=00007bd2 di=00000002 bp=00007c00 sp=0000fc08 cs=0000 ip=7d6e f=0002

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Re: [SeaBIOS] [coreboot] Patch number 4 for floppy in SeaBIOS
by Gelip 07 Dec '13

07 Dec '13

My floppy is OK. I tested it in this mobo with vendor BIOS and also in other PC and working good. After apply incremental patch still Disk I/O error: 08.264: Booting from Floppy... 08.264: enter handle_13: 08.264: a=00000201 b=00000000 c=00000001 d=00000000 ds=0000 es=07c0 ss=dd80 08.264: si=00000000 di=00000000 bp=00000000 sp=0000fab8 cs=f000 ip=c9a2 f=0202 08.264: disk_op d=0x000f4500 lba=0 buf=0x00007c00 count=1 cmd=2 08.264: check_recal_drive 0 08.264: floppy_drive_recal 0 08.264: handle_0e 08.264: floppy_pio 08.264: floppy_pio 08.300: floppy_pio 08.682: handle_0e 08.682: floppy_pio 08.682: floppy_media_sense 0 ftype=4 08.682: floppy_drive_readid 0 rate=0 head=0 08.687: floppy_pio 08.689: handle_0e 08.689: floppy_media_sense finish 0 data_rate=0 fms=17 stype=4 08.690: floppy_pio 08.825: handle_0e 08.825: Booting from 0000:7c00 08.825: enter handle_13: 08.825: a=00000201 b=00000700 c=00000002 d=00000100 ds=0000 es=0000 ss=dd80 08.825: si=00007bd2 di=00000700 bp=00007c00 sp=0000fab8 cs=0000 ip=7d6e f=0002 08.825: disk_op d=0x000f4500 lba=19 buf=0x00000700 count=1 cmd=2 08.825: floppy_pio 09.008: handle_0e 09.008: enter handle_13: 09.008: a=00000201 b=00000700 c=00000010 d=00000100 ds=0000 es=0000 ss=dd80 09.008: si=00007bd2 di=00000002 bp=00007c00 sp=0000fab8 cs=0000 ip=7d6e f=0002 09.008: disk_op d=0x000f4500 lba=33 buf=0x00000700 count=1 cmd=2 09.014: floppy_pio 09.138: handle_0e 09.138: enter handle_13: 09.138: a=00000201 b=00000900 c=00000011 d=00000100 ds=0000 es=0000 ss=dd80 09.138: si=00007bd2 di=00000002 bp=00007c00 sp=0000fab8 cs=0000 ip=7d6e f=0006 09.149: disk_op d=0x000f4500 lba=34 buf=0x00000900 count=1 cmd=2 09.149: floppy_pio 09.335: handle_0e 09.335: enter handle_13: 09.335: a=00000201 b=00000b00 c=00000012 d=00000100 ds=0000 es=0000 ss=dd80 09.335: si=00007bd2 di=00000002 bp=00007c00 sp=0000fab8 cs=0000 ip=7d6e f=0006 09.335: disk_op d=0x000f4500 lba=35 buf=0x00000b00 count=1 cmd=2 09.341: floppy_pio 09.721: handle_0e 09.721: floppy error: 40 04 10 01 00 00 02 09.721: invalid basic_access:96: 09.721: a=00000200 b=00000b00 c=00000012 d=00000100 ds=0000 es=0000 ss=dd80 09.722: si=00007bd2 di=00000002 bp=00007c00 sp=0000fab8 cs=0000 ip=7d6e f=0006 ================================================================================= I write how I build coreboot with SeaBIOS: a.. make menuconfig and set payload SeaBIOS to master b.. cd /coreboot/build c.. rm -R seabios d.. git clone git://git.seabios.org/seabios.git seabios e.. apply patches to src/config.h and src/hw/floppy.c f.. change DEBUG_LEVEL default 1 to 8 in src/Kconfig g.. cd ../.. h.. make i.. ./build/seabios/scripts/encodeint.py floppy0 4 j.. ./build/cbfstool build/coreboot.rom add -f floppy0 -n etc/floppy0 -t raw

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[PATCH] xhci: allocate scratch pad buffers
by Gerd Hoffmann 07 Dec '13

07 Dec '13

Untested. Anyone who tried to get xhci run on real hardware is welcome to test whenever this patch improves things. Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/hw/usb-xhci.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/hw/usb-xhci.c b/src/hw/usb-xhci.c index 66ce3c4..6c24855 100644 --- a/src/hw/usb-xhci.c +++ b/src/hw/usb-xhci.c @@ -710,6 +710,19 @@ configure_xhci(void *data) writel(&xhci->ir->erstba_high, 0); xhci->evts->cs = 1; + reg = readl(&xhci->caps->hcsparams2); + u32 spb = reg >> 27; + if (spb) { + dprintf(3, "%s: setup %d scratch pad buffers\n", __func__, spb); + u64 *spba = memalign_high(64, sizeof(*spba) * spb); + void *pad = memalign_high(4096, 4096 * spb); + int i; + for (i = 0; i < spb; i++) + spba[i] = (u32)pad + (i * 4096); + xhci->devs[0].ptr_low = (u32)spba; + xhci->devs[0].ptr_high = 0; + } + reg = readl(&xhci->op->usbcmd); reg |= XHCI_CMD_RS; writel(&xhci->op->usbcmd, reg); -- 1.8.3.1

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Re: [SeaBIOS] [coreboot] Patch number 4 for floppy in SeaBIOS
by Gelip 07 Dec '13

07 Dec '13

Still Disk I/O error: 07.178: Booting from Floppy... 07.198: enter handle_13: 07.198: a=00000201 b=00000000 c=00000001 d=00000000 ds=0000 es=07c0 ss=dd80 07.198: si=00000000 di=00000000 bp=00000000 sp=0000fae8 cs=f000 ip=c9a1 f=0202 07.198: disk_op d=0x000f4530 lba=0 buf=0x00007c00 count=1 cmd=2 07.198: check_recal_drive 0 07.198: floppy_drive_recal 0 07.198: handle_0e 07.198: floppy_pio 07.198: floppy_pio 07.198: handle_0e 07.198: floppy_pio 07.198: floppy_media_sense 0 ftype=4 07.198: floppy_drive_readid 0 rate=0 head=0 07.198: floppy_pio 07.513: handle_0e 07.513: floppy_media_sense finish 0 data_rate=0 fms=17 stype=4 07.514: floppy_pio 07.685: handle_0e 07.685: Booting from 0000:7c00 07.685: enter handle_13: 07.685: a=00000201 b=00000700 c=00000002 d=00000100 ds=0000 es=0000 ss=dd80 07.685: si=00007bd2 di=00000700 bp=00007c00 sp=0000fae8 cs=0000 ip=7d6e f=0002 07.684: disk_op d=0x000f4530 lba=19 buf=0x00000700 count=1 cmd=2 07.684: floppy_pio 07.850: handle_0e 07.850: enter handle_13: 07.850: a=00000201 b=00000700 c=00000010 d=00000100 ds=0000 es=0000 ss=dd80 07.850: si=00007bd2 di=00000002 bp=00007c00 sp=0000fae8 cs=0000 ip=7d6e f=0002 07.852: disk_op d=0x000f4530 lba=33 buf=0x00000700 count=1 cmd=2 07.852: floppy_pio 07.965: handle_0e 07.965: enter handle_13: 07.965: a=00000201 b=00000900 c=00000011 d=00000100 ds=0000 es=0000 ss=dd80 07.965: si=00007bd2 di=00000002 bp=00007c00 sp=0000fae8 cs=0000 ip=7d6e f=0006 07.965: disk_op d=0x000f4530 lba=34 buf=0x00000900 count=1 cmd=2 07.971: floppy_pio 08.133: handle_0e 08.133: enter handle_13: 08.133: a=00000201 b=00000b00 c=00000012 d=00000100 ds=0000 es=0000 ss=dd80 08.134: si=00007bd2 di=00000002 bp=00007c00 sp=0000fae8 cs=0000 ip=7d6e f=0006 08.136: disk_op d=0x000f4530 lba=35 buf=0x00000b00 count=1 cmd=2 08.136: floppy_pio 08.507: handle_0e 08.507: floppy error: 40 04 10 01 00 00 02 08.507: invalid basic_access:96: 08.507: a=00000200 b=00000b00 c=00000012 d=00000100 ds=0000 es=0000 ss=dd80 08.510: si=00007bd2 di=00000002 bp=00007c00 sp=0000fae8 cs=0000 ip=7d6e f=0006

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SMBIOS Type 4
by Bret Ketchum 06 Dec '13

06 Dec '13

Looking at the 1.7.3 source it appears that smbios_setup creates a type 4 entry for each core rather than one per package/socket as would be typical of a bare metal bios. Is this behavior by design? Thanks in advance.... Bret

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[PATCH] Separate out sec32init sections even when not doing code relocation.
by Kevin O'Connor 06 Dec '13

06 Dec '13

The current code does not boot on QEMU with 256K roms when code relocation is disabled, because QEMU only maps the last 128K of the rom to low memory. The seabios make_bios_writable() call copies the full rom to low memory. This patch separates out the init sections even if code relocations are disabled. This effectively ensures that make_bios_writable() code is in the last 128K of the rom. This also introduces a new build symbol (final_readonly_start) which stores the address of where the final runtime read-only memory begins. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- scripts/layoutrom.py | 53 +++++++++++++++++++++++++++++++++------------------- src/malloc.c | 5 ++--- 2 files changed, 36 insertions(+), 22 deletions(-) diff --git a/scripts/layoutrom.py b/scripts/layoutrom.py index 17330ae..24cd7a4 100755 --- a/scripts/layoutrom.py +++ b/scripts/layoutrom.py @@ -163,12 +163,14 @@ class LayoutInfo: sections32low = sec32low_start = sec32low_align = None sections32fseg = sec32fseg_start = sec32fseg_align = None zonefseg_start = zonefseg_end = None + final_readonly_start = None zonelow_base = final_sec32low_start = None exportsyms = varlowsyms = None # Determine final memory addresses for sections -def doLayout(sections, config): +def doLayout(sections, config, genreloc): li = LayoutInfo() + li.genreloc = genreloc # Determine 16bit positions li.sections16 = getSectionsCategory(sections, '16') textsections = getSectionsPrefix(li.sections16, '.text.') @@ -215,7 +217,23 @@ def doLayout(sections, config): li.sec32flat_start, li.sec32flat_align = setSectionsStart( textsections + rodatasections + datasections + bsssections , li.sec32fseg_start, 16) + + # Determine 32flat init positions + li.sections32init = getSectionsCategory(sections, '32init') + init32_textsections = getSectionsPrefix(li.sections32init, '.text.') + init32_rodatasections = getSectionsPrefix(li.sections32init, '.rodata') + init32_datasections = getSectionsPrefix(li.sections32init, '.data.') + init32_bsssections = getSectionsPrefix(li.sections32init, '.bss.') + + li.sec32init_start, li.sec32init_align = setSectionsStart( + init32_textsections + init32_rodatasections + + init32_datasections + init32_bsssections + , li.sec32flat_start, 16) + + # Determine location of ZoneFSeg memory. li.zonefseg_end = li.sec32flat_start + if not genreloc: + li.zonefseg_end = li.sec32init_start li.zonefseg_start = BUILD_BIOS_ADDR if li.zonefseg_start + BUILD_MIN_BIOSTABLE > li.zonefseg_end: # Not enough ZoneFSeg space - force a minimum space. @@ -224,23 +242,19 @@ def doLayout(sections, config): li.sec32flat_start, li.sec32flat_align = setSectionsStart( textsections + rodatasections + datasections + bsssections , li.zonefseg_start, 16) - - # Determine 32flat init positions - li.sections32init = getSectionsCategory(sections, '32init') - textsections = getSectionsPrefix(li.sections32init, '.text.') - rodatasections = getSectionsPrefix(li.sections32init, '.rodata') - datasections = getSectionsPrefix(li.sections32init, '.data.') - bsssections = getSectionsPrefix(li.sections32init, '.bss.') - - li.sec32init_start, li.sec32init_align = setSectionsStart( - textsections + rodatasections + datasections + bsssections - , li.sec32flat_start, 16) + li.sec32init_start, li.sec32init_align = setSectionsStart( + init32_textsections + init32_rodatasections + + init32_datasections + init32_bsssections + , li.sec32flat_start, 16) + li.final_readonly_start = min(BUILD_BIOS_ADDR, li.sec32flat_start) + if not genreloc: + li.final_readonly_start = min(BUILD_BIOS_ADDR, li.sec32init_start) # Determine "low memory" data positions li.sections32low = getSectionsCategory(sections, '32low') sec32low_end = li.sec32init_start if config.get('CONFIG_MALLOC_UPPERMEMORY'): - final_sec32low_end = min(BUILD_BIOS_ADDR, li.sec32flat_start) + final_sec32low_end = li.final_readonly_start zonelow_base = final_sec32low_end - 64*1024 li.zonelow_base = max(BUILD_ROM_START, alignpos(zonelow_base, 2*1024)) else: @@ -390,6 +404,7 @@ def writeLinkerScripts(li, out16, out32seg, out32flat): zonefseg_end = 0x%x ; zonelow_base = 0x%x ; final_varlow_start = 0x%x ; + final_readonly_start = 0x%x ; code32flat_start = 0x%x ; .text code32flat_start : { @@ -413,6 +428,7 @@ def writeLinkerScripts(li, out16, out32seg, out32flat): li.zonefseg_end, li.zonelow_base, li.final_sec32low_start, + li.final_readonly_start, sec32all_start, relocstr, outRelSections(li.sections32low, 'code32flat_start'), @@ -450,7 +466,7 @@ def markRuntime(section, sections, chain=[]): for reloc in section.relocs: markRuntime(reloc.symbol.section, sections, chain + [section.name]) -def findInit(sections, genreloc): +def findInit(sections): # Recursively find and mark all "runtime" sections. for section in sections: if ('.data.varlow.' in section.name or '.data.varfseg.' in section.name @@ -459,7 +475,7 @@ def findInit(sections, genreloc): for section in sections: if section.category is not None: continue - if section.fileid == '32flat' and genreloc: + if section.fileid == '32flat': section.category = '32init' else: section.category = section.fileid @@ -662,8 +678,7 @@ def main(): sections = gc(info16, info32seg, info32flat) # Separate 32bit flat into runtime and init parts - genreloc = '_reloc_abs_start' in info32flat[1] - findInit(sections, genreloc) + findInit(sections) # Note "low memory" and "fseg memory" parts for section in getSectionsPrefix(sections, '.data.varlow.'): @@ -672,8 +687,8 @@ def main(): section.category = '32fseg' # Determine the final memory locations of each kept section. - li = doLayout(sections, config) - li.genreloc = genreloc + genreloc = '_reloc_abs_start' in info32flat[1] + li = doLayout(sections, config, genreloc) # Exported symbols li.exportsyms = [symbol for symbol in info16[1].values() diff --git a/src/malloc.c b/src/malloc.c index 65104f6..6ef418a 100644 --- a/src/malloc.c +++ b/src/malloc.c @@ -332,9 +332,8 @@ rom_get_max(void) if (CONFIG_MALLOC_UPPERMEMORY) return ALIGN_DOWN((u32)RomBase->allocend - OPROM_HEADER_RESERVE , OPTION_ROM_ALIGN); - extern u8 code32init_end[]; - u32 end = (u32)code32init_end; - return end > BUILD_BIOS_ADDR ? BUILD_BIOS_ADDR : end; + extern u8 final_readonly_start[]; + return (u32)final_readonly_start; } // Return the end of the last deployed option rom. -- 1.8.3.1

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'make oldconfig' broken...
by David Woodhouse 06 Dec '13

06 Dec '13

Why does it keep forgetting my config and reverting to defaults, every time I touch src/Kconfig? [dwmw2@shinybook seabios]$ make oldconfig scripts/kconfig/conf --oldconfig /home/dwmw2/git/seabios/src/Kconfig # # configuration written to /home/dwmw2/git/seabios/.config # [dwmw2@shinybook seabios]$ grep CSM .config CONFIG_CSM=y [dwmw2@shinybook seabios]$ touch src/Kconfig [dwmw2@shinybook seabios]$ make oldconfig Build default config # # configuration written to /home/dwmw2/git/seabios/.config # scripts/kconfig/conf --oldconfig /home/dwmw2/git/seabios/src/Kconfig # # configuration written to /home/dwmw2/git/seabios/.config # [dwmw2@shinybook seabios]$ grep CSM .config # CONFIG_CSM is not set [dwmw2@shinybook seabios]$ -- dwmw2

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[PATCH 4/3] Broken attempt to add Oxford Semi PCI serial port support
by David Woodhouse 06 Dec '13

06 Dec '13

Based on http://git.chromium.org/gitweb/?p=chromiumos/third_party/seabios.git;a=comm… Doesn't work: ERROR: .data.varinit./home/dwmw2/git/seabios/src/hw/pci.c.93 is VARVERIFY32INIT but used from ['.text.runtime./home/dwmw2/git/seabios/src/resume.c.149', '.text.__callrom', '.text.serial_debug_preinit', '.text.pci_find_device'] make: *** [out/romlayout16.lds] Error 1 It might also need to re-discover its serial ports after PCI enumeration and BAR assignment. It may be set up at a fixed location for early debug, then moved when PCI is set up for real. Perhaps the Oxford code needs to run something once, early, which just discovers which PCI B/D/F to use, and then looks a lot more like the Quark code in find_mmio_serial(). Signed-off-by-but-do-not-use-as-is: David Woodhouse <David.Woodhouse(a)intel.com> --- src/Kconfig | 7 +++++++ src/hw/serialio.c | 15 ++++++++++++++- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 696ab46..a0ef46a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -490,6 +490,13 @@ menu "Debugging" default n help Use Quark UART1 (PCI device 0x14, function 5) for serial debug. + config DEBUG_SERIAL_OXFORD + bool "OXPCIe 952 serial port debugging" + depends on DEBUG_SERIAL + select DEBUG_SERIAL_MMIO + default n + help + Send debugging information to Oxford Semiconductors PCI serial port. config DEBUG_SERIAL_PORT depends on DEBUG_SERIAL && !DEBUG_SERIAL_MMIO hex "Serial port base address" diff --git a/src/hw/serialio.c b/src/hw/serialio.c index b2bc68f..3310c7f 100644 --- a/src/hw/serialio.c +++ b/src/hw/serialio.c @@ -53,7 +53,20 @@ find_mmio_serial(void) return 0; } } - + if (CONFIG_DEBUG_SERIAL_OXFORD) { + struct pci_device *oxpcie_dev; + // Detect Startech MPEX1S952 + oxpcie_dev = pci_find_device(0x1415, 0xc158); + if (!oxpcie_dev) // Startech PEX1S1PMINI + oxpcie_dev = pci_find_device(0x1415, 0xc11b); + if (oxpcie_dev) { + u32 bar = pci_config_readl(oxpcie_dev->bdf, PCI_BASE_ADDRESS_0); + if (!(bar & 0xf)) { + set_serial_addr(bar, 1); + return 0; + } + } + } return -1; } -- 1.8.3.1 -- David Woodhouse Open Source Technology Centre David.Woodhouse(a)intel.com Intel Corporation

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[PATCH 3/3] Initialise debug output in handle_csm()
by David Woodhouse 06 Dec '13

06 Dec '13

For a PCI serial port, we have to discover its location. Potentially on every entry, since UEFI may shift it at some point during the boot process from an early debug setup to a final location after real PCI enumeration. Signed-off-by: David Woodhouse <David.Woodhouse(a)intel.com> --- src/fw/csm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/fw/csm.c b/src/fw/csm.c index 4e4b688..39634cd 100644 --- a/src/fw/csm.c +++ b/src/fw/csm.c @@ -109,6 +109,8 @@ handle_csm_0001(struct bregs *regs) return; } + debug_preinit(); + dprintf(3, "Legacy16UpdateBbs table %04x:%04x\n", regs->es, regs->bx); csm_boot_table = MAKE_FLATPTR(regs->es, regs->bx); -- 1.8.3.1 -- David Woodhouse Open Source Technology Centre David.Woodhouse(a)intel.com Intel Corporation

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[PATCH 2/3] Add Intel Quark UART support
by David Woodhouse 06 Dec '13

06 Dec '13

This includes generic support for MMIO serial which can be used for other PCI (or non-PCI) serial ports too. Only outputs to the serial port in 32-bit mode, unless we're lucky enough that it's at an address below 1MiB. Signed-off-by: David Woodhouse <David.Woodhouse(a)intel.com> --- src/Kconfig | 15 ++++++++++++++- src/hw/serialio.c | 56 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 92c3102..696ab46 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -477,8 +477,21 @@ menu "Debugging" default n help Send debugging information to serial port. - config DEBUG_SERIAL_PORT + config DEBUG_SERIAL_MMIO depends on DEBUG_SERIAL + bool + default n + help + Send debugging information to PCI serial port. + config DEBUG_SERIAL_QUARK + bool "Intel Quark serial port debugging" + depends on DEBUG_SERIAL + select DEBUG_SERIAL_MMIO + default n + help + Use Quark UART1 (PCI device 0x14, function 5) for serial debug. + config DEBUG_SERIAL_PORT + depends on DEBUG_SERIAL && !DEBUG_SERIAL_MMIO hex "Serial port base address" default 0x3f8 help diff --git a/src/hw/serialio.c b/src/hw/serialio.c index 8ec36c2..b2bc68f 100644 --- a/src/hw/serialio.c +++ b/src/hw/serialio.c @@ -9,6 +9,9 @@ #include "output.h" // dprintf #include "serialio.h" // serial_debug_preinit #include "x86.h" // outb +#include "hw/pci_regs.h" // PCI_VENDOR_ID, PCI_BASE_ADDRESS_0 +#include "hw/pci.h" // pci_config_readl +#include "stacks.h" // call32 /**************************************************************** @@ -17,8 +20,42 @@ #define DEBUG_TIMEOUT 100000 +#if CONFIG_DEBUG_SERIAL_MMIO +static u32 serial_addr; +static u8 serial_stride; +#define serial_out(d, ofs) writeb((void *)(serial_addr + (ofs)*serial_stride), (d)) +#define serial_in(ofs) readb((void *)(serial_addr + (ofs)*serial_stride)) +// Debug output only in 32-bit mode, or when MMIO address < 1MiB +#define serial_valid() (serial_addr && (!MODE16 || serial_addr < 0x100000)) +#define set_serial_addr(adr, str) do { serial_addr = (adr); \ + serial_stride = (str); } while (0) +#else #define serial_out(d, reg) outb(d, CONFIG_DEBUG_SERIAL_PORT+(reg)) #define serial_in(reg) inb(CONFIG_DEBUG_SERIAL_PORT+(reg)) +#define serial_valid() (1) +#define set_serial_addr(adr, str) do { ; } while (0) +#endif + +static int +find_mmio_serial(void) +{ + if (CONFIG_DEBUG_SERIAL_QUARK) { + // debug port is bus 0, device 0x14, function 5. + u16 uart_bdf = pci_to_bdf(0, 0x14, 5); + + // If it isn't a Quark UART... + if (pci_config_readl(uart_bdf, PCI_VENDOR_ID) != 0x09368086) + return -1; + + u32 bar0 = pci_config_readl(uart_bdf, PCI_BASE_ADDRESS_0); + if (!(bar0 & 0xf)) { + set_serial_addr(bar0, 4); + return 0; + } + } + + return -1; +} // Setup the debug serial port for output. void @@ -26,6 +63,21 @@ serial_debug_preinit(void) { if (!CONFIG_DEBUG_SERIAL) return; + + if (CONFIG_DEBUG_SERIAL_MMIO) { + // Need to discover serial port MMIO address + if (MODE16) { + // Needs to be done in 32-bit mode. + extern void _cfunc32flat_serial_debug_preinit(void); + call32(_cfunc32flat_serial_debug_preinit, 0, -1); + return; + } + + // Find the PCI device or whatever provides the serial port + if (find_mmio_serial()) + return; + } + // setup for serial logging: 8N1 u8 oldparam, newparam = 0x03; oldparam = serial_in(SEROFF_LCR); @@ -46,6 +98,8 @@ serial_debug(char c) { if (!CONFIG_DEBUG_SERIAL) return; + if (!serial_valid()) + return; int timeout = DEBUG_TIMEOUT; while ((serial_in(SEROFF_LSR) & 0x20) != 0x20) if (!timeout--) @@ -68,6 +122,8 @@ serial_debug_flush(void) { if (!CONFIG_DEBUG_SERIAL) return; + if (!serial_valid()) + return; int timeout = DEBUG_TIMEOUT; while ((serial_in(SEROFF_LSR) & 0x60) != 0x60) if (!timeout--) -- 1.8.3.1 -- David Woodhouse Open Source Technology Centre David.Woodhouse(a)intel.com Intel Corporation

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