SeaBIOS

seabios@seabios.org

4 participants
3801 discussions

[ANNOUNCE] SeaBIOS 1.7.5
by Kevin O'Connor 28 May '14

28 May '14

The 1.7.5 version of SeaBIOS has now been released. For more information on the release, please see: http://seabios.org/Releases New in this release: * Support for obtaining SMBIOS tables directly from QEMU. * XHCI USB controller fixes for real hardware (now tested on several boards) * SeaVGABIOS improvements * New driver for "coreboot native vga" support * Improved detection of older x86emu versions with incorrect emulation. * Several bug fixes and code cleanups For information on obtaining SeaBIOS, please see: http://seabios.org/Download

1 0

Re: [SeaBIOS] [PATCH] python3 fixes for vgabios and csm builds.
by Kevin O'Connor 27 May '14

27 May '14

On Thu, May 22, 2014 at 05:01:40PM -0400, Kevin O'Connor wrote: > Avoid using chr() as this produces unicode strings on python3. Make > sure to only use ord() on slices as the python3 bytearray type returns > an integer on a non-slice array access. FYI, I have pushed this change. -Kevin

1 0

[PATCH] python3 fixes for vgabios and csm builds.
by Kevin O'Connor 22 May '14

22 May '14

Avoid using chr() as this produces unicode strings on python3. Make sure to only use ord() on slices as the python3 bytearray type returns an integer on a non-slice array access. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- scripts/buildrom.py | 18 +++++++++++------- scripts/checkrom.py | 20 ++++++++------------ 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/scripts/buildrom.py b/scripts/buildrom.py index 8ff60e2..0499049 100755 --- a/scripts/buildrom.py +++ b/scripts/buildrom.py @@ -5,7 +5,7 @@ # # This file may be distributed under the terms of the GNU GPLv3 license. -import sys +import sys, struct from python23compat import as_bytes @@ -14,8 +14,11 @@ def alignpos(pos, alignbytes): return (pos + mask) & ~mask def checksum(data): - ords = map(ord, data) - return sum(ords) + if (sys.version_info > (3, 0)): + cksum = sum(data) + else: + cksum = sum(map(ord, data)) + return struct.pack('<B', (0x100 - cksum) & 0xff) def main(): inname = sys.argv[1] @@ -34,14 +37,15 @@ def main(): # Check if a pci header is present pcidata = ord(data[24:25]) + (ord(data[25:26]) << 8) if pcidata != 0: - data = data[:pcidata + 16] + chr(int(count/512)) + chr(0) + data[pcidata + 18:] + blocks = struct.pack('<H', int(count/512)) + data = data[:pcidata + 16] + blocks + data[pcidata + 18:] # Fill in size field; clear checksum field - data = data[:2] + chr(int(count/512)) + data[3:6] + as_bytes("\0") + data[7:] + blocks = struct.pack('<B', int(count/512)) + data = data[:2] + blocks + data[3:6] + as_bytes("\0") + data[7:] # Checksum rom - newsum = (256 - checksum(data)) & 0xff - data = data[:6] + chr(newsum) + data[7:] + data = data[:6] + checksum(data) + data[7:] # Write new rom f = open(outname, 'wb') diff --git a/scripts/checkrom.py b/scripts/checkrom.py index 83d4671..377277d 100755 --- a/scripts/checkrom.py +++ b/scripts/checkrom.py @@ -5,8 +5,8 @@ # # This file may be distributed under the terms of the GNU GPLv3 license. -import sys -import layoutrom +import sys, struct +import layoutrom, buildrom from python23compat import as_bytes @@ -14,12 +14,8 @@ def subst(data, offset, new): return data[:offset] + new + data[offset + len(new):] def checksum(data, start, size, csum): - sumbyte = 0 - while size: - sumbyte = sumbyte + ord(data[start + size - 1]) - size = size - 1 - sumbyte = (0x100 - sumbyte) & 0xff - return subst(data, start+csum, chr(sumbyte)) + sumbyte = buildrom.checksum(data[start:start+size]) + return subst(data, start+csum, sumbyte) def main(): # Get args @@ -76,11 +72,11 @@ def main(): tableofs = symbols['csm_compat_table'].offset - symbols['code32flat_start'].offset entry_addr = symbols['entry_csm'].offset - layoutrom.BUILD_BIOS_ADDR - byte1 = chr(entry_addr & 0xff) - byte2 = chr(entry_addr >> 8) - rawdata = subst(rawdata, tableofs+ENTRY_FIELD_OFS, byte1+byte2) + entry_addr = struct.pack('<H', entry_addr) + rawdata = subst(rawdata, tableofs+ENTRY_FIELD_OFS, entry_addr) - tablesize = ord(rawdata[tableofs+SIZE_FIELD_OFS]) + tsfield = tableofs+SIZE_FIELD_OFS + tablesize = ord(rawdata[tsfield:tsfield+1]) rawdata = checksum(rawdata, tableofs, tablesize, CSUM_FIELD_OFS) # Print statistics -- 1.9.0

1 0

[PATCH 0/3] use full io address space on q35
by Gerd Hoffmann 20 May '14

20 May '14

Hi, First patch swapped for v2 of this series, using the patch from Paolo now, which removes the pmbase dependency in the smm code altogether. Second patch (unmodified) makes acpi pmbase a variable and figure where to place the registers at runtime. No functional change. With these preparations in place the third patch (unmodified too) moves the acpi pm registers below 0x1000 for new enougth qemu (2.0+). The whole 0x1000 -> 0xffff range is free then on q35. cheers, Gerd Gerd Hoffmann (2): acpi: remove PORT_ACPI_PM_BASE constant Allow using full io region on q35. Paolo Bonzini (1): smm: remove code to handle ACPI disable/enable src/fw/acpi.c | 14 +++++++------- src/fw/biostables.c | 1 + src/fw/paravirt.c | 5 +++++ src/fw/paravirt.h | 2 -- src/fw/pciinit.c | 32 +++++++++++++++++--------------- src/fw/smm.c | 29 ++--------------------------- src/util.h | 1 + 7 files changed, 33 insertions(+), 51 deletions(-) -- 1.8.3.1

3 6

[PATCH 0/7] vgabios improvements
by Kevin O'Connor 19 May '14

19 May '14

This patch series refactors the vgabios graphics mode framebuffer manipulation code. It then adds in support for manipulating "direct" framebuffers that modern vga modes use. This series (along with the followup patches for coreboot native vga vgabios) is also available at: https://github.com/KevinOConnor/seabios/tree/testing -Kevin Kevin O'Connor (7): vgabios: Add option to control use of standard VGA IO ports. vgabios: Split vgafb_scroll() into separate move and clear functions. vgabios: Rewrite vgafb.c graphics operations to set of 4 standard operators. vgabios: Introduce text_address(). vgabios: Add support for manipulating framebuffers in high memory. Set the color attribute when calling vgabios print character. vgabios: PMM scan was incorrectly depending on a zero %ds segment. src/output.c | 1 + vgasrc/Kconfig | 8 + vgasrc/vgabios.c | 119 ++++++--- vgasrc/vgabios.h | 34 ++- vgasrc/vgafb.c | 762 +++++++++++++++++++++++++++++-------------------------- vgasrc/vgainit.c | 15 +- 6 files changed, 536 insertions(+), 403 deletions(-) -- 1.9.0

5 37

[PATCH v2 0/3] use full io address space on q35
by Gerd Hoffmann 15 May '14

15 May '14

Hi, Digged out an old patch from the mailing list, to make smm use acpi_pm1a_cnt. This allows to make the acpi pmbase a variable and figure where to place the registers at runtime. With these preparations in place we can go move acpi pm registers below 0x1000 for new enougth qemu (2.0+). The whole 0x1000 -> 0xffff range is free then on q35. cheers, Gerd Gerd Hoffmann (3): smm: use acpi_pm1a_cnt acpi: remove PORT_ACPI_PM_BASE constant Allow using full io region on q35. src/fw/acpi.c | 14 +++++++------- src/fw/biostables.c | 3 ++- src/fw/paravirt.c | 5 +++++ src/fw/paravirt.h | 2 -- src/fw/pciinit.c | 32 +++++++++++++++++--------------- src/fw/smm.c | 8 ++++---- src/util.h | 3 ++- 7 files changed, 37 insertions(+), 30 deletions(-) -- 1.8.3.1

3 7

Question about the relationship between bios.bin and vgabios.bin
by Jaeyong Yoo 14 May '14

14 May '14

Hello Seabios! I started the thread from qemu-list and Laszlo suggested me to post the question here. In Seabios, the call-path of calling vgarom entry point is the following: handle_post() [src/post.c] make_bios_writable() [src/fw/shadow.c] make_bios_writable_intel() __make_bios_writable_intel() -- shadows vgabios in C segment too dopost() [src/post.c] maininit() vgarom_setup() [src/optionroms.c] init_pcirom() init_optionrom() callrom() __callrom() _rom_header_entry [vgasrc/vgaentry.S] vga_post() [vgasrc/vgainit.c] For me, it looks like seabios (bios.bin) calls a function, vga_post, that is supposed be in vgabios.bin. It makes me thinking that vgabios.bin is somehow embedded in bios.bin. But, in my case I use both bios.bin and vgabios.bin to booting up my guest OS (I'm using qemu). Apparently, I'm not clearly understanding the difference between vgabios inside bios.bin and vgabios-stdvga.bin. Could you tell me the difference? And, I'm trying to debug a vgabios.bin by examining with qemu+gdb. Especially, I'm trying to set the break-point to the entry point of vgabios.bin and I'm not quite sure how to do this since I don't know the address where vgabios.bin is loaded. I would appreciate if you give me some hint about this. Best regards, Jaeyong

3 2

[RFC PATCH] SMBIOS: Turn on VM flag on default type 0 structure
by Gabriel L. Somlo 13 May '14

13 May '14

Since commit d85c22e44ee4e24f2be19d579ea8fa0066a85fbb, when pulling aggregate tables from fw_cfg, we generate a default type 0 (bios info) structure if one isn't already provided. This patch enables the "virtual machine" bit within the bios_characteristics_extension_bytes field of the default type 0 structure. Signed-off-by: Gabriel Somlo <somlo(a)cmu.edu> --- What do you all think, does it make sense to flip on the "virtual machine" bit when generating a default Bios Info (type 0) table to go along with everything else we received via fw_cfg ? If yes, please apply :) Thanks, Gabriel src/fw/biostables.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/fw/biostables.c b/src/fw/biostables.c index 17bee8e..64f3157 100644 --- a/src/fw/biostables.c +++ b/src/fw/biostables.c @@ -350,9 +350,10 @@ smbios_new_type_0(void *start, memset(p->bios_characteristics, 0, 8); p->bios_characteristics[0] = 0x08; - /* Enable targeted content distribution (needed for SVVP) */ + /* Enable targeted content distribution (needed for SVVP); + * Also enable "virtual machine" bit: */ p->bios_characteristics_extension_bytes[0] = 0; - p->bios_characteristics_extension_bytes[1] = 4; + p->bios_characteristics_extension_bytes[1] = 0x14; /* TCG/SVVP | VM */ p->system_bios_major_release = 0; p->system_bios_minor_release = 0; -- 1.9.0

1 0

[PATCH] vgabios: Add debug message if x86emu leal check triggers.
by Kevin O'Connor 13 May '14

13 May '14

Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- vgasrc/vgaentry.S | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/vgasrc/vgaentry.S b/vgasrc/vgaentry.S index 6e31c4e..11197f1 100644 --- a/vgasrc/vgaentry.S +++ b/vgasrc/vgaentry.S @@ -47,7 +47,17 @@ _rom_header_signature: // Force a fault if found to be running on broken x86emu versions. DECLFUNC x86emu_fault +msg: .ascii "SeaVGABIOS: x86emu leal trap!\n" x86emu_fault: +#if CONFIG_DEBUG_IO + movw %cs:DebugOutputPort, %dx + movw $msg, %si +1: movb %cs:(%si), %al + outb %al, (%dx) + incw %si + cmpw $x86emu_fault, %si + jl 1b +#endif 1: hlt jmp 1b -- 1.9.0

1 0

[RFC] SeaBIOS v2.0 and 32bit drivers
by Kevin O'Connor 13 May '14

13 May '14

I've been considering a possible architectural change to SeaBIOS. Currently, SeaBIOS contains a mix of 16bit code and 32bit code. All of the initialization and bootup code is done in regular 32bit mode, but runtime code (the callbacks the OS uses) is generally run in 16bit mode. I have been thinking about possibly changing this so that hardware driver code runs exclusively in 32bit mode. Specifically, this would involve running the disk controller code, the keyboard/mouse controller code, and all hardware interrupt handlers exclusively in 32bit mode. To support this, some BIOS calls would require SeaBIOS to transition from 16bit mode to 32bit mode in order to satisfy the request. This trampolining to 32bit mode at runtime is already done for the AHCI driver, the XHCI driver, and the pvscsi driver - as these devices can not function with only a 16bit driver. Even with this proposed change, SeaBIOS would still continue to have 16bit code, though the remaining 16bit code would be almost exclusively for interface support and it would be noticeably smaller. In initial tests, the final 16bit code size drops from ~35K to ~16K. The main benefit of this change is that it makes it easier to develop and enhance the SeaBIOS hardware driver code, it makes understanding the code simpler, and reduces the overall size of the SeaBIOS binary. The biggest downside to this change would be problems running old DOS era programs that attempt to run the BIOS in vm86 mode. Specifically, the dos emm386 program is known to prevent 32 bit trampolines in SeaBIOS from working. (There's been a bit of experience with AHCI drivers running in 32bit mode (and now XHCI) so we have good confidence that modern OSes wont present a problem.) To continue to support these old DOS era programs I'm proposing we implement an SMI to help trampoline to 32bit mode. This can be done within SeaBIOS for QEMU TCG, but it would require work on kvm, coreboot, and ovmf to support it. (If we go down this path and these projects aren't extended to help trampoline to 32bit mode, then these projects would no longer be able to run these old DOS era programs with SeaBIOS.) For testing purposes, I have put together a series of patches to run the SeaBIOS drivers in 32bit mode and to implement the QEMU TCG SMI helper. The code is in a very rough state, but it demonstrates the idea. It's available at: https://github.com/KevinOConnor/seabios/tree/testing-32bit-drivers Unfortunately, the QEMU TCG SMI doesn't seem to help in vm86 mode, but I believe it is due to the QEMU code not handling CPL changes properly in SMM mode. I still need to confirm this though. In closing, this email is to start discussion on the proposal. This would not impact the next release of SeaBIOS. Comments? -Kevin

2 3

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

SeaBIOS