SeaBIOS

seabios@seabios.org

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3801 discussions

[PATCH] Add option to only execute CBFS option ROMs
by Timothy Pearson 12 Feb '15

12 Feb '15

All, This is my first time submitting a patch to SeaBIOS for review/inclusion; I assume this list is the correct initial contact? I have run into several situations where it is neccessary to execute only the relevant option ROMs contained in CBFS while ignoring any option ROM binary code present on PCI/PCIe devices; e.g. when the option ROM provided by the manufacturer is buggy but a FOSS replacement is available that works properly. This patch adds an option to only execute option ROMs contained in CBFS. Tested on ASUS KFSN4-DRE with iPXE ROMs built in to CBFS; with this option set the on-board network ROMs were ignored while the iPXE ROMs executed normally. -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com

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Re: [SeaBIOS] [PATCH] pci: enable SERR# for error forwording in bridge control register
by Chen Fan 10 Feb '15

10 Feb '15

On 02/02/2015 10:44 PM, Bjorn Helgaas wrote: > On Sun, Feb 1, 2015 at 10:08 PM, Nishank Trivedi > <nishank.trivedi(a)netapp.com> wrote: >> On 2/1/15 6:13 PM, Chen Fan wrote: >>> >>> On 02/01/2015 07:01 AM, Kevin O'Connor wrote: >>>> On Wed, Jan 28, 2015 at 04:05:13PM +0800, Chen Fan wrote: >>>>> For PCIe device support AER(Advanced Error Reporting), from the >>>>> pcie spec 3.0 chapter 6.2.5, ERR_COR, ERR_NONFATAL, and ERR_FATAL >>>>> can be forwarded from the secondary interface to the primary interface, >>>>> only require the SERR# Enable bit in the Bridge Control register is set. >>>>> >>>>> and at the kernel side, we found only _HPP() method can enable >>>>> SERR#, So here we want to turn on this bit. >>>>> >>>>> Signed-off-by: Chen Fan <chen.fan.fnst(a)cn.fujitsu.com> >>>>> --- >>>>> src/fw/pciinit.c | 4 ++++ >>>>> 1 file changed, 4 insertions(+) >>>>> >>>>> diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c >>>>> index 34279a4..28ed1af 100644 >>>>> --- a/src/fw/pciinit.c >>>>> +++ b/src/fw/pciinit.c >>>>> @@ -310,6 +310,10 @@ static void pci_bios_init_device(struct >>>>> pci_device *pci) >>>>> /* enable memory mappings */ >>>>> pci_config_maskw(bdf, PCI_COMMAND, 0, >>>>> PCI_COMMAND_IO | PCI_COMMAND_MEMORY | >>>>> PCI_COMMAND_SERR); >>>>> + /* enable SERR# for forwording */ >>>>> + if (pci->header_type & PCI_HEADER_TYPE_BRIDGE) >>>>> + pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0, >>>>> + PCI_BRIDGE_CTL_SERR); >>>>> } >>>> Thanks for submitting your patch. >>>> >>>> I'm not that familiar with all the details of the PCI specification. >>>> Can you elaborate on what doesn't work if this patch is not present, >>>> or what does work or work better when present? Is this associated >>>> with a QEMU feature or change? >>> With this patch, the aer error inject feature for pcie device in QEMU >>> will work . the hmp command line is called pcie_aer_inject_error. >>> a endpoint device propagates error messages to guest that need the >>> parent bridge type devices enable the SERR# in bridge control reigster >>> from pcie spec 3.0 chapter 6.2.5, and currently, the register bit is >>> not turned on, so the command pcie_aer_inject_error is not work. >>> and if the patch is ok, could you check in this patch? >> >> Patch looks fine to me. >> Certain PCI switches, like PEX87xx, provide mechanism to explicitly inject >> errors (unlike aer_inject tool where just interrupt is raised). However, if >> SERR bit is not enabled in the bridges, error is not percolated to root >> port, probably because kernel expects BIOS to enable this bit. CC'ing Bjorn >> who can correct if this incorrect understanding. > I think your understanding of PCI_BRIDGE_CTL_SERR is correct. Linux > doesn't really have formal expectations about how platforms should set > PCI_BRIDGE_CTL_SERR. It's possible that Linux should be more > proactive about enabling it. I think it's just an area that nobody > has paid much attention to. Hi Kevin, How do you think of this patch? Thanks, Chen > Bjorn > . >

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[PATCH] build: remove hardcoded timestamp
by Olaf Hering 09 Feb '15

09 Feb '15

The timestamp and hostname carries no value for the default build. If its really required in special environment, or if someone is emotionally attached to such strings, it is is handled by existing logic a few lines above: provide your own .version file Once this patch is applied it is possible to get reproducible builds of Xens hvmloader. Signed-off-by: Olaf Hering <olaf(a)aepfle.de> --- scripts/buildversion.sh | 1 - 1 file changed, 1 deletion(-) diff --git a/scripts/buildversion.sh b/scripts/buildversion.sh index e5ce96c..338b7f0 100755 --- a/scripts/buildversion.sh +++ b/scripts/buildversion.sh @@ -11,7 +11,6 @@ elif [ -f .version ]; then else VERSION="?" fi -VERSION="${VERSION}-`date +"%Y%m%d_%H%M%S"`-`hostname`" echo "Version: ${VERSION}" # Build header file

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[PATCH] vgabios: Use EBDA (instead of PMM) for extra stack
by Kevin O'Connor 03 Feb '15

03 Feb '15

Instead of allocating the SeaVGABIOS extra stack via a PCIv3 style PMM call, use the EBDA to store the stack. The stack is placed at the end of the first 1KiB of the EBDA. Normally this EBDA space is reserved for the main BIOS, but SeaBIOS doesn't use the space. This works around an issue with 16bit code running on Windows Vista (and likely later versions of Windows). The Windows 16bit emulator can not handle a stack in the e-segment. Using the EBDA, and thus relocating the stack to the 9-segment, works around the issue. Reported-by: Richard Laager <rlaager(a)wiktel.com> Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- There were several possible ways to resolve the main issue. I'm leaning torwards the "use the EBDA for the stack" approach, and the patch below implements that. -Kevin --- vgasrc/Kconfig | 18 ++++++++---------- vgasrc/vgaentry.S | 20 +++++++++++++------- vgasrc/vgainit.c | 56 +++++++------------------------------------------------ 3 files changed, 28 insertions(+), 66 deletions(-) diff --git a/vgasrc/Kconfig b/vgasrc/Kconfig index 400e8da..bc1ea48 100644 --- a/vgasrc/Kconfig +++ b/vgasrc/Kconfig @@ -90,19 +90,17 @@ menu "VGA ROM" Support emulating text mode features when only a framebuffer is available. - config VGA_ALLOCATE_EXTRA_STACK + config VGA_EXTRA_STACK depends on BUILD_VGABIOS - bool "Allocate an internal stack for 16bit interrupt entry point" + bool "Use an extra stack located in the EBDA" default y help - Attempt to allocate (via BIOS PMM call) an internal stack - for the legacy 16bit 0x10 interrupt entry point. This - reduces the amount of space on the caller's stack that - SeaVGABIOS uses. - - config VGA_EXTRA_STACK_SIZE - int - default 512 + Use space at the end of the first 1KiB of the EBDA for an + internal stack when the legacy 16bit 0x10 interrupt entry + point is called. This reduces the amount of space on the + caller's stack that SeaVGABIOS uses. Normally the first + 1KiB of the EBDA is reserved for the main BIOS, but + SeaBIOS does not use this space. config VGA_VBE depends on BUILD_VGABIOS diff --git a/vgasrc/vgaentry.S b/vgasrc/vgaentry.S index f9cf656..2e4b200 100644 --- a/vgasrc/vgaentry.S +++ b/vgasrc/vgaentry.S @@ -104,15 +104,19 @@ entry_10: ENTRY_ARG_VGA handle_10 iretw +#define BDA_ebda_seg 0x0e + // Entry point using extra stack DECLFUNC entry_10_extrastack entry_10_extrastack: cli cld - pushw %ds // Set %ds:%eax to space on ExtraStack + pushw %ds // Set %ds:%eax to end of first 1K of EBDA pushl %eax - movw %cs:ExtraStackSeg, %ds - movl $(CONFIG_VGA_EXTRA_STACK_SIZE-PUSHBREGS_size-16), %eax + movw $SEG_BDA, %ax + movw %ax, %ds + movw BDA_ebda_seg, %ds + movl $(1024-PUSHBREGS_size-16), %eax SAVEBREGS_POP_DSEAX // Save registers on extra stack movl %esp, PUSHBREGS_size+8(%eax) movw %ss, PUSHBREGS_size+12(%eax) @@ -145,11 +149,13 @@ entry_timer_hook: entry_timer_hook_extrastack: cli cld - pushw %ds // Set %ds:%eax to space on ExtraStack + pushw %ds // Set %ds:%eax to end of first 1K of EBDA pushl %eax - movw %cs:ExtraStackSeg, %ds - movl $(CONFIG_VGA_EXTRA_STACK_SIZE-PUSHBREGS_size-8), %eax - SAVEBREGS_POP_DSEAX + movw $SEG_BDA, %ax + movw %ax, %ds + movw BDA_ebda_seg, %ds + movl $(1024-PUSHBREGS_size-8), %eax + SAVEBREGS_POP_DSEAX // Save registers on extra stack movl %esp, PUSHBREGS_size(%eax) movw %ss, PUSHBREGS_size+4(%eax) diff --git a/vgasrc/vgainit.c b/vgasrc/vgainit.c index 8d12261..78d5556 100644 --- a/vgasrc/vgainit.c +++ b/vgasrc/vgainit.c @@ -43,51 +43,6 @@ struct pci_data rom_pci_data VAR16 VISIBLE16 = { /**************************************************************** - * PMM call and extra stack setup - ****************************************************************/ - -u16 ExtraStackSeg VAR16 VISIBLE16; - -static void -allocate_extra_stack(void) -{ - if (!CONFIG_VGA_ALLOCATE_EXTRA_STACK) - return; - u32 pmmscan; - for (pmmscan=0; pmmscan < BUILD_BIOS_SIZE; pmmscan+=16) { - struct pmmheader *pmm = (void*)pmmscan; - if (GET_FARVAR(SEG_BIOS, pmm->signature) != PMM_SIGNATURE) - continue; - if (checksum_far(SEG_BIOS, pmm, GET_FARVAR(SEG_BIOS, pmm->length))) - continue; - struct segoff_s entry = GET_FARVAR(SEG_BIOS, pmm->entry); - dprintf(1, "Attempting to allocate VGA stack via pmm call to %04x:%04x\n" - , entry.seg, entry.offset); - u16 res1, res2; - asm volatile( - "pushl %0\n" - "pushw $(8|1)\n" // Permanent low memory request - "pushl $0xffffffff\n" // Anonymous handle - "pushl $" __stringify(CONFIG_VGA_EXTRA_STACK_SIZE/16) "\n" - "pushw $0x00\n" // PMM allocation request - "lcallw *12(%%esp)\n" - "addl $16, %%esp\n" - "cli\n" - "cld\n" - : "+r" (entry.segoff), "=a" (res1), "=d" (res2) : : "cc", "memory"); - u32 res = res1 | (res2 << 16); - if (!res || res == PMM_FUNCTION_NOT_SUPPORTED) - return; - dprintf(1, "VGA stack allocated at %x\n", res); - SET_VGA(ExtraStackSeg, res >> 4); - extern void entry_10_extrastack(void); - SET_IVT(0x10, SEGOFF(get_global_seg(), (u32)entry_10_extrastack)); - return; - } -} - - -/**************************************************************** * Timer hook ****************************************************************/ @@ -110,7 +65,7 @@ hook_timer_irq(void) extern void entry_timer_hook_extrastack(void); struct segoff_s oldirq = GET_IVT(0x08); struct segoff_s newirq = SEGOFF(get_global_seg(), (u32)entry_timer_hook); - if (CONFIG_VGA_ALLOCATE_EXTRA_STACK && GET_GLOBAL(ExtraStackSeg)) + if (CONFIG_VGA_EXTRA_STACK) newirq = SEGOFF(get_global_seg(), (u32)entry_timer_hook_extrastack); dprintf(1, "Hooking hardware timer irq (old=%x new=%x)\n" , oldirq.segoff, newirq.segoff); @@ -177,10 +132,13 @@ vga_post(struct bregs *regs) if (CONFIG_VGA_STDVGA_PORTS) stdvga_build_video_param(); + // Setup int10 entry point extern void entry_10(void); - SET_IVT(0x10, SEGOFF(get_global_seg(), (u32)entry_10)); - - allocate_extra_stack(); + extern void entry_10_extrastack(void); + struct segoff_s newirq = SEGOFF(get_global_seg(), (u32)entry_10); + if (CONFIG_VGA_EXTRA_STACK) + newirq = SEGOFF(get_global_seg(), (u32)entry_10_extrastack); + SET_IVT(0x10, newirq); hook_timer_irq(); -- 1.9.3

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Next release
by Kevin O'Connor 01 Feb '15

01 Feb '15

I was originally targeting end of January for the next release, but I'm now planning on pushing that back to mid February. Lets target February 16th as the release date. If you know of any regressions or defects in SeaBIOS, please raise them now. Please consider the code in a "feature freeze" until the next release. Thanks, -Kevin

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SeaBIOS hang with VGA option ROM
by Timothy Pearson 27 Jan '15

27 Jan '15

All, I have a board here that uses an XGI Volari Z9s integrated graphics device. The board boots under coreboot and loads Linux, but if I add the appropriate VGA option ROM (extracted from the vendor BIOS) SeaBIOS hangs: SeaBIOS (version rel-1.7.5-150-g301dd09-20150126_124858-apollo) Found mainboard ASUS KFSN4-DRE Relocating init from 0x000e6fe0 to 0x3ff95800 (size 42816) Found CBFS header at 0xfffffc80 CPU Mhz=2311 Found 26 PCI devices (max PCI bus is 05) Copying MPTABLE from 0x3ffe0400/3ffe0410 to 0x000f1550 Copying ACPI RSDP from 0x3ffe1400 to 0x000f1520 Copying SMBIOS entry point from 0x3ffec800 to 0x000f1500 Using pmtimer, ioport 0x2008 Scan for VGA option rom Running option rom at c000:0003 The Volari graphics initialise and work properly once Linux has booted and loaded the appropriate device drivers. For now I have been using SGABIOS for VGA emulation, however I would like to see the native VGA work on boot. Any ideas? Thanks! -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com

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Re: [SeaBIOS] SeaBIOS hang with VGA option ROM
by Kevin O'Connor 26 Jan '15

26 Jan '15

On Mon, Jan 26, 2015 at 02:07:41PM -0600, Timothy Pearson wrote: > On 01/26/2015 01:51 PM, Kevin O'Connor wrote: > >It will likely be hard to figure out why your vendor vgabios is > >hanging. It's possible something in seabios is causing it to get > >confused, but it's also possible something during the coreboot > >initialization is confusing it. > > > >I suggest increasing the SeaBIOS debugging level to 8 and see if it > >reveals any further information. > > Debug level 8: > > SeaBIOS (version rel-1.7.5-150-g301dd09-20150126_140432-apollo) [...] > Scan for VGA option rom > Attempting to init PCI bdf 01:04.0 (vd 18ca:0020) > Copying data 32768@0xfff36278 to 32768@0x000c0000 > Checking rom 0x000c0000 (sig aa55 size 64) > Running option rom at c000:0003 So, no additional information. You could try increasing the debug level to 99 just to see if irqs are still on (and if so, to see where the pc is when irqs are hitting). However, unless you have access to the vendor vgabios code it's very difficult to guess what's confusing it. BTW, did you make sure all of the following are disabled in coreboot: CONFIG_VGA_ROM_RUN, CONFIG_PCI_ROM_RUN, CONFIG_ON_DEVICE_ROM_RUN If coreboot supports native vga init for your board, you could try using seavgabios and skip the vendor vgabios. Another approach would be to see if you can get get the vga bios to run in some emulator (such as xorg's x86emu, coreboot's emulator, qemu, etc) and then try to figure out what's different. Please keep the mailing list on the CC. -Kevin

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[Qemu-devel] [PATCH RFC 00/17] implement multiple primary busses for pc machines
by Marcel Apfelbaum 23 Jan '15

23 Jan '15

This series depends on: - [SeaBIOS] [PATCH 0/2] fw/pci: better support for multiple host bridges (https://www.mail-archive.com/seabios@seabios.org/msg07103.html) - Not yet final, comments need to be adressed - [Qemu-devel] [PATCH v2 00/47] ACPI refactoring: replace template patching with C ASL API (http://lists.gnu.org/archive/html/qemu-devel/2015-01/msg02895.html) Reasoning: We need multiple primary busess for a few reasons, the most important one is to be able to associate a pass-trough device with a guest NUMA node. The OS-es are able to associate a NUMA node only to a primary bus, not to a specific PCI device or a pci-2-pci bridge. PC machines support multiple NUMA nodes for CPUs and memory, however the IO was not yet supported. Series status: The series is fully functional but tested only with Windows2012 server/Fedora 19 and e1000/virtio-net-pci. You are more than welcome to try using: -device pxb-device,id=bridge1,bus_nr=4 -device e1000,bus=bridge1,addr=0x1 -bios <patched with the above series> patch 1 adds the necessary acpi constructs based on Igor's series patch 2-5 implements acpi code needed to expose the pxb's primary bus to guests patch 6 separates the pci_bus code into a designated file patch 7-11 handles the implicit assumptions in code that only one primary bus can exist patch 12 handles the actual implementation of the PXB devices patch 13-14 enables the device patch 15 implements PXB map_irq function, (can be squashed into the actual PXB) patch 16-17 hacks that need to be addressed before removing the "RFC" status. Todo: - Solve the little hacks (patches 16/17) - Resend the SeaBios series after the comments are addressed - More testing with other OS-es and other pci devices - Implement the association of a root bus with a NUMA node (acpi proximity) - Think of migration implications and missing code (Ideas?) Any comments will be welcomed and appreciated. I will not be able to respond next week, but after that I'll answer to all questions/comments. Thanks, Marcel Marcel Apfelbaum (17): acpi: added needed acpi constructs hw/acpi: add support for multiple root busses hw/apci: add _PRT method for extra root busses hw/acpi: add _CRS method for extra root busses hw/acpi: remove from root bus 0 the crs resources used by other busses. hw/pci: move pci bus related code to separate files hw/pci: made pci_bus_is_root a PCIBusClass method hw/pci: made pci_bus_num a PCIBusClass method hw/pci: introduce TYPE_PCI_MAIN_HOST_BRIDGE interface hw/pci: removed 'rootbus nr is 0' assumption from qmp_pci_query hw/pci: implement iteration over multiple host bridges hw/pci: introduce PCI Expander Bridge (PXB) hw/pci: inform bios if the system has more than one pci bridge hw/pci: piix - suport multiple host bridges hw/pxb: add map_irq func hw/pci-bridge: hack - disable shpc bar (will be removed from the series) hw/acpi: hack - generate dummy region ranges for first acpi-build (will be removed from the series) arch_init.c | 1 + hw/acpi/acpi-build-utils.c | 107 +++++++- hw/alpha/typhoon.c | 1 + hw/i386/acpi-build.c | 305 ++++++++++++++++++++- hw/i386/kvm/pci-assign.c | 1 + hw/i386/pc.c | 13 + hw/mips/gt64xxx_pci.c | 1 + hw/pci-bridge/Makefile.objs | 1 + hw/pci-bridge/pci_bridge_dev.c | 2 + hw/pci-bridge/pci_expander_bridge.c | 191 ++++++++++++++ hw/pci-host/bonito.c | 1 + hw/pci-host/grackle.c | 1 + hw/pci-host/piix.c | 63 ++++- hw/pci-host/ppce500.c | 1 + hw/pci-host/q35.c | 5 + hw/pci-host/uninorth.c | 1 + hw/pci/Makefile.objs | 2 +- hw/pci/pci-hotplug-old.c | 1 + hw/pci/pci.c | 501 +---------------------------------- hw/pci/pci_bus.c | 510 ++++++++++++++++++++++++++++++++++++ hw/pci/pci_host.c | 6 + hw/ppc/ppc4xx_pci.c | 1 + hw/scsi/megasas.c | 1 + hw/sh4/r2d.c | 1 + hw/sh4/sh_pci.c | 1 + hw/vfio/pci.c | 1 + hw/xen/xen_pt.c | 1 + include/hw/acpi/acpi-build-utils.h | 12 + include/hw/pci/pci.h | 6 +- include/hw/pci/pci_bus.h | 29 ++ include/hw/pci/pci_host.h | 11 + 31 files changed, 1267 insertions(+), 512 deletions(-) create mode 100644 hw/pci-bridge/pci_expander_bridge.c create mode 100644 hw/pci/pci_bus.c -- 2.1.0

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vgabios -> seabios breaks (my) 16-bit applications
by Richard Laager 17 Jan '15

17 Jan '15

I've recently upgraded a host from Ubuntu Precise (qemu-kvm-1.0) to Ubuntu Trusty (qemu 2.0.0). I have a Windows 2008 32-bit OS running on a 64-bit VM that runs a 16-bit line of business application. (While I realize that "upgrade the application" is the right answer, I can't.) The Windows VM boots, but the business application crashes on startup. Changing the VM to be a 32-bit VM doesn't help. After several hours of compiling and testing intermediate qemu versions, I accidentally stumbled into the real issue. Trusty has switched from vgabios to seabios. I have confirmed that switching the vgabios*.bin images back to the vgabios package (rather than seabios) fixes the 16-bit application in the guest. Per a suggestion on the Ubuntu bug I filed, I built an updated seabios package using the source from git (specifically, revision 60e0e55f212dadd043ab9e39bee05a48013ddd8f). It has the same problem. I then set CONFIG_DEBUG_LEVEL=8 and booted with "-chardev stdio,id=seabios -device isa-debugcon,iobase=0x402,chardev=seabios" per: http://www.seabios.org/pipermail/seabios/2011-May/001718.html The debug log is attached. For more details, including a couple of screenshots of the NTVDM crash dialog, see: https://bugs.launchpad.net/ubuntu/+source/qemu/+bug/1404396 What's the next step in debugging this? -- Richard

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[PATCH 0/9] Refactor USB send_bulk and send_control
by Kevin O'Connor 09 Jan '15

09 Jan '15

This series refactors parts of the internal USB driver code interface. It merges the ?hci_send_bulk() and ?hci_send_control() functions into one function ?hci_send_pipe(). The control and bulk transmission functions were similar, but often had slightly different implementations and quirks. Unifying them reduces the overall code size. It also makes it easier to issue control commands at run-time, which should make it easier for future enhancements (such as keyboard led control). I tested this on qemu and with a bunch of devices on my c720 and e350m1. However, I don't have a uhci board readily available. I'll have to dust off my via board and see if it still works. If others can run some tests that would be appreciated. In the process of testing this series, I found that USB3 hubs aren't working that great - I sometimes get timeout messages on my e350m1 (though all functionality still works), and usb3 hubs aren't working on my c720. This does not look to be a regression though. (It does seem that USB3 hubs still need more work though). This series is also available at: https://github.com/KevinOConnor/seabios/tree/testing -Kevin Kevin O'Connor (9): ehci: No need to support td array wrapping ehci: Merge ehci_send_control with ehci_send_bulk ohci: Merge ohci_send_control with ohci_send_bulk uhci: Merge uhci_send_control with uhci_send_bulk xhci: Merge xhci_send_control with xhci_send_bulk usb: Use usb_send_pipe() now that all drivers have x_send_pipe() xhci: Move xhci_xfer_x() functions together xhci: Merge some xhci_xfer_x() functions into xhci_send_pipe() usb: Control transfers always have an 8 byte command size src/hw/usb-ehci.c | 123 +++++++++++++++--------------------------- src/hw/usb-ehci.h | 5 +- src/hw/usb-ohci.c | 87 ++++++++++-------------------- src/hw/usb-ohci.h | 5 +- src/hw/usb-uhci.c | 96 ++++++++++++--------------------- src/hw/usb-uhci.h | 5 +- src/hw/usb-xhci.c | 156 +++++++++++++++++------------------------------------- src/hw/usb-xhci.h | 5 +- src/hw/usb.c | 40 ++++++-------- src/hw/usb.h | 2 + 10 files changed, 180 insertions(+), 344 deletions(-) -- 1.9.3

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