SeaBIOS

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3783 discussions

Re: [SeaBIOS] [Qemu-devel] [PATCH] SeaBios: Fix reset procedure reentrancy problem on qemu-kvm platform
by Kevin O'Connor 23 Dec '15

23 Dec '15

On Tue, Dec 22, 2015 at 03:15:26AM +0000, Xulei (Stone) wrote: > Hi, Kevin, > Can you tell how to reset/reboot this VM, if it goes to the handle_hwpic1() > on its booting procedure? I mean, usually, SeaBIOS would not go to > handle_hwpic routine. But in my test case, SeaBIOS calls handle_hwpic when > KVM injects a #UD expcetion (not irq) and SeaBIOS will loop to handle this > if KVM persistently injects exception. > > Now, i just wish to reset/reboot this VM if it is fall into handle_hwpic. I > tried follwing patch and it seems not work. What can i do to force reset/reboot? Call the reset() function. -Kevin

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Re: [SeaBIOS] SeaBIOS Digest, Vol 72, Issue 33
by Wim Vervoorn 22 Dec '15

22 Dec '15

Hello Stefan, I think it will work perfectly for the higher level functions like : tpm_smbios_measure(void) etc. Here you can easily implement tpm 1.2 and 2.0 handling. For the functions like tpm_add_measurement_to_log() I don't think it is that easy or useful. For those it's probably better to have a tpm 1.2 and a tpm 2.0 variant each with their own API but not with a wrapper. Please note I did not look into all details so I might be seeing problems that aren't there (or can be solved easily). Best Regards, Wim Vervoorn Eltan B.V. Ambachtstraat 23 5481 SM Schijndel The Netherlands T : +31-(0)73-594 46 64 E : wvervoorn(a)eltan.com W : http://www.eltan.com "THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS STRICTLY PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, PLEASE IMMEDIATELY NOTIFY THE SENDER BY TELEPHONE +31-(0)73-5944664 OR REPLY EMAIL, AND IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES." From: Stefan Berger [mailto:stefanb@us.ibm.com] Sent: Tuesday, December 22, 2015 2:56 PM To: Wim Vervoorn <wvervoorn(a)eltan.com> Cc: Kevin O'Connor <kevin(a)koconnor.net>; seabios(a)seabios.org Subject: RE: [SeaBIOS] SeaBIOS Digest, Vol 72, Issue 33 Wim Vervoorn <wvervoorn(a)eltan.com<mailto:wvervoorn@eltan.com>> wrote on 12/22/2015 08:43:54 AM: > > Hello Stefan, > > I have my doubts. This will work fine as long as the toplevel > function tpm_foo() in your example can be implemented to have a > single API independent of the required support. If the API differs > between the tpm 1.2 and tpm 2.0 case I think it will only be confusing things. > > Given the differences between tpm 1.2 and 2.0 do you think you will > be able to maintain this single API? The top level function tpm_foo() will be called by other SeaBIOS code for doing TPM initialization, measurements, the menu, S3 resume, and for the BIOS API. For the API we would support the same API for TPM 1.2 and for TPM 2. The difference between the tpm12_foo and tpm2_foo functions are mainly that different TPM commands are created and sent to the TIS. So far, this works fine. Do you have concrete concerns regarding this? How else would you do it ? Regards, Stefan > > > Best Regards, > Wim Vervoorn > > Eltan B.V. > Ambachtstraat 23 > 5481 SM Schijndel > The Netherlands > > T : +31-(0)73-594 46 64 > E : wvervoorn(a)eltan.com<mailto:wvervoorn@eltan.com> > W : http://www.eltan.com<http://www.eltan.com/> > "THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE > INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS > STRICTLY PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, > PLEASE IMMEDIATELY NOTIFY THE SENDER BY TELEPHONE +31-(0)73-5944664 > OR REPLY EMAIL, AND IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES." > > > > > From: Stefan Berger [mailto:stefanb@us.ibm.com] > Sent: Monday, December 21, 2015 5:50 PM > To: Kevin O'Connor <kevin(a)koconnor.net<mailto:kevin@koconnor.net>> > Cc: seabios(a)seabios.org<mailto:seabios@seabios.org>; Wim Vervoorn <wvervoorn(a)eltan.com<mailto:wvervoorn@eltan.com>> > Subject: Re: [SeaBIOS] SeaBIOS Digest, Vol 72, Issue 33 > > "Kevin O'Connor" <kevin(a)koconnor.net<mailto:kevin@koconnor.net>> wrote on 12/17/2015 05:22:56 PM: > > > > > On Mon, Nov 30, 2015 at 11:32:05AM +0000, Wim Vervoorn wrote: > > > Hello, > > > > > > I noticed that a lot of work is going on for the TPM support in SeaBIOS. > > > > > > All of this work is TPM 1.2 based. I was wondering if there are any > > > plans to support TPM 2.0 in the future. > > > > I'm not aware of any plans. > > We're working on it... > > > So maybe you have some comments to the following: > > There will be a patch for probing the TPM TIS hardware interface for > whether there's a TPM 1.2 or a TPM 2. > We then have a patch for prefixing all TPM 1.2 functions with tpm12_ > and then introduce functions like these ones here: > > static ... tpm12_foo() { ... } > static ... tpm2_foo() { ... } > > tpm_foo() > { > [...] > > switch (tpmversion) { > case TPM_VERSION_1_2: > tpm12_foo() > break; > case TPM_VERSION_2: > tpm2_foo(); > break; > } > > [...] > } > > That way the probing will lead us to use either TPM1.2 or TPM 2 > specific code. There will be multiple such constructs in tcgbios.c file. > > Stefan

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Re: [SeaBIOS] SeaBIOS Digest, Vol 72, Issue 33
by Wim Vervoorn 22 Dec '15

22 Dec '15

Hello Stefan, I have my doubts. This will work fine as long as the toplevel function tpm_foo() in your example can be implemented to have a single API independent of the required support. If the API differs between the tpm 1.2 and tpm 2.0 case I think it will only be confusing things. Given the differences between tpm 1.2 and 2.0 do you think you will be able to maintain this single API? Best Regards, Wim Vervoorn Eltan B.V. Ambachtstraat 23 5481 SM Schijndel The Netherlands T : +31-(0)73-594 46 64 E : wvervoorn(a)eltan.com W : http://www.eltan.com "THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS STRICTLY PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, PLEASE IMMEDIATELY NOTIFY THE SENDER BY TELEPHONE +31-(0)73-5944664 OR REPLY EMAIL, AND IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES." From: Stefan Berger [mailto:stefanb@us.ibm.com] Sent: Monday, December 21, 2015 5:50 PM To: Kevin O'Connor <kevin(a)koconnor.net> Cc: seabios(a)seabios.org; Wim Vervoorn <wvervoorn(a)eltan.com> Subject: Re: [SeaBIOS] SeaBIOS Digest, Vol 72, Issue 33 "Kevin O'Connor" <kevin(a)koconnor.net<mailto:kevin@koconnor.net>> wrote on 12/17/2015 05:22:56 PM: > > On Mon, Nov 30, 2015 at 11:32:05AM +0000, Wim Vervoorn wrote: > > Hello, > > > > I noticed that a lot of work is going on for the TPM support in SeaBIOS. > > > > All of this work is TPM 1.2 based. I was wondering if there are any > > plans to support TPM 2.0 in the future. > > I'm not aware of any plans. We're working on it... So maybe you have some comments to the following: There will be a patch for probing the TPM TIS hardware interface for whether there's a TPM 1.2 or a TPM 2. We then have a patch for prefixing all TPM 1.2 functions with tpm12_ and then introduce functions like these ones here: static ... tpm12_foo() { ... } static ... tpm2_foo() { ... } tpm_foo() { [...] switch (tpmversion) { case TPM_VERSION_1_2: tpm12_foo() break; case TPM_VERSION_2: tpm2_foo(); break; } [...] } That way the probing will lead us to use either TPM1.2 or TPM 2 specific code. There will be multiple such constructs in tcgbios.c file. Stefan

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Re: [SeaBIOS] [Qemu-devel] [PATCH] SeaBios: Fix reset procedure reentrancy problem on qemu-kvm platform
by Xulei (Stone) 22 Dec '15

22 Dec '15

Hi, Kevin, Can you tell how to reset/reboot this VM, if it goes to the handle_hwpic1() on its booting procedure? I mean, usually, SeaBIOS would not go to handle_hwpic routine. But in my test case, SeaBIOS calls handle_hwpic when KVM injects a #UD expcetion (not irq) and SeaBIOS will loop to handle this if KVM persistently injects exception. Now, i just wish to reset/reboot this VM if it is fall into handle_hwpic. I tried follwing patch and it seems not work. What can i do to force reset/reboot? @@ -7,10 +7,11 @@ #include "biosvar.h" // SET_IVT #include "config.h" // CONFIG_* #include "output.h" // dprintf #include "pic.h" // pic_* + #include "hw/ps2port.h" u16 pic_irqmask_read(void) { if (!CONFIG_HARDWARE_IRQ) @@ -103,10 +104,11 @@ pic_isr2_read(void) void VISIBLE16 handle_hwpic1(struct bregs *regs) { dprintf(DEBUG_ISR_hwpic1, "handle_hwpic1 irq=%x\n", pic_isr1_read()); pic_eoi1(); + i8042_reboot(); } useful information: kmod ftrace: <...>-31509 [035] 154753.180077: kvm_exit: reason EXCEPTION_NMI rip 0x3 info 0 80000306 <...>-31509 [035] 154753.180077: kvm_emulate_insn: 0:3:f0 53 (real) <...>-31509 [035] 154753.180077: kvm_inj_exception: #UD (0x0) <...>-31509 [035] 154753.180077: kvm_entry: vcpu 0 bad SeaBIOS log: [2015-12-17 12:37:30] In 32bit resume [2015-12-17 12:37:30] =====Attempting a hard reboot==== [2015-12-17 12:37:30] SeaBIOS (version rel-1.8.1-0-g4adadbd-20151217_104405-linux-emBwNn) [2015-12-17 12:37:30] No Xen hypervisor found. [2015-12-17 12:37:30] Running on QEMU (i440fx) [2015-12-17 12:37:30] Running on KVM [2015-12-17 12:37:30] RamSize: 0x80000000 [cmos] [2015-12-17 12:37:30] Relocating init from 0x000db230 to 0x7ffad360 (size 76768) [2015-12-17 12:37:30] Found QEMU fw_cfg [2015-12-17 12:37:30] RamBlock: addr 0x0000000000000000 len 0x0000000080000000 [e820] [2015-12-17 12:37:30] Moving pm_base to 0x600 [2015-12-17 12:37:30] boot order: [2015-12-17 12:37:30] 1: /pci@i0cf8/ide@1,1/drive@0/disk@0 [2015-12-17 12:37:30] 2: HALT [2015-12-17 12:37:30] maininit [2015-12-17 12:37:30] platform_hardware_setup [2015-12-17 12:37:30] init pic [2015-12-17 12:37:30] pic_setup [2015-12-17 12:37:30] pic_reset [2015-12-17 12:37:30] enable_hwirq [2015-12-17 12:37:30] CPU Mhz=3304 [2015-12-17 12:37:30] enable_hwirq [2015-12-17 12:37:30] enable_hwirq [2015-12-17 12:37:30] === PCI bus & bridge init === [2015-12-17 12:37:30] PCI: pci_bios_init_bus_rec bus = 0x0 [2015-12-17 12:37:30] === PCI device probing === [2015-12-17 12:37:30] Found 6 PCI devices (max PCI bus is 00) [2015-12-17 12:37:30] === PCI new allocation pass #1 === [2015-12-17 12:37:30] PCI: check devices [2015-12-17 12:37:30] === PCI new allocation pass #2 === [2015-12-17 12:37:30] PCI: IO: c000 - c02f [2015-12-17 12:37:30] PCI: 32: 0000000080000000 - 00000000fec00000 [2015-12-17 12:37:30] PCI: map device bdf=00:01.2 bar 4, addr 0000c000, size 00000020 [io] [2015-12-17 12:37:30] PCI: map device bdf=00:01.1 bar 4, addr 0000c020, size 00000010 [io] [2015-12-17 12:37:30] PCI: map device bdf=00:02.0 bar 6, addr febe0000, size 00010000 [mem] [2015-12-17 12:37:30] PCI: map device bdf=00:02.0 bar 1, addr febf0000, size 00001000 [mem] [2015-12-17 12:37:30] PCI: map device bdf=00:02.0 bar 0, addr fc000000, size 02000000 [prefmem] [2015-12-17 12:37:30] PCI: init bdf=00:00.0 id=8086:1237 [2015-12-17 12:37:30] PCI: init bdf=00:01.0 id=8086:7000 [2015-12-17 12:37:30] PIIX3/PIIX4 init: elcr=00 0c [2015-12-17 12:37:30] PCI: init bdf=00:01.1 id=8086:7010 [2015-12-17 12:37:30] PCI: init bdf=00:01.2 id=8086:7020 [2015-12-17 12:37:30] PCI: init bdf=00:01.3 id=8086:7113 [2015-12-17 12:37:30] Using pmtimer, ioport 0x608 [2015-12-17 12:37:30] PCI: init bdf=00:02.0 id=1013:00b8 [2015-12-17 12:37:30] PCI: Using 00:02.0 for primary VGA [2015-12-17 12:37:30] handle_hshamanpnd:dl leae_p_sismcmp_p:i: d a=ap3 <<======= everytime stuck, AP setup log seems abnormal! [2015-12-17 12:37:30] ièf[cf_^ifd_=f3 [2015-12-17 12:37:30] èf[f^f_f]fÃÍ^XË<90>Found 4 cpu(s) max supported 4 cpu(s) [2015-12-17 12:37:30] Copying PIR from 0x7ffbea18 to 0x000f5700 [2015-12-17 12:37:30] Copying MPTABLE from 0x00006e30/7ffa42c0 to 0x000f55e0 [2015-12-17 12:37:30] Copying SMBIOS entry point from 0x00006e11 to 0x000f55c0 [2015-12-17 12:37:31] Scan for VGA option rom [2015-12-17 12:37:31] Running option rom at c000:0003 [2015-12-17 12:37:31] Start SeaVGABIOS (version rel-1.8.1-0-g4adadbd-20150316_085902-nilsson.home.kraxel.org) [2015-12-17 12:37:31] enter vga_post: [2015-12-17 12:37:31] a=00000010 b=0000ffff c=00000000 d=0000ffff ds=0000 es=f000 ss=0000 [2015-12-17 12:37:31] si=00000000 di=000057e0 bp=00000000 sp=00006dbe cs=f000 ip=d1fb f=0000 [2015-12-17 12:37:31] cirrus init [2015-12-17 12:37:31] cirrus init 2 [2015-12-17 12:37:31] Attempting to allocate VGA stack via pmm call to f000:d2a0 <<====== here stuck, loop handle PIC irq0 [2015-12-17 12:37:35] handle_hwpic1 irq=0 [2015-12-17 12:37:35] handle_hwpic1 irq=0 [2015-12-17 12:37:35] handle_hwpic1 irq=0 [2015-12-17 12:37:35] handle_hwpic1 irq=0 [2015-12-17 12:37:35] handle_hwpic1 irq=0 [2015-12-17 12:37:35] handle_hwpic1 irq=0 [2015-12-17 12:37:35] handle_hwpic1 irq=0 [2015-12-17 12:37:35] handle_hwpic1 irq=0 [2015-12-17 12:37:35] handle_hwpic1 irq=0 [2015-12-17 12:37:35] handle_hwpic1 irq=0 ... always hanle_hwpic1 irq=0, never ends anymore... >> -----Original Message----- >> From: Kevin O'Connor [mailto:kevin@koconnor.net] >> Sent: Tuesday, December 22, 2015 2:47 AM >> To: Gonglei (Arei) >> Cc: Xulei (Stone); Paolo Bonzini; qemu-devel; seabios(a)seabios.org; >> Huangweidong (C); kvm(a)vger.kernel.org; Radim Krcmar >> Subject: Re: [Qemu-devel] [PATCH] SeaBios: Fix reset procedure reentrancy >> problem on qemu-kvm platform >> >> On Mon, Dec 21, 2015 at 09:41:32AM +0000, Gonglei (Arei) wrote: >> > When the gurb of OS is booting, then the softirq and C function >> > send_disk_op() may use extra stack of SeaBIOS. If we inject a NMI, >> > romlayout.S: irqentry_extrastack is invoked, and the extra stack will >> > be used again. And the stack of first calling will be broken, so that the >> SeaBIOS stuck. >> > >> > You can easily reproduce the problem. >> > >> > 1. start on guest >> > 2. reset the guest >> > 3. inject a NMI when the guest show the grub surface 4. then the guest >> > stuck >> >> Does the SeaBIOS patch below help? > >Sorry, it doesn't work. What's worse is we cannot stop SeaBIOS stuck by >Setting "CONFIG_ENTRY_EXTRASTACK=n" after applying this patch. > > >> I'm not familiar with how to "inject a >> NMI" - can you describe the process in more detail? >> > >1. Qemu Command line: > >#: /home/qemu/x86_64-softmmu/qemu-system-x86_64 -enable-kvm -m 4096 -smp 8 -name suse -vnc 0.0.0.0:10 \ >-device virtio-scsi-pci,id=scsi0 -drive file=/home/suse11_sp3_32_2,if=none,id=drive-scsi0-0-0-0,format=raw,cache=none,aio=native \ >-device scsi-hd,bus=scsi0.0,drive=drive-scsi0-0-0-0,id=scsi0-0-0-0 \ >-chardev file,id=seabios,path=/home/seabios.log -device isa-debugcon,iobase=0x402,chardev=seabios \ >-monitor stdio -qmp unix:/tmp/qmp,server,nowait > >2. Inject a NMI by QMP: > >#: /home/qemu/scripts/qmp # ./qmp-shell /tmp/qmp >Welcome to the QMP low-level shell! >Connected to QEMU 2.5.0 > >(QEMU) system_reset >{"return": {}} >(QEMU) inject-nmi >{"return": {}} >(QEMU) inject-nmi >{"return": {}} > > >Regards, >-Gonglei > >> -Kevin >> >> >> --- a/src/romlayout.S >> +++ b/src/romlayout.S >> @@ -548,7 +548,9 @@ entry_post: >> ENTRY_INTO32 _cfunc32flat_handle_post // Normal entry point >> >> ORG 0xe2c3 >> - IRQ_ENTRY 02 >> + .global entry_02 >> +entry_02: >> + ENTRY handle_02 // NMI handler does not switch onto extra >> +stack >> >> ORG 0xe3fe >> .global entry_13_official

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Re: [SeaBIOS] [Qemu-devel] [PATCH] SeaBios: Fix reset procedure reentrancy problem on qemu-kvm platform
by Kevin O'Connor 22 Dec '15

22 Dec '15

On Mon, Dec 21, 2015 at 09:41:32AM +0000, Gonglei (Arei) wrote: > When the gurb of OS is booting, then the softirq and C function send_disk_op() > may use extra stack of SeaBIOS. If we inject a NMI, romlayout.S: irqentry_extrastack > is invoked, and the extra stack will be used again. And the stack of first calling > will be broken, so that the SeaBIOS stuck. > > You can easily reproduce the problem. > > 1. start on guest > 2. reset the guest > 3. inject a NMI when the guest show the grub surface > 4. then the guest stuck Does the SeaBIOS patch below help? I'm not familiar with how to "inject a NMI" - can you describe the process in more detail? -Kevin --- a/src/romlayout.S +++ b/src/romlayout.S @@ -548,7 +548,9 @@ entry_post: ENTRY_INTO32 _cfunc32flat_handle_post // Normal entry point ORG 0xe2c3 - IRQ_ENTRY 02 + .global entry_02 +entry_02: + ENTRY handle_02 // NMI handler does not switch onto extra stack ORG 0xe3fe .global entry_13_official

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Re: [SeaBIOS] SeaBIOS recognising USB 3.0 on boot works - partly
by Kevin O'Connor 22 Dec '15

22 Dec '15

On Mon, Dec 21, 2015 at 06:44:18PM +0000, edward wandasiewicz wrote: > With 47-g977a7d4, we get > > 1. YES - we get no duplicate of the Philips, and get just one of each > appear in the boot list, Mushkin & Philips > > 2. NO - we sometimes get just the Mushkin only - no Philips detected - > with both devices plugged in, about 1 in 10 cold boot starts - both > plugged in USB 3 port and both plugged in Type C port > > The 2 Type C cables used, are those from the Google Play Store, for the record. > > cbmem attached for each. It looks like in both of the failure logs that the super/high confusion delayed the usb3 connection notification past the time SeaBIOS was looking for connection notifications. I suspect you could get around this by increasing "etc/usb-time-sigatt". (For example, by adding "$CBFSTOOL $CBFSFILE add-int -i 300 -n etc/usb-time-sigatt" to the "Other settings" section of the chrome image building script I previously sent.) This "secondary failure" after patch 47 is one of the reasons I'm not sure how to really fix the dup drive issue. -Kevin

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Re: [SeaBIOS] SeaBIOS recognising USB 3.0 on boot works - partly
by Kevin O'Connor 22 Dec '15

22 Dec '15

On Sun, Dec 20, 2015 at 09:47:04PM +0000, edward wandasiewicz wrote: > As requested, for rel-1.9.0-46-g636cbb4. Thanks. So, same as before? > Is it worth testing the double scenario, or maybe put it down to a > "manufacturer's flaw" going forward? I need additional time to think about that and to see if any other similar reports occur. In the mean time, could you pull testing again and retry (with 47-g977a7d4). I think that branch will fix the issue for you (and it could give you a short term workaround if you need that). -Kevin

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Re: [SeaBIOS] 5 basic features provided by CSM, which SeaBIOS does provide?
by Kevin O'Connor 22 Dec '15

22 Dec '15

On Mon, Dec 21, 2015 at 12:57:33PM +0000, Stojsavljevic, Zoran wrote: > Hello Kevin, > > All Good with setting CSM ON for legacy support. You need it for 16 bit BIOSes, and for legacy OSes, such as WIN XP or WIN 7 and derivatives. > > Here is the question I am wondering: What if I decide to bring FSP -> Coreboot -> SeaBIOS -> WIN 8.1 32. Do I really need SeaBIOS with option set to: CSM ON (I brought WIN 8.1 32 on CC2 with SeaBIOS and feature CSM ON)? In other words, can I bring WIN 8.1 32 on FSP -> Coreboot -> SeaBIOS with CSM OFF? > > The same question for: FSP -> Coreboot -> SeaBIOS -> WIN 8.1 64? I guess, here is CSM ON mandatory. Am I correct? > > Could I have a true 32 or 64 UEFI compliant OS on BSP: FSP -> Coreboot -> SeaBIOS -> UEFI OS sans/without CSM feature ON? The same one I have after bringing on UEFI 32/64 BIOS UEFI 32/64 OS (CSM is OFF always)? > In all of the above situations you must compile SeaBIOS with CONFIG_COREBOOT=y and CONFIG_CSM=n. CONFIG_CSM is mutually exclusive with CONFIG_COREBOOT, and if one is planning to run SeaBIOS directly from coreboot then one must use CONFIG_COREBOOT=y. -Kevin

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Re: [SeaBIOS] SeaBIOS Digest, Vol 72, Issue 33
by Wim Vervoorn 22 Dec '15

22 Dec '15

Hello, I noticed that a lot of work is going on for the TPM support in SeaBIOS. All of this work is TPM 1.2 based. I was wondering if there are any plans to support TPM 2.0 in the future. Best regards, Wim Vervoorn -----Original Message----- From: SeaBIOS [mailto:seabios-bounces@seabios.org] On Behalf Of seabios-request(a)seabios.org Sent: Monday, November 30, 2015 5:50 AM To: seabios(a)seabios.org Subject: SeaBIOS Digest, Vol 72, Issue 33 Send SeaBIOS mailing list submissions to seabios(a)seabios.org To subscribe or unsubscribe via the World Wide Web, visit http://www.seabios.org/mailman/listinfo/seabios or, via email, send a message with subject or body 'help' to seabios-request(a)seabios.org You can reach the person managing the list at seabios-owner(a)seabios.org When replying, please edit your Subject line so it is more specific than "Re: Contents of SeaBIOS digest..." Today's Topics: 1. [PATCH 0/3] tpm: Small fixes and add menu for TPM control (Stefan Berger) 2. [PATCH 3/3] tpm: Add a menu for TPM configuration (Stefan Berger) 3. [PATCH 2/3] tpm: Check length parameter of the array (Stefan Berger) ---------------------------------------------------------------------- Message: 1 Date: Sun, 29 Nov 2015 23:49:40 -0500 From: Stefan Berger <stefanb(a)us.ibm.com> To: seabios(a)seabios.org, kevin(a)koconnor.net Cc: Stefan Berger <stefanb(a)us.ibm.com> Subject: [SeaBIOS] [PATCH 0/3] tpm: Small fixes and add menu for TPM control Message-ID: <1448858983-19505-1-git-send-email-stefanb(a)us.ibm.com> This series provides two small fixes and then adds the menu for TPM control. Regards, Stefan Stefan Berger (3): Remove check for working TPM from TPM interrupt handler Check length parameter of the array tpm: Add a menu for TPM configuration src/boot.c | 9 +- src/std/tcg.h | 41 ++++ src/tcgbios.c | 661 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++- src/tcgbios.h | 2 + src/util.h | 1 + 5 files changed, 708 insertions(+), 6 deletions(-) -- 2.4.3 ------------------------------ Message: 2 Date: Sun, 29 Nov 2015 23:49:43 -0500 From: Stefan Berger <stefanb(a)us.ibm.com> To: seabios(a)seabios.org, kevin(a)koconnor.net Subject: [SeaBIOS] [PATCH 3/3] tpm: Add a menu for TPM configuration Message-ID: <1448858983-19505-4-git-send-email-stefanb(a)us.ibm.com> From: Stefan Berger <stefanb(a)linux.vnet.ibm.com> This patch adds an new menu entry to the main menu. This menu item enables the user to enter a TPM control menu which allows control of those aspects of the TPM's state that can only be controlled while in the firmware and while physical presence can be asserted. If the machine has a TPM, the boot menu will look as follows, with the new menu item accessible by pressing the 't' key. Select boot device: 1. ata0-1: QEMU HARDDISK ATA-7 Hard-Disk (6144 MiBytes) 2. Legacy option rom 3. iPXE (PCI 00:03.0) t. TPM Menu Upon pressing t the TPM submenu will be shown: The Trusted Platform Module (TPM) is a hardware device in this machine. It can help verify the integrity of system software. The current state of the TPM is: Enabled and active Ownership has not been taken A user can take ownership of the TPM Available options are: d. Disable the TPM v. Deactivate the TPM p. Prevent installation of an owner If no change is desired or if this menu was reached by mistake, press ESC to reboot the machine. The TPM menu only shows those options that are currently accessible considering the state of the TPM. The patch adds several functions for sending those messages to the TPM required for supporting those menu items. Signed-off-by: Stefan Berger <stefanb(a)linux.vnet.ibm.com> --- src/boot.c | 9 +- src/std/tcg.h | 41 ++++ src/tcgbios.c | 653 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/tcgbios.h | 2 + src/util.h | 1 + 5 files changed, 705 insertions(+), 1 deletion(-) diff --git a/src/boot.c b/src/boot.c index e0f73a3..a251eb4 100644 --- a/src/boot.c +++ b/src/boot.c @@ -427,7 +427,7 @@ get_raw_keystroke(void) } // Read a keystroke - waiting up to 'msec' milliseconds. -static int +int get_keystroke(int msec) { u32 end = irqtimer_calc(msec); @@ -486,6 +486,9 @@ interactive_bootmenu(void) printf("%d. %s\n", maxmenu , strtcpy(desc, pos->description, ARRAY_SIZE(desc))); } + if (tpm_is_working()) { + printf("\nt. TPM Configuration\n"); + } // Get key press. If the menu key is ESC, do not restart boot unless // 1.5 seconds have passed. Otherwise users (trained by years of @@ -496,6 +499,10 @@ interactive_bootmenu(void) scan_code = get_keystroke(1000); if (scan_code == 1 && !irqtimer_check(esc_accepted_time)) continue; + if (tpm_is_working() && scan_code == 20 /* t */) { + printf("\n"); + tpm_menu(); + } if (scan_code >= 1 && scan_code <= maxmenu+1) break; } diff --git a/src/std/tcg.h b/src/std/tcg.h index f6a47c7..d7b3fc4 100644 --- a/src/std/tcg.h +++ b/src/std/tcg.h @@ -292,6 +292,29 @@ struct tpm_res_getcap_perm_flags { struct tpm_permanent_flags perm_flags; } PACKED; +struct tpm_req_getcap_stclear_flags { + TPM_REQ_HEADER + u32 capArea; + u32 subCapSize; + u32 subCap; +} PACKED; + +struct tpm_stclear_flags { + u16 tag; + u8 flags[5]; +} PACKED; + +#define STCLEAR_FLAG_IDX_DEACTIVATED 0 +#define STCLEAR_FLAG_IDX_DISABLE_FORCE_CLEAR 1 +#define STCLEAR_FLAG_IDX_PHYSICAL_PRESENCE 2 +#define STCLEAR_FLAG_IDX_PHYSICAL_PRESENCE_LOCK 3 +#define STCLEAR_FLAG_IDX_GLOBAL_LOCK 4 + +struct tpm_res_getcap_stclear_flags { + TPM_RSP_HEADER + u32 size; + struct tpm_stclear_flags stclear_flags; +} PACKED; struct tpm_res_getcap_ownerauth { TPM_RSP_HEADER @@ -325,4 +348,22 @@ struct tpm_res_sha1complete { u8 hash[20]; } PACKED; +#define TPM_STATE_ENABLED 1 +#define TPM_STATE_ACTIVE 2 +#define TPM_STATE_OWNED 4 +#define TPM_STATE_OWNERINSTALL 8 + +/* + * physical presence interface + */ + +#define TPM_PPI_OP_NOOP 0 +#define TPM_PPI_OP_ENABLE 1 +#define TPM_PPI_OP_DISABLE 2 +#define TPM_PPI_OP_ACTIVATE 3 +#define TPM_PPI_OP_DEACTIVATE 4 +#define TPM_PPI_OP_CLEAR 5 +#define TPM_PPI_OP_SET_OWNERINSTALL_TRUE 8 +#define TPM_PPI_OP_SET_OWNERINSTALL_FALSE 9 + #endif // tcg.h diff --git a/src/tcgbios.c b/src/tcgbios.c index 285723c..e28d3eb 100644 --- a/src/tcgbios.c +++ b/src/tcgbios.c @@ -23,6 +23,8 @@ #include "string.h" // checksum #include "tcgbios.h"// tpm_*, prototypes #include "util.h" // printf, get_keystroke +#include "malloc.h" // malloc_* +#include "stacks.h" // wait_threads static const u8 Startup_ST_CLEAR[] = { 0x00, TPM_ST_CLEAR }; static const u8 Startup_ST_STATE[] = { 0x00, TPM_ST_STATE }; @@ -40,6 +42,11 @@ static const u8 GetCapability_Permanent_Flags[] = { 0x00, 0x00, 0x01, 0x08 }; +static const u8 GetCapability_STClear_Flags[] = { + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x04, + 0x00, 0x00, 0x01, 0x09 +}; + static const u8 GetCapability_OwnerAuth[] = { 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x11 @@ -88,6 +95,12 @@ tpm_state_t tpm_state VARLOW = { .tpm_driver_to_use = TPM_INVALID_DRIVER, }; +typedef struct { + u8 op; +} tpm_bios_cfg; + +extern void reset_vector(void) __noreturn; + static u32 is_preboot_if_shutdown(void) { @@ -136,6 +149,15 @@ has_working_tpm(void) return tpm_state.tpm_working; } +int +tpm_is_working(void) +{ + if (!CONFIG_TCGBIOS) + return 0; + + return tpm_state.tpm_working; +} + static u32 transmit(u8 locty, struct tpm_req_header *req, void *respbuffer, u32 *respbufferlen, @@ -1169,3 +1191,634 @@ tpm_interrupt_handler32(struct bregs *regs) return; } + +static u32 +read_stclear_flags(char *buf, int buf_len) +{ + u32 rc; + u32 returnCode; + struct tpm_res_getcap_stclear_flags stcf; + + memset(buf, 0, buf_len); + + rc = build_and_send_cmd(0, TPM_ORD_GetCapability, + GetCapability_STClear_Flags, + sizeof(GetCapability_STClear_Flags), + (u8 *)&stcf, sizeof(stcf), + &returnCode, TPM_DURATION_TYPE_SHORT); + + dprintf(DEBUG_tcg, "TCGBIOS: Return code from TPM_GetCapability() " + "= 0x%08x\n", returnCode); + + if (rc || returnCode) + goto err_exit; + + memcpy(buf, &stcf.stclear_flags, buf_len); + + return 0; + +err_exit: + dprintf(DEBUG_tcg, "TCGBIOS: TPM malfunctioning (line %d).\n", __LINE__); + + tpm_set_failure(); + if (rc) + return rc; + return TCG_TCG_COMMAND_ERROR; +} + +static u32 +assert_physical_presence(int verbose) +{ + u32 rc = 0; + u32 returnCode; + struct tpm_stclear_flags stcf; + + rc = read_stclear_flags((char *)&stcf, sizeof(stcf)); + if (rc) { + dprintf(DEBUG_tcg, + "Error reading STClear flags: 0x%08x\n", rc); + return rc; + } + + if (stcf.flags[STCLEAR_FLAG_IDX_PHYSICAL_PRESENCE]) + /* physical presence already asserted */ + return 0; + + rc = build_and_send_cmd(0, TPM_ORD_PhysicalPresence, + PhysicalPresence_CMD_ENABLE, + sizeof(PhysicalPresence_CMD_ENABLE), + NULL, 0, &returnCode, TPM_DURATION_TYPE_SHORT); + + dprintf(DEBUG_tcg, + "Return code from TSC_PhysicalPresence(CMD_ENABLE) = 0x%08x\n", + returnCode); + + if (rc || returnCode) { + if (verbose) + printf("Error: Could not enable physical presence.\n\n"); + goto err_exit; + } + + rc = build_and_send_cmd(0, TPM_ORD_PhysicalPresence, + PhysicalPresence_PRESENT, + sizeof(PhysicalPresence_PRESENT), + NULL, 0, &returnCode, TPM_DURATION_TYPE_SHORT); + + dprintf(DEBUG_tcg, + "Return code from TSC_PhysicalPresence(PRESENT) = 0x%08x\n", + returnCode); + + if (rc || returnCode) { + if (verbose) + printf("Error: Could not set presence flag.\n\n"); + goto err_exit; + } + + return 0; + +err_exit: + dprintf(DEBUG_tcg, "TCGBIOS: TPM malfunctioning (line %d).\n", __LINE__); + + tpm_set_failure(); + if (rc) + return rc; + return TCG_TCG_COMMAND_ERROR; +} + +static u32 +read_permanent_flags(char *buf, int buf_len) +{ + u32 rc; + u32 returnCode; + struct tpm_res_getcap_perm_flags pf; + + memset(buf, 0, buf_len); + + rc = build_and_send_cmd(0, TPM_ORD_GetCapability, + GetCapability_Permanent_Flags, + sizeof(GetCapability_Permanent_Flags), + (u8 *)&pf, sizeof(pf), + &returnCode, TPM_DURATION_TYPE_SHORT); + + dprintf(DEBUG_tcg, "TCGBIOS: Return code from TPM_GetCapability() " + "= 0x%08x\n", returnCode); + + if (rc || returnCode) + goto err_exit; + + memcpy(buf, &pf.perm_flags, buf_len); + + return 0; + +err_exit: + dprintf(DEBUG_tcg, "TCGBIOS: TPM malfunctioning (line %d).\n", __LINE__); + + tpm_set_failure(); + if (rc) + return rc; + return TCG_TCG_COMMAND_ERROR; +} + +static u32 +read_has_owner(int *has_owner) +{ + u32 rc; + u32 returnCode; + struct tpm_res_getcap_ownerauth oauth; + + rc = build_and_send_cmd(0, TPM_ORD_GetCapability, + GetCapability_OwnerAuth, + sizeof(GetCapability_OwnerAuth), + (u8 *)&oauth, sizeof(oauth), + &returnCode, TPM_DURATION_TYPE_SHORT); + + dprintf(DEBUG_tcg, "TCGBIOS: Return code from TPM_GetCapability() " + "= 0x%08x\n", returnCode); + + if (rc || returnCode) + goto err_exit; + + *has_owner = oauth.flag; + + return 0; + +err_exit: + dprintf(DEBUG_tcg,"TCGBIOS: TPM malfunctioning (line %d).\n", __LINE__); + + tpm_set_failure(); + if (rc) + return rc; + return TCG_TCG_COMMAND_ERROR; +} + +static u32 +enable_tpm(int enable, u32 *returnCode, int verbose) +{ + u32 rc; + struct tpm_permanent_flags pf; + + rc = read_permanent_flags((char *)&pf, sizeof(pf)); + if (rc) + return rc; + + if (pf.flags[PERM_FLAG_IDX_DISABLE] && !enable) + return 0; + + rc = assert_physical_presence(verbose); + if (rc) { + dprintf(DEBUG_tcg, "TCGBIOS: Asserting physical presence failed.\n"); + return rc; + } + + rc = build_and_send_cmd(0, enable ? TPM_ORD_PhysicalEnable + : TPM_ORD_PhysicalDisable, + NULL, 0, NULL, 0, returnCode, + TPM_DURATION_TYPE_SHORT); + if (enable) + dprintf(DEBUG_tcg, "Return code from TPM_PhysicalEnable = 0x%08x\n", + *returnCode); + else + dprintf(DEBUG_tcg, "Return code from TPM_PhysicalDisable = 0x%08x\n", + *returnCode); + + if (rc || *returnCode) + goto err_exit; + + return 0; + +err_exit: + if (enable) + dprintf(DEBUG_tcg, "TCGBIOS: Enabling the TPM failed.\n"); + else + dprintf(DEBUG_tcg, "TCGBIOS: Disabling the TPM failed.\n"); + + dprintf(DEBUG_tcg, "TCGBIOS: TPM malfunctioning (line %d).\n", __LINE__); + + tpm_set_failure(); + if (rc) + return rc; + return TCG_TCG_COMMAND_ERROR; +} + +static u32 +activate_tpm(int activate, int allow_reset, u32 *returnCode, int verbose) +{ + u32 rc; + struct tpm_permanent_flags pf; + + rc = read_permanent_flags((char *)&pf, sizeof(pf)); + if (rc) + return rc; + + if (pf.flags[PERM_FLAG_IDX_DEACTIVATED] && !activate) + return 0; + + if (pf.flags[PERM_FLAG_IDX_DISABLE]) + return 0; + + rc = assert_physical_presence(verbose); + if (rc) { + dprintf(DEBUG_tcg, "TCGBIOS: Asserting physical presence failed.\n"); + return rc; + } + + rc = build_and_send_cmd(0, TPM_ORD_PhysicalSetDeactivated, + activate ? CommandFlag_FALSE + : CommandFlag_TRUE, + activate ? sizeof(CommandFlag_FALSE) + : sizeof(CommandFlag_TRUE), + NULL, 0, returnCode, TPM_DURATION_TYPE_SHORT); + + dprintf(DEBUG_tcg, + "Return code from PhysicalSetDeactivated(%d) = 0x%08x\n", + activate ? 0 : 1, *returnCode); + + if (rc || *returnCode) + goto err_exit; + + if (activate && allow_reset) { + if (verbose) { + printf("Requiring a reboot to activate the TPM.\n"); + + msleep(2000); + } + reset_vector(); + } + + return 0; + +err_exit: + dprintf(DEBUG_tcg, "TCGBIOS: TPM malfunctioning (line %d).\n", __LINE__); + + tpm_set_failure(); + if (rc) + return rc; + return TCG_TCG_COMMAND_ERROR; +} + +static u32 +enable_activate(int allow_reset, u32 *returnCode, int verbose) +{ + u32 rc; + + rc = enable_tpm(1, returnCode, verbose); + if (rc) + return rc; + + rc = activate_tpm(1, allow_reset, returnCode, verbose); + + return rc; +} + +static u32 +force_clear(int enable_activate_before, int enable_activate_after, + u32 *returnCode, int verbose) +{ + u32 rc; + int has_owner; + + rc = read_has_owner(&has_owner); + if (rc) + return rc; + if (!has_owner) { + if (verbose) + printf("TPM does not have an owner.\n"); + return 0; + } + + if (enable_activate_before) { + rc = enable_activate(0, returnCode, verbose); + if (rc) { + dprintf(DEBUG_tcg, + "TCGBIOS: Enabling/activating the TPM failed.\n"); + return rc; + } + } + + rc = assert_physical_presence(verbose); + if (rc) { + dprintf(DEBUG_tcg, "TCGBIOS: Asserting physical presence failed.\n"); + return rc; + } + + rc = build_and_send_cmd(0, TPM_ORD_ForceClear, + NULL, 0, NULL, 0, returnCode, + TPM_DURATION_TYPE_SHORT); + + dprintf(DEBUG_tcg, "Return code from TPM_ForceClear() = 0x%08x\n", + *returnCode); + + if (rc || *returnCode) + goto err_exit; + + if (!enable_activate_after) { + if (verbose) + printf("Owner successfully cleared.\n" + "You will need to enable/activate the TPM again.\n\n"); + return 0; + } + + enable_activate(1, returnCode, verbose); + + return 0; + +err_exit: + dprintf(DEBUG_tcg, "TCGBIOS: TPM malfunctioning (line %d).\n", __LINE__); + + tpm_set_failure(); + if (rc) + return rc; + return TCG_TCG_COMMAND_ERROR; +} + +static u32 +set_owner_install(int allow, u32 *returnCode, int verbose) +{ + u32 rc; + int has_owner; + struct tpm_permanent_flags pf; + + rc = read_has_owner(&has_owner); + if (rc) + return rc; + if (has_owner) { + if (verbose) + printf("Must first remove owner.\n"); + return 0; + } + + rc = read_permanent_flags((char *)&pf, sizeof(pf)); + if (rc) + return rc; + + if (pf.flags[PERM_FLAG_IDX_DISABLE]) { + if (verbose) + printf("TPM must first be enable.\n"); + return 0; + } + + rc = assert_physical_presence(verbose); + if (rc) { + dprintf(DEBUG_tcg, "TCGBIOS: Asserting physical presence failed.\n"); + return rc; + } + + rc = build_and_send_cmd(0, TPM_ORD_SetOwnerInstall, + (allow) ? CommandFlag_TRUE : + CommandFlag_FALSE, + sizeof(CommandFlag_TRUE), + NULL, 0, returnCode, TPM_DURATION_TYPE_SHORT); + + dprintf(DEBUG_tcg, "Return code from TPM_SetOwnerInstall() = 0x%08x\n", + *returnCode); + + if (rc || *returnCode) + goto err_exit; + + if (verbose) + printf("Installation of owner %s.\n", allow ? "enabled" : "disabled"); + + return 0; + +err_exit: + dprintf(DEBUG_tcg, "TCGBIOS: TPM malfunctioning (line %d).\n", __LINE__); + tpm_set_failure(); + if (rc) + return rc; + return TCG_TCG_COMMAND_ERROR; +} + +static u32 +tpm_process_cfg(const tpm_bios_cfg *cfg, int verbose, u32 *returnCode) +{ + u32 rc = 0; + + switch (cfg->op) { + case TPM_PPI_OP_NOOP: /* no-op */ + break; + + case TPM_PPI_OP_ENABLE: + rc = enable_tpm(1, returnCode, verbose); + break; + + case TPM_PPI_OP_DISABLE: + rc = enable_tpm(0, returnCode, verbose); + break; + + case TPM_PPI_OP_ACTIVATE: + rc = activate_tpm(1, 1, returnCode, verbose); + break; + + case TPM_PPI_OP_DEACTIVATE: + rc = activate_tpm(0, 1, returnCode, verbose); + break; + + case TPM_PPI_OP_CLEAR: + rc = force_clear(1, 0, returnCode, verbose); + break; + + case TPM_PPI_OP_SET_OWNERINSTALL_TRUE: + rc = set_owner_install(1, returnCode, verbose); + break; + + case TPM_PPI_OP_SET_OWNERINSTALL_FALSE: + rc = set_owner_install(0, returnCode, verbose); + break; + + default: + break; + } + + if (rc) + printf("Op %d: An error occurred: 0x%x TPM return code: 0x%x\n", + cfg->op, rc, *returnCode); + + return rc; +} + +static int +get_tpm_state(void) +{ + int state = 0; + struct tpm_permanent_flags pf; + int has_owner; + + if (read_permanent_flags((char *)&pf, sizeof(pf)) || + read_has_owner(&has_owner)) + return ~0; + + if (!pf.flags[PERM_FLAG_IDX_DISABLE]) + state |= TPM_STATE_ENABLED; + + if (!pf.flags[PERM_FLAG_IDX_DEACTIVATED]) + state |= TPM_STATE_ACTIVE; + + if (has_owner) { + state |= TPM_STATE_OWNED; + } else { + if (pf.flags[PERM_FLAG_IDX_OWNERSHIP]) + state |= TPM_STATE_OWNERINSTALL; + } + + return state; +} + +static void +show_tpm_menu(int state, int next_scancodes[7]) +{ + int i = 0; + + printf("\nThe current state of the TPM is:\n"); + + if (state & TPM_STATE_ENABLED) + printf(" Enabled"); + else + printf(" Disabled"); + + if (state & TPM_STATE_ACTIVE) + printf(" and active\n"); + else + printf(" and deactivated\n"); + + if (state & TPM_STATE_OWNED) + printf(" Ownership has been taken\n"); + else { + printf(" Ownership has not been taken\n"); + if (state & TPM_STATE_OWNERINSTALL) + printf(" A user can take ownership of the TPM\n"); + else + printf(" Taking ownership of the TPM has been disabled\n"); + } + + if ((state & (TPM_STATE_ENABLED | TPM_STATE_ACTIVE)) != + (TPM_STATE_ENABLED | TPM_STATE_ACTIVE)) { + printf("\nNote: To make use of all functionality, the TPM must be " + "enabled and active.\n"); + } + + printf("\nAvailable options are:\n"); + if (state & TPM_STATE_ENABLED) { + printf(" d. Disable the TPM\n"); + next_scancodes[i++] = 32; + + if (state & TPM_STATE_ACTIVE) { + printf(" v. Deactivate the TPM\n"); + next_scancodes[i++] = 47; + + if (state & TPM_STATE_OWNERINSTALL) { + printf(" p. Prevent installation of an owner\n"); + next_scancodes[i++] = 25; + } else { + printf(" s. Allow installation of an owner\n"); + next_scancodes[i++] = 31; + } + } else { + printf(" a. Activate the TPM\n"); + next_scancodes[i++] = 30; + } + + } else { + printf(" e. Enable the TPM\n"); + next_scancodes[i++] = 18; + } + + if (state & TPM_STATE_OWNED) { + printf(" c. Clear ownership\n"); + next_scancodes[i++] = 46; + } + + next_scancodes[i++] = 0; +} + +void +tpm_menu(void) +{ + if (!CONFIG_TCGBIOS) + return; + + int scancode, next_scancodes[7]; + u32 rc, returnCode; + tpm_bios_cfg cfg = { + .op = TPM_PPI_OP_NOOP, + }; + int state = 0, i; + int waitkey; + + while (get_keystroke(0) >= 0) + ; + wait_threads(); + + printf("The Trusted Platform Module (TPM) is a hardware device in " + "this machine.\n" + "It can help verify the integrity of system software.\n\n"); + + for (;;) { + if ((state = get_tpm_state()) != ~0) { + show_tpm_menu(state, next_scancodes); + } else { + printf("TPM is not working correctly.\n"); + return; + } + + printf("\nIf no change is desired or if this menu was reached by " + "mistake, press ESC to\n" + "reboot the machine.\n"); + + cfg.op = TPM_PPI_OP_NOOP; + + waitkey = 1; + + while (waitkey) { + while ((scancode = get_keystroke(1000)) == ~0) + ; + + switch (scancode) { + case 1: + // ESC + reset_vector(); + break; + case 18: /* e. enable */ + cfg.op = TPM_PPI_OP_ENABLE; + break; + case 32: /* d. disable */ + cfg.op = TPM_PPI_OP_DISABLE; + break; + case 30: /* a. activate */ + cfg.op = TPM_PPI_OP_ACTIVATE; + break; + case 47: /* v. deactivate */ + cfg.op = TPM_PPI_OP_DEACTIVATE; + break; + case 46: /* c. clear owner */ + cfg.op = TPM_PPI_OP_CLEAR; + break; + case 25: /* p. prevent ownerinstall */ + cfg.op = TPM_PPI_OP_SET_OWNERINSTALL_FALSE; + break; + case 31: /* s. allow ownerinstall */ + cfg.op = TPM_PPI_OP_SET_OWNERINSTALL_TRUE; + break; + default: + continue; + } + + /* + * Using the next_scancodes array, check whether the + * pressed key is currently a valid option. + */ + for (i = 0; i < sizeof(next_scancodes); i++) { + if (next_scancodes[i] == 0) + break; + + if (next_scancodes[i] == scancode) { + rc = tpm_process_cfg(&cfg, 1, &returnCode); + + if (rc) + printf("An error occurred: 0x%x\n", rc); + waitkey = 0; + break; + } + } + } + } +} diff --git a/src/tcgbios.h b/src/tcgbios.h index 4d69b1e..7934fc3 100644 --- a/src/tcgbios.h +++ b/src/tcgbios.h @@ -13,5 +13,7 @@ u32 tpm_add_bcv(u32 bootdrv, const u8 *addr, u32 length); u32 tpm_add_cdrom(u32 bootdrv, const u8 *addr, u32 length); u32 tpm_add_cdrom_catalog(const u8 *addr, u32 length); u32 tpm_option_rom(const void *addr, u32 len); +int tpm_is_working(void); +void tpm_menu(void); #endif /* TCGBIOS_H */ diff --git a/src/util.h b/src/util.h index 7fcd6dc..76db57f 100644 --- a/src/util.h +++ b/src/util.h @@ -36,6 +36,7 @@ int bootprio_find_pci_rom(struct pci_device *pci, int instance); int bootprio_find_named_rom(const char *name, int instance); struct usbdevice_s; int bootprio_find_usb(struct usbdevice_s *usbdev, int lun); +int get_keystroke(int msec); // bootsplash.c void enable_vga_console(void); -- 2.4.3 ------------------------------ Message: 3 Date: Sun, 29 Nov 2015 23:49:42 -0500 From: Stefan Berger <stefanb(a)us.ibm.com> To: seabios(a)seabios.org, kevin(a)koconnor.net Subject: [SeaBIOS] [PATCH 2/3] tpm: Check length parameter of the array Message-ID: <1448858983-19505-3-git-send-email-stefanb(a)us.ibm.com> From: Stefan Berger <stefanb(a)linux.vnet.ibm.com> Check the length parameter that indicates the length of the array for whether it has a minimum value of 0x200. Signed-off-by: Stefan Berger <stefanb(a)linux.vnet.ibm.com> --- src/tcgbios.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/tcgbios.c b/src/tcgbios.c index c17d80d..285723c 100644 --- a/src/tcgbios.c +++ b/src/tcgbios.c @@ -766,6 +766,9 @@ tpm_add_bcv(u32 bootdrv, const u8 *addr, u32 length) if (!has_working_tpm()) return TCG_GENERAL_ERROR; + if (length < 0x200) + return TCG_INVALID_INPUT_PARA; + const char *string = "Booting BCV device 00h (Floppy)"; if (bootdrv == 0x80) string = "Booting BCV device 80h (HDD)"; -- 2.4.3 ------------------------------ Subject: Digest Footer _______________________________________________ SeaBIOS mailing list SeaBIOS(a)seabios.org http://www.seabios.org/mailman/listinfo/seabios ------------------------------ End of SeaBIOS Digest, Vol 72, Issue 33 ***************************************

3 2

Re: [SeaBIOS] 5 basic features provided by CSM, which SeaBIOS does provide?
by Kevin O'Connor 21 Dec '15

21 Dec '15

On Fri, Dec 18, 2015 at 08:43:37AM +0000, Stojsavljevic, Zoran wrote: > Hello both lists, Jiming, > > There are 5 basic features, provided by CSM SeaBIOS payload, and I > am looking to list of these features. > > Could you, please, provide to me list of these features, and some > description, and/or pointer to these descriptions? I don't fully understand your question. One can build SeaBIOS as a Compatibility Support Module (CSM) for UEFI, and this has been tested with OVMF on virtual machines. It's theoretically also possible to use it as a CSM on real hardware with a UEFI payload on coreboot, but to the best of my knowledge that has never been tested. When SeaBIOS is used as a CSM module, it provides legacy 16bit BIOS support on UEFI machines to bootloaders and option roms that require that support. The only link I have for SeaBIOS CSM is: http://www.seabios.org/Build_overview#Build_as_a_UEFI_Compatibility_Support… Cheers, -Kevin

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