SeaBIOS November 2024

seabios@seabios.org

7 participants
7 discussions

[PATCH v2 1/4] add debug when we set pci_pad_mem64
by John Levon 13 Nov '24

13 Nov '24

This is an interesting enough setting to add a dprintf() for. Signed-off-by: John Levon <john.levon(a)nutanix.com> --- src/fw/pciinit.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index bb44dc29..0395fdbf 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -1197,8 +1197,10 @@ pci_setup(void) } } - if (CPUPhysBits >= 36 && CPULongMode && RamSizeOver4G) + if (CPUPhysBits >= 36 && CPULongMode && RamSizeOver4G) { + dprintf(1, "enabling 64-bit pci mmio window\n"); pci_pad_mem64 = 1; + } dprintf(1, "=== PCI bus & bridge init ===\n"); if (pci_probe_host() != 0) { -- 2.34.1

8 31

[PATCH] Support multiple USB HID keyboards/mice
by Daniel Khodabakhsh 13 Nov '24

13 Nov '24

This change allows the use of multiple USB HID keyboards and mice. It's similar to the change by Stef van Os from this thread: https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/O6Y4LU… however this new change uses the linked list approach instead of a fixed array. Tested on QEMU and an Asus KGPE-D16 with 2 keyboards and one mice

2 4

[PATCH] Add force-boot-menu runtime configuration
by Daniel Khodabakhsh 12 Nov '24

12 Nov '24

This change adds a 'force-boot-menu' runtime configuration such that if a non-zero value is set and 'show-boot-menu' is also non-zero, SeaBIOS will show the boot menu without a timeout. This is similar to GRUB having a timeout set to '-1' and originally I wanted to implement it that way but the function to retrieve an integer retrieves an unsigned one so I thought this "boolean" configuration is a good way to implement it. Tested on ASUS KGPE-D16. From b1d69c8da90ab9ec25cc3f35ed5ee651e8405ff1 Mon Sep 17 00:00:00 2001 From: Daniel Khodabakhsh <d.khodabakhsh(a)gmail.com> Date: Thu, 7 Nov 2024 18:46:16 -0800 Subject: [PATCH] Add force-boot-menu runtime configuration. --- docs/Runtime_config.md | 1 + src/boot.c | 32 +++++++++++++++++++------------- 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/docs/Runtime_config.md b/docs/Runtime_config.md index 5795382b..af4da96a 100644 --- a/docs/Runtime_config.md +++ b/docs/Runtime_config.md @@ -177,6 +177,7 @@ There are several additional configuration options available in the | boot-menu-message | Customize the text boot menu message. Normally, when in text mode SeaBIOS will report the string "\\nPress ESC for boot menu.\\n\\n". This field allows the string to be changed. (This is a string field, and is added as a file containing the raw string.) | boot-menu-key | Controls which key activates the boot menu. The value stored is the DOS scan code (eg, 0x86 for F12, 0x01 for Esc). If this field is set, be sure to also customize the **boot-menu-message** field above. | boot-menu-wait | Amount of time (in milliseconds) to wait at the boot menu prompt before selecting the default boot. +| force-boot-menu | Forces the display of the boot menu unless the value is 0. **show-boot-menu** must also be set to 1. The default is 0. | boot-fail-wait | If no boot devices are found SeaBIOS will reboot after 60 seconds. Set this to the amount of time (in milliseconds) to customize the reboot delay or set to -1 to disable rebooting when no boot devices are found | extra-pci-roots | If the target machine has multiple independent root buses set this to a positive value. The SeaBIOS PCI probe will then search for the given number of extra root buses. | ps2-keyboard-spinup | Some laptops that emulate PS2 keyboards don't respond to keyboard commands immediately after powering on. One may specify the amount of time (in milliseconds) here to allow as additional time for the keyboard to become responsive. When this field is set, SeaBIOS will repeatedly attempt to detect the keyboard until the keyboard is found or the specified timeout is reached. diff --git a/src/boot.c b/src/boot.c index 1effd802..9bcb2480 100644 --- a/src/boot.c +++ b/src/boot.c @@ -708,20 +708,26 @@ interactive_bootmenu(void) return; } - while (get_keystroke(0) >= 0) - ; - - char *bootmsg = romfile_loadfile("etc/boot-menu-message", NULL); + // Show boot splash and proceed with booting if force_boot_menu == 0 (default), + // otherwise force display menu + int force_boot_menu = romfile_loadint("etc/force-boot-menu", 0); int menukey = romfile_loadint("etc/boot-menu-key", 1); - printf("%s", bootmsg ?: "\nPress ESC for boot menu.\n\n"); - free(bootmsg); - - u32 menutime = romfile_loadint("etc/boot-menu-wait", DEFAULT_BOOTMENU_WAIT); - enable_bootsplash(); - int scan_code = get_keystroke(menutime); - disable_bootsplash(); - if (scan_code != menukey) - return; + int scan_code; + if (force_boot_menu == 0) { + while (get_keystroke(0) >= 0) + ; + + char *bootmsg = romfile_loadfile("etc/boot-menu-message", NULL); + printf("%s", bootmsg ?: "\nPress ESC for boot menu.\n\n"); + free(bootmsg); + + u32 menutime = romfile_loadint("etc/boot-menu-wait", DEFAULT_BOOTMENU_WAIT); + enable_bootsplash(); + scan_code = get_keystroke(menutime); + disable_bootsplash(); + if (scan_code != menukey) + return; + } while (get_keystroke(0) >= 0) ; -- 2.46.0

2 2

[PATCH] resume: reset mmconfig to zero
by Omar Berrow 12 Nov '24

12 Nov '24

I apologize for the previous thing sent on the mailing list. On wake it would attempt to use the ECAM space to restore access to ECAM, which wouldn't work because ECAM is disabled after reset. Signed-off-by: Omar Berrow <omarkberrow(a)gmail.com> --- src/hw/pci.c | 2 +- src/resume.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/hw/pci.c b/src/hw/pci.c index 8eda84b2..dfe4d92a 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -14,7 +14,7 @@ #define PORT_PCI_CMD 0x0cf8 #define PORT_PCI_DATA 0x0cfc -static u32 mmconfig; +volatile u32 mmconfig; static void *mmconfig_addr(u16 bdf, u32 addr) { diff --git a/src/resume.c b/src/resume.c index fb0b8a89..10b873c3 100644 --- a/src/resume.c +++ b/src/resume.c @@ -96,6 +96,15 @@ s3_resume(void) return; } + make_bios_writable(); + // reset mmconfig to make sure that we don't use PCIe to + // resume PCIe + dprintf(1, "resetting mmconfig\n"); + extern volatile u32 mmconfig; + mmconfig = 0; + dprintf(1, "mmconfig: 0x%x\n", mmconfig); +// make_bios_readonly(); + pic_setup(); smm_setup(); smp_resume(); -- 2.45.2

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Fwd: [PATCH] resume: reset mmconfig to zero
by Omar Berrow 03 Nov '24

03 Nov '24

---------- Forwarded message --------- From: Omar Berrow <omarkberrow(a)gmail.com> Date: Sun, Nov 3, 2024 at 7:11 AM Subject: Re: [SeaBIOS] [PATCH] resume: reset mmconfig to zero To: Paul Menzel <pmenzel(a)molgen.mpg.de> > Also maybe mention the new log messages. > Should the log level be increased to 3, or is it important to have it in the logs? I must've forgotten to remove the printf while debugging, it's fine to completely remove it. > What’s the downside of not making the BIOS read-only? The BIOS does later write to mmconfig while resuming, it does indeed assume that the bios is writable, which, if I made it read-only again, would make this assumption false. > Nice find. Is there a way to reproduce your issue, for example with QEMU? Indeed: - Put QEMU into the S3 sleeping state. - When you wake the virtual machine, if you were to add logs in pci_config_writel, you would see that it tries to use ECAM space while access to the ECAM is being restored. Side effects: ECAM access was never truly restored in the BIOS on resume, so when the kernel then goes to access the PCIe bus through ECAM, it finds that no changes are going through. If you guys need a kernel that has S3 to verify this, I will link my kernel below https://github.com/OBOS-dev/obos/tree/b26e062af2c53ee6c3364a88784d22225ee27… (for the best performance, use CMAKE_BUILD_TYPE=Release and KVM) It should suspend right after printing: > [ LOG ] oboskrnl: Suspend requested Sincerely, Omar

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[PATCH] resume: reset mmconfig to zero
by Omar Berrow 03 Nov '24

03 Nov '24

Signed-off-by: Omar Berrow <omarkberrow(a)gmail.com> --- src/hw/pci.c | 2 +- src/resume.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/hw/pci.c b/src/hw/pci.c index 8eda84b2..dfe4d92a 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -14,7 +14,7 @@ #define PORT_PCI_CMD 0x0cf8 #define PORT_PCI_DATA 0x0cfc -static u32 mmconfig; +volatile u32 mmconfig; static void *mmconfig_addr(u16 bdf, u32 addr) { diff --git a/src/resume.c b/src/resume.c index fb0b8a89..10b873c3 100644 --- a/src/resume.c +++ b/src/resume.c @@ -96,6 +96,15 @@ s3_resume(void) return; } + make_bios_writable(); + // reset mmconfig to make sure that we don't use PCIe to + // resume PCIe + dprintf(1, "resetting mmconfig\n"); + extern volatile u32 mmconfig; + mmconfig = 0; + dprintf(1, "mmconfig: 0x%x\n", mmconfig); +// make_bios_readonly(); + pic_setup(); smm_setup(); smp_resume(); -- 2.45.2

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feature patch: NVRAM bootorder
by Timothy Kenno Handojo 01 Nov '24

01 Nov '24

Dear Maintainers, I hope this message finds you well. Attached is the patch containing some of my changes I'm proposing: 0001-boot-Allow-setting-bootorder-from-CMOS-entry.patch The change allows seabios to load bootorder not only from CBFS but also from the NVRAM as well, making use of coreboot's cmos.layout. To prepare testing environment: - Prepare the coreboot source code with coreboot-qemu-q35-cmos.layout-test.patch. Configure coreboot for QEMU Q35 platform. For the payload, you can select anything (I simply choose SeaBIOS for simplicity), with secondary payloads of coreinfo and nvramcui. I've attached the qemu-q35-defconfig to eliminate possible ambiguity. - Compile a coreboot.rom. - Prepare the SeaBIOS source code with 0001-boot-Allow-setting-bootorder-from-CMOS-entry.patch, and compile it. - On the newly compiled coreboot.rom, use cbfstool (which gets compiled along with the coreboot.rom) to remove fallback/payload, then add the newly compiled bios.bin.elf as the new fallback/payload. - Prepare a Linux bootable. In general, any Linux system would do as long as you can run the required software. I go with Alpine Linux live disk as its ISO image is only 64MB. Any additional files go in a secondary disk, including its overlay system. I simply created a 16MB image using dd command and then formatted it with FAT. - Compile cbmem and nvramtool from coreboot's util directory. For my Alpine Linux setup, I need to make sure to compile with musl instead of glibc (e.g. in an Alpine chroot) - Include cbmem and nvramtool to the Linux bootable. For my Alpine setup, I simply have a secondary disk image (also where I put the overlay). - For convenience, I'd put everything in the same directory. To actually test: - Run QEMU with `qemu-system-x86_64 -enable-kvm -cpu host -M q35 -bios coreboot-qemu.rom -m 1G <disks>` - For the QEMU options, serial output can be used as well, however it tends to break when loading coreinfo & nvramcui. Regardless, it's useful when all I have to do is debug with cbmem output. - On the BIOS screen, press Esc to see the menu. Note the disks should be on top. Boot to the disk. - Once your Linux system boots on QEMU, login to CLI as root, use nvramtool to modify the 'bootorder' entry. I myself ran `nvramtool -w bootorder="/rom@img/coreinfo"` to make it boot coreinfo first thing. - Reboot the QEMU system (do NOT kill the QEMU), press Esc again and see that coreinfo now jumps to the top. You can also not press Esc and see it loads coreinfo. Feel free to replace coreinfo with something else! Some todo - Create a tool to modify bootorder more properly (i.e. loading from file would be nice, for starters) -- in progress - Make bootorder a reserved section on cmos.layout to prevent unintended changes. - Test on a read hardware, I have a Thinkpad X230 eager to try it Do let me know if you have any feedback! Warm regards, Timothy Kenno Handojo

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SeaBIOS November 2024