SeaBIOS March 2020

seabios@seabios.org

17 participants
41 discussions

[PATCH] pci: add mmconfig support
by Gerd Hoffmann 23 Mar '20

23 Mar '20

Add support for pci config space access via mmconfig bar. Enable for qemu q35 chipset. Main advantage is that we need only one instead of two io operations per config space access, which translates to one instead of two vmexits for virtualization. Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/hw/pci.h | 1 + src/fw/pciinit.c | 1 + src/hw/pci.c | 54 ++++++++++++++++++++++++++++++++++++++++++------ 3 files changed, 50 insertions(+), 6 deletions(-) diff --git a/src/hw/pci.h b/src/hw/pci.h index 2e30e28918a0..01c51f705a00 100644 --- a/src/hw/pci.h +++ b/src/hw/pci.h @@ -39,6 +39,7 @@ u32 pci_config_readl(u16 bdf, u32 addr); u16 pci_config_readw(u16 bdf, u32 addr); u8 pci_config_readb(u16 bdf, u32 addr); void pci_config_maskw(u16 bdf, u32 addr, u16 off, u16 on); +void pci_enable_mmconfig(u64 addr, const char *name); u8 pci_find_capability(u16 bdf, u8 cap_id, u8 cap); int pci_next(int bdf, int bus); int pci_probe_host(void); diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index d5e87f00f164..d25931bb0573 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -480,6 +480,7 @@ static void mch_mmconfig_setup(u16 bdf) pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, 0); pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR + 4, upper); pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, lower); + pci_enable_mmconfig(Q35_HOST_BRIDGE_PCIEXBAR_ADDR, "q35"); } static void mch_mem_addr_setup(struct pci_device *dev, void *arg) diff --git a/src/hw/pci.c b/src/hw/pci.c index 9855badbc7da..3b8f43cbe5dc 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -14,38 +14,71 @@ #define PORT_PCI_CMD 0x0cf8 #define PORT_PCI_DATA 0x0cfc +static u32 mmconfig; + +static void *pci_mmconfig_addr(u16 bdf, u32 addr) +{ + if (!mmconfig) + return NULL; + return (void*)(mmconfig + ((u32)bdf << 12) + addr); +} + void pci_config_writel(u16 bdf, u32 addr, u32 val) { - outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD); - outl(val, PORT_PCI_DATA); + void *mmcfg = pci_mmconfig_addr(bdf, addr); + if (mmcfg) { + writel(mmcfg, val); + } else { + outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD); + outl(val, PORT_PCI_DATA); + } } void pci_config_writew(u16 bdf, u32 addr, u16 val) { - outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD); - outw(val, PORT_PCI_DATA + (addr & 2)); + void *mmcfg = pci_mmconfig_addr(bdf, addr); + if (mmcfg) { + writew(mmcfg, val); + } else { + outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD); + outw(val, PORT_PCI_DATA + (addr & 2)); + } } void pci_config_writeb(u16 bdf, u32 addr, u8 val) { - outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD); - outb(val, PORT_PCI_DATA + (addr & 3)); + void *mmcfg = pci_mmconfig_addr(bdf, addr); + if (mmcfg) { + writeb(mmcfg, val); + } else { + outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD); + outb(val, PORT_PCI_DATA + (addr & 3)); + } } u32 pci_config_readl(u16 bdf, u32 addr) { + void *mmcfg = pci_mmconfig_addr(bdf, addr); + if (mmcfg) + return readl(mmcfg); outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD); return inl(PORT_PCI_DATA); } u16 pci_config_readw(u16 bdf, u32 addr) { + void *mmcfg = pci_mmconfig_addr(bdf, addr); + if (mmcfg) + return readw(mmcfg); outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD); return inw(PORT_PCI_DATA + (addr & 2)); } u8 pci_config_readb(u16 bdf, u32 addr) { + void *mmcfg = pci_mmconfig_addr(bdf, addr); + if (mmcfg) + return readb(mmcfg); outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD); return inb(PORT_PCI_DATA + (addr & 3)); } @@ -58,6 +91,15 @@ pci_config_maskw(u16 bdf, u32 addr, u16 off, u16 on) pci_config_writew(bdf, addr, val); } +void +pci_enable_mmconfig(u64 addr, const char *name) +{ + if (addr >= 0x100000000ll) + return; + dprintf(1, "PCIe: using %s mmconfig at 0x%llx\n", name, addr); + mmconfig = addr; +} + u8 pci_find_capability(u16 bdf, u8 cap_id, u8 cap) { int i; -- 2.18.2

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GCC 10: tcgbios.c:290:30: warning: array subscript '(<unknown>) + 4294967295' is outside the bounds of an interior zero-length array 'struct TCG_EfiSpecIdEventAlgorithmSize[0]' [-Wzero-length-bounds]
by Paul Menzel 21 Mar '20

21 Mar '20

Dear SeaBIOS folks, Building SeaBIOS master with GCC 10 from Debian Sid/unstable, the compiler shows the warning below. ``` $ make CC=gcc-10 V=1 […] Compile checking out/src/tcgbios.o gcc-10 -Iout/ -Isrc -Os -MD -g -Wall -Wno-strict-aliasing -Wold-style-definition -Wtype-limits -m32 -march=i386 -mregparm=3 -mpreferred-stack-boundary=2 -minline-all-stringops -fomit-frame-pointer -freg-struct-return -ffreestanding -fno-delete-null-pointer-checks -ffunction-sections -fdata-sections -fno-common -fno-merge-constants -fno-pie -fno-stack-protector -fstack-check=no -Wno-address-of-packed-member -DMODE16=0 -DMODESEGMENT=0 -c src/tcgbios.c -o out/src/tcgbios.o src/tcgbios.c: In function 'tpm20_write_EfiSpecIdEventStruct': src/tcgbios.c:290:30: warning: array subscript '(<unknown>) + 4294967295' is outside the bounds of an interior zero-length array 'struct TCG_EfiSpecIdEventAlgorithmSize[0]' [-Wzero-length-bounds] 290 | event.hdr.digestSizes[count].algorithmId = be16_to_cpu(sel->hashAlg); | ~~~~~~~~~~~~~~~~~~~~~^~~~~~~ In file included from src/tcgbios.c:22: src/std/tcg.h:527:7: note: while referencing 'digestSizes' 527 | } digestSizes[0]; | ^~~~~~~~~~~ src/tcgbios.c:291:30: warning: array subscript '(<unknown>) + 4294967295' is outside the bounds of an interior zero-length array 'struct TCG_EfiSpecIdEventAlgorithmSize[0]' [-Wzero-length-bounds] 291 | event.hdr.digestSizes[count].digestSize = hsize; | ~~~~~~~~~~~~~~~~~~~~~^~~~~~~ In file included from src/tcgbios.c:22: src/std/tcg.h:527:7: note: while referencing 'digestSizes' 527 | } digestSizes[0]; | ^~~~~~~~~~~ […] ``` Kind regards, Paul

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Sometimes USB disks do not show up on first boot, I have to press Ctrl+Alt+Delete a few times for it to appear
by Dalao 20 Mar '20

20 Mar '20

I'm using coreboot with seabios on Thinkpad T420. I found that sometimes USB disks do not show up on first code boot (press the power button), possibly due to slow on detection? If I press Ctrl+Alt+Delete a few times, they will appear in the list. Recently I used clonezilla for backup and I was inspired by this feature. Clonezilla has the following screen that it will detection disks periodically until it find the disk. So I wonder could seabios implement features like this that after I press the ESC, the list will update periodically? ``` Every 3.0s: ocs-scan-disk 2020/03/21 03:22:25 You can insert storage device into this machine now if you want to use that, then wait for it to be detected. Scanning devices... Available disk(s) on this machine: =================================== Excluding busy partition or disk... /dev/sdb: Innostor_ Innostor_Innostor_0000000797508878-0:0 16.0GB =================================== Update periodically. Press Ctrl-C to exit this window. ```

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[PATCH] build: use -fcf-protection=none when available
by Christian Ehrhardt 20 Mar '20

20 Mar '20

Some hardened gcc v9 compilers (such as the one in Ubuntu) default this option which for seabios leads to emulation errors when running in KVM (does not trigger in TCG) on older intel chips of the Penryn generation (~2006-2008). Symptom in KVM looks like: KVM internal error. Suberror: 1 emulation failure EAX=00000000 EBX=00000000 ECX=000086d4 EDX=00000000 ESI=00000000 EDI=00000000 EBP=000086d4 ESP=00006d7c EIP=00007acf EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES =0000 00000000 ffffffff 00809300 CS =f000 000f0000 ffffffff 00809b00 SS =0000 00000000 ffffffff 00809300 DS =0000 00000000 ffffffff 00809300 FS =0000 00000000 ffffffff 00809300 GS =0000 00000000 ffffffff 00809300 LDT=0000 00000000 0000ffff 00008200 TR =0000 00000000 0000ffff 00008b00 GDT= 000f6200 00000037 IDT= 00000000 000003ff CR0=00000010 CR2=00000000 CR3=00000000 CR4=00000000 DR0=0000000000000000 DR1=0000000000000000 DR2=0000000000000000 DR3=0000000000000000 DR6=00000000ffff0ff0 DR7=0000000000000400 EFER=0000000000000000 Code=b8 90 d9 00 00 66 e8 6b f7 ff ff 66 b8 0a 00 00 00 e9 61 f2 <f3> 0f 1e fb 66 57 66 56 66 53 66 53 66 89 c7 67 66 89 14 24 66 89 ce 66 e8 15 f8 ff ff 88 URL: https://bugs.launchpad.net/ubuntu/+source/qemu/+bug/1866870 Signed-off-by: Christian Ehrhardt <christian.ehrhardt(a)canonical.com> --- Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile b/Makefile index 5f7d5370..9e8188e5 100644 --- a/Makefile +++ b/Makefile @@ -69,6 +69,7 @@ COMMONCFLAGS += $(call cc-option,$(CC),-fno-stack-protector,) COMMONCFLAGS += $(call cc-option,$(CC),-fno-stack-protector-all,) COMMONCFLAGS += $(call cc-option,$(CC),-fstack-check=no,) COMMONCFLAGS += $(call cc-option,$(CC),-Wno-address-of-packed-member,) +COMMONCFLAGS += $(call cc-option,$(CC),-fcf-protection=none,) COMMA := , CFLAGS32FLAT := $(COMMONCFLAGS) -DMODE16=0 -DMODESEGMENT=0 -- 2.25.1

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[PATCH] romlayout32flag.lds: Use `. +=` instead of `. =`
by Fangrui Song 18 Mar '20

18 Mar '20

This improves the portability of the linker script and allows lld to link rom.o We can thus delete an ld check detecting "cannot move location counter backwards". Dot assignment inside an output section has a inconsistent behavior which makes lld difficult to implement. See https://bugs.llvm.org/show_bug.cgi?id=43083 Signed-off-by: Fangrui Song <maskray(a)google.com> --- scripts/layoutrom.py | 7 ++++++- scripts/test-build.sh | 42 +----------------------------------------- 2 files changed, 7 insertions(+), 42 deletions(-) diff --git a/scripts/layoutrom.py b/scripts/layoutrom.py index 6616721..bbf07aa 100755 --- a/scripts/layoutrom.py +++ b/scripts/layoutrom.py @@ -335,14 +335,19 @@ def outRelSections(sections, startsym, useseg=0): if section.finalloc is not None] sections.sort(key=operator.itemgetter(0)) out = "" + dot = "_reloc_init_end" for addr, section in sections: loc = section.finalloc if useseg: loc = section.finalsegloc - out += ". = ( 0x%x - %s ) ;\n" % (loc, startsym) + if isinstance(dot, str): + out += ". += 0x%x - %s ;\n" % (loc, dot) + elif dot < loc: + out += ". += 0x%x ;\n" % (loc-dot,) if section.name in ('.rodata.str1.1', '.rodata'): out += "_rodata%s = . ;\n" % (section.fileid,) out += "*%s.*(%s)\n" % (section.fileid, section.name) + dot = loc + section.size return out # Build linker script output for a list of relocations. diff --git a/scripts/test-build.sh b/scripts/test-build.sh index 25cc2f2..8b35d6f 100755 --- a/scripts/test-build.sh +++ b/scripts/test-build.sh @@ -4,50 +4,10 @@ mkdir -p ${OUT} TMPFILE1=${OUT}/tmp_testcompile1.c TMPFILE1o=${OUT}/tmp_testcompile1.o -TMPFILE1_ld=${OUT}/tmp_testcompile1.lds TMPFILE2=${OUT}/tmp_testcompile2.c TMPFILE2o=${OUT}/tmp_testcompile2.o TMPFILE3o=${OUT}/tmp_testcompile3.o -# Test if ld's alignment handling is correct. This is a known problem -# with the linker that ships with Ubuntu 11.04. -cat - > $TMPFILE1 <<EOF -const char v1[] __attribute__((section(".text.v1"))) = "0123456789"; -const char v2[] __attribute__((section(".text.v2"))) = "0123456789"; -EOF -cat - > $TMPFILE1_ld <<EOF -SECTIONS -{ - .mysection 0x88f0 : { -. = 0x10 ; -*(.text.v1) -. = 0x20 ; -*(.text.v2) -. = 0x30 ; - } -} -EOF -$CC -O -g -c $TMPFILE1 -o $TMPFILE1o > /dev/null 2>&1 -if [ $? -ne 0 ]; then - echo "Unable to execute the C compiler ($CC)." >&2 - echo "" >&2 - echo "Please install a working compiler and retry." >&2 - echo -1 - exit 0 -fi -$LD -T $TMPFILE1_ld $TMPFILE1o -o $TMPFILE2o > /dev/null 2>&1 -if [ $? -ne 0 ]; then - echo "The version of LD on this system ($LD) does not properly handle" >&2 - echo "alignments. As a result, this project can not be built." >&2 - echo "" >&2 - echo "The problem may be the result of this LD bug report:" >&2 - echo " http://sourceware.org/bugzilla/show_bug.cgi?id=12726" >&2 - echo "" >&2 - echo "Please update to a working version of binutils and retry." >&2 - echo -1 - exit 0 -fi - # Test for "-fwhole-program". Older versions of gcc (pre v4.1) don't # support the whole-program optimization - detect that. $CC -fwhole-program -S -o /dev/null -xc /dev/null > /dev/null 2>&1 @@ -87,4 +47,4 @@ echo 0 # "ebp" register is clobberred in an "asm" statement. The code has # been modified to not clobber "ebp" - no test is available yet. -rm -f $TMPFILE1 $TMPFILE1o $TMPFILE1_ld $TMPFILE2 $TMPFILE2o $TMPFILE3o +rm -f $TMPFILE1 $TMPFILE1o $TMPFILE2 $TMPFILE2o $TMPFILE3o -- 2.25.1

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[PATCH] docs: Spell verb *set up* with a space
by Paul Menzel 18 Mar '20

18 Mar '20

Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- docs/Execution_and_code_flow.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Execution_and_code_flow.md b/docs/Execution_and_code_flow.md index 4a7ba8d..267464e 100644 --- a/docs/Execution_and_code_flow.md +++ b/docs/Execution_and_code_flow.md @@ -39,7 +39,7 @@ The POST phase itself has several sub-phases. * The "preinit" sub-phase: code run prior to [code relocation](Linking overview#Code relocation). * The "init" sub-phase: code to initialize internal variables and interfaces. -* The "setup" sub-phase: code to setup hardware and drivers. +* The "setup" sub-phase: code to set up hardware and drivers. * The "prepboot" sub-phase: code to finalize interfaces and prepare for the boot phase. -- 2.26.0.rc2

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[PATCH] optionroms: Use revision when finding Option ROM
by Paul Menzel 18 Mar '20

18 Mar '20

From: Rob Barnes <robbarnes(a)google.com> Date: Wed, 22 Jan 2020 14:09:21 -0700 Some devices have the same vendor and device ID but need different Option ROM files. Change the look-up to include the revision, then fallback to looking up without the revision. BUG=b:148125384 TEST=Manual, boot trembyle and confirm SeaBIOS console is displayed. Change-Id: I4c969b08727077fcb5ca1198e61cc6711c675019 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/seabios/+… Reviewed-by: Raul E Rangel <rrangel(a)chromium.org> Tested-by: Rob Barnes <robbarnes(a)google.com> Commit-Queue: Rob Barnes <robbarnes(a)google.com> Auto-Submit: Rob Barnes <robbarnes(a)google.com> --- src/optionroms.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/optionroms.c b/src/optionroms.c index e906ab9..c3aa9b0 100644 --- a/src/optionroms.c +++ b/src/optionroms.c @@ -329,10 +329,17 @@ init_pcirom(struct pci_device *pci, int isvga, u64 *sources) dprintf(4, "Attempting to init PCI bdf %pP (vd %04x:%04x)\n" , pci, pci->vendor, pci->device); - char fname[17]; - snprintf(fname, sizeof(fname), "pci%04x,%04x.rom" - , pci->vendor, pci->device); + char fname[20]; + // Try to find rom file with revision included + snprintf(fname, sizeof(fname), "pci%04x,%04x,%02x.rom" + , pci->vendor, pci->device, pci->revision); struct romfile_s *file = romfile_find(fname); + if (!file) { + // Fallback to finding rom file without revision + snprintf(fname, sizeof(fname), "pci%04x,%04x.rom" + , pci->vendor, pci->device); + file = romfile_find(fname); + } struct rom_header *rom = NULL; if (file) rom = deploy_romfile(file); -- 2.25.1

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[PATCH] Fix serial port detection on systems with Blizzard Chrome EC
by Paul Menzel 18 Mar '20

18 Mar '20

From: "Ronald G. Minnich" <rminnich(a)chromium.org> Date: Thu, 24 May 2012 11:27:26 -0700 Serial port detection in SeaBIOS tests for bit 2 in the IER. That bit is never set, and SeaBIOS mistakenly reports 0 serial ports. As it happens, just testing for IER to be not-all-ones is good enough. This happens on all systems where the AP serial port uses the Blizzard EC (Ivy Bridge, Haswell). Does not affect Bay Trail, since we use the native Intel serial port. It’s a hardware limitation of which registers the Blizzard COMx port implementation provides. Nothing we can do in EC software. BUG=chrome-os-partner:9946 TEST=build SeaBIOS with serial port enabled, and note that SeaBIOS says init serial Found 1 serial ports BRANCH=none Signed-off-by: Ronald G. Minnich <rminnich(a)chromium.org> Change-Id: I6bee73788ca6533091d85e54d05b37a564f910a7 Reviewed-on: https://chromium-review.googlesource.com/184421 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/227500 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- src/serial.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/serial.c b/src/serial.c index 88349c8..e67ac77 100644 --- a/src/serial.c +++ b/src/serial.c @@ -26,10 +26,12 @@ detect_serial(u16 port, u8 timeout, u8 count) return 0; outb(0x02, port+SEROFF_IER); u8 ier = inb(port+SEROFF_IER); - if (ier != 0x02) + dprintf(8, "IER is 0x%02x (Expected 0x02 or 0x00)\n", ier); + if (ier != 0x02 && ier != 0) return 0; u8 iir = inb(port+SEROFF_IIR); - if ((iir & 0x3f) != 0x02) + dprintf(8, "IIR is 0x%02x (Expected != 0x3f)\n", iir & 0x3f); + if ((iir & 0x3f) == 0x3f) return 0; outb(0x00, port+SEROFF_IER); -- 2.25.1

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[PATCH] Makefile: Allow overriding defconfig
by Paul Menzel 18 Mar '20

18 Mar '20

From: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri, 31 Jan 2014 13:53:58 -0800 Allow specifying a file instead of /dev/null for defconfig. BUG=none BRANCH=none TEST=emerge-panther chromeos-seabios works and produces usable SeaBIOS image Change-Id: I01d902eb9a6dff9ced7e3dd061aa33f831a64e8c Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/185752 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/227448 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> --- Makefile | 3 +++ scripts/kconfig/Makefile | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 5f7d537..b57b529 100644 --- a/Makefile +++ b/Makefile @@ -7,6 +7,9 @@ # Output directory OUT=out/ +# Default config (can be overriden) +KCONFIG_DEFCONFIG?=/dev/null + # Common command definitions export HOSTCC := $(CC) export CONFIG_SHELL := sh diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile index 1c12936..a3fe942 100644 --- a/scripts/kconfig/Makefile +++ b/scripts/kconfig/Makefile @@ -96,7 +96,7 @@ savedefconfig: $(obj)/conf defconfig: $(obj)/conf @echo " Build default config" - $(Q)$< --defconfig=/dev/null $(Kconfig) + $(Q)$< --defconfig=$(KCONFIG_DEFCONFIG) $(Kconfig) %_defconfig: $(obj)/conf $(Q)$< --defconfig=arch/$(SRCARCH)/configs/$@ $(Kconfig) -- 2.25.1

3 2

[PATCH 1/2] fw/coreboot: Log coreboot table entries
by Paul Menzel 17 Mar '20

17 Mar '20

If the log level is at least 5, print out the coreboot table entries to the console. This is useful for debugging. Relocating coreboot bios tables Looking at type 0x10 (start: 0x0, size 4096/0x1000) Looking at type 0x1 (start: 0x1000, size 651264/0x9f000) Looking at type 0x1 (start: 0xc0000, size 2146123776/0x7feb4000) Looking at type 0x10 (start: 0x7ff74000, size 573440/0x8c000) Copying SMBIOS entry point from 0x7ff74000 to 0x000f5700 Copying ACPI RSDP from 0x7ff75000 to 0x000f56e0 Looking at type 0x2 (start: 0xb0000000, size 268435456/0x10000000) Looking at type 0x1 (start: 0x100000000, size 2147483648/0x80000000) Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- src/fw/coreboot.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/fw/coreboot.c b/src/fw/coreboot.c index 7c0954b..96a4748 100644 --- a/src/fw/coreboot.c +++ b/src/fw/coreboot.c @@ -266,6 +266,8 @@ coreboot_platform_setup(void) int i, count = MEM_RANGE_COUNT(cbm); for (i=0; i<count; i++) { struct cb_memory_range *m = &cbm->map[i]; + dprintf(5, "Looking at type 0x%x (start: 0x%llx, size %llu/0x%llx)\n", + m->type, m->start, m->size, m->size); if (m->type == CB_MEM_TABLE) scan_tables(m->start, m->size); } -- 2.26.0.rc2

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SeaBIOS March 2020