SeaBIOS October 2017

seabios@seabios.org

17 participants
38 discussions

Re: [SeaBIOS] How to build seabios(coreboot style) with manually specified entry_elf() address ?
by Tang Rong 04 Oct '17

04 Oct '17

Modify the onboard firmware by myself is too risky. If anything goes wrong with my customized depthcharge, I'll need to reprogram the SPI, right? Any way to test it on qemu? On Wed, Oct 4, 2017 at 11:02 AM, Matt DeVillier <matt.devillier(a)gmail.com> wrote: > given what you're trying to do, I'd think it would be easier to modify > depthcharge to jump to RW_LEGACY later / after doing the other init normally > done when booting ChromeOS, than to try and shoehorn SeaBIOS into something > depthcharge would load like a kernel > > On Tue, Oct 3, 2017 at 9:42 PM, Tang Rong <phtr071(a)gmail.com> wrote: >> >> Hi Matt, we chated about kexec booting chromeos for Acer C710 on IRC, >> thanks a lot for your help. >> >> I digged to into depthcharge code, and found they did quite a lot of >> work, including patching the SMBIOS for fwid, redirecting ehci to >> xhci, etc. However, SeaBios on RW_LEGACY can not enjoy these work as >> legacy mode got started very early. In addition, flash >> seabios/tianocore on ssd (pretending to be linux kernel) would be much >> safer option. > >

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Re: [SeaBIOS] How to build seabios(coreboot style) with manually specified entry_elf() address ?
by Matt DeVillier 04 Oct '17

04 Oct '17

given what you're trying to do, I'd think it would be easier to modify depthcharge to jump to RW_LEGACY later / after doing the other init normally done when booting ChromeOS, than to try and shoehorn SeaBIOS into something depthcharge would load like a kernel On Tue, Oct 3, 2017 at 9:42 PM, Tang Rong <phtr071(a)gmail.com> wrote: > Hi Matt, we chated about kexec booting chromeos for Acer C710 on IRC, > thanks a lot for your help. > > I digged to into depthcharge code, and found they did quite a lot of > work, including patching the SMBIOS for fwid, redirecting ehci to > xhci, etc. However, SeaBios on RW_LEGACY can not enjoy these work as > legacy mode got started very early. In addition, flash > seabios/tianocore on ssd (pretending to be linux kernel) would be much > safer option. >

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Re: [SeaBIOS] How to build seabios(coreboot style) with manually specified entry_elf() address ?
by Tang Rong 04 Oct '17

04 Oct '17

Hi Matt, we chated about kexec booting chromeos for Acer C710 on IRC, thanks a lot for your help. I digged to into depthcharge code, and found they did quite a lot of work, including patching the SMBIOS for fwid, redirecting ehci to xhci, etc. However, SeaBios on RW_LEGACY can not enjoy these work as legacy mode got started very early. In addition, flash seabios/tianocore on ssd (pretending to be linux kernel) would be much safer option.

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Re: [SeaBIOS] How to build seabios(coreboot style) with manually specified entry_elf() address ?
by Matt DeVillier 04 Oct '17

04 Oct '17

what device are you targeting? John Lewis and I both offer firmware for Intel-based ChromeOS devices that boots directly to either SeaBIOS (for legacy boot) or Tianocore (for UEFI boot). If you just need SeaBIOS as a RW_LEGACY payload which will be loaded by depthcharge, we offer that too. See: https://mrchromebox.tech https://johnlewis.ie cheers, Matt On Tue, Oct 3, 2017 at 9:02 PM, Tang Rong <phtr071(a)gmail.com> wrote: > Hi SeaBios developers: > > I would like to build SeaBios as payload of chromebook Depthcharge > instead of coreboot, because Depthcharge seems to have some additional > device initialization on per-board basis. I did some search and found > SeaBios could be used as Grub2 payload, so I guess this is not mission > impossible. > > According to google's doc here: > http://dev.chromium.org/chromium-os/developer-information-for-chrome-os- > devices/custom-firmware > , depthcharge can copy any 32-bit blob into 0x100000, and directly > jump to it. So I will need the entry_elf to be 0x100000, and in > addition, anything instruction below 0x100000 should be safely > descarded without impacting seabios's functionality(because > depthcharge always jump to the beginning of the blob). > > Is it possible to build such a seabios raw blob with entry point as > 0x100000? If not, maybe I can use some 2-step jump: let depthcharge > jump to 0x100000 first, then jump to the real entry_elf? As I know > nothing about linkerscript or assembly, maybe some of you could help > me figure out. > > Thanks! > > _______________________________________________ > SeaBIOS mailing list > SeaBIOS(a)seabios.org > https://mail.coreboot.org/mailman/listinfo/seabios >

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How to build seabios(coreboot style) with manually specified entry_elf() address ?
by Tang Rong 04 Oct '17

04 Oct '17

Hi SeaBios developers: I would like to build SeaBios as payload of chromebook Depthcharge instead of coreboot, because Depthcharge seems to have some additional device initialization on per-board basis. I did some search and found SeaBios could be used as Grub2 payload, so I guess this is not mission impossible. According to google's doc here: http://dev.chromium.org/chromium-os/developer-information-for-chrome-os-dev… , depthcharge can copy any 32-bit blob into 0x100000, and directly jump to it. So I will need the entry_elf to be 0x100000, and in addition, anything instruction below 0x100000 should be safely descarded without impacting seabios's functionality(because depthcharge always jump to the beginning of the blob). Is it possible to build such a seabios raw blob with entry point as 0x100000? If not, maybe I can use some 2-step jump: let depthcharge jump to 0x100000 first, then jump to the real entry_elf? As I know nothing about linkerscript or assembly, maybe some of you could help me figure out. Thanks!

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How to build seabios(coreboot style) with manually specified entry_elf() address ?
by Tang Rong 03 Oct '17

03 Oct '17

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[PATCH v3 0/6] add serial console support
by Gerd Hoffmann 03 Oct '17

03 Oct '17

This patch series adds serial console support to seabios. Patches 1-4 add some bits the serial console patch depends on. Patch 5 adds the actual serial console support, for both primary display mode and splitmode (running in parallel to a vga display). The recommended way to activate the serial console is "qemu -machine graphics=no". Patch 6 is just for testing convenience and will not be merged. It makes the seabios serial console a drop-in replacement for sgabios, i.e. it is possible to activate it using "qemu -device sga". Gerd Hoffmann (6): std: add cp437 to unicode map kbd: make enqueue_key public, add ascii_to_keycode romfile: add support for constant files. paravirt: serial console configuration. add serial console support [hack] ignore sgabios, enable sercon instead Makefile | 3 +- src/config.h | 1 - src/cp437.h | 1 + src/romfile.h | 2 + src/util.h | 6 + src/clock.c | 1 + src/cp437.c | 275 ++++++++++++++++++++++ src/fw/paravirt.c | 8 + src/kbd.c | 18 +- src/misc.c | 8 - src/optionroms.c | 16 +- src/post.c | 2 + src/romfile.c | 46 ++++ src/sercon.c | 673 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/Kconfig | 5 + src/romlayout.S | 50 +++- 16 files changed, 1097 insertions(+), 18 deletions(-) create mode 100644 src/cp437.h create mode 100644 src/cp437.c create mode 100644 src/sercon.c -- 2.9.3

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characters display slowly when serial is enabled and debug level >=9
by Iru Cai 01 Oct '17

01 Oct '17

Hello, I just found that when I enable serial output and set debug level >=9, characters will display very slowly. It becomes worse when the machine has serial output. I can see the characters show on screen one by one. After I see the serial output. I think handler_16 is to blame, because there are many output for it. Iru -- Please do not send me Microsoft Office/Apple iWork documents. Send OpenDocument instead! http://fsf.org/campaigns/opendocument/

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SeaBIOS October 2017