SeaBIOS February 2016

seabios@seabios.org

21 participants
30 discussions

[RFC PATCH v4] fw/pci: Add support for mapping Intel IGD via QEMU
by Alex Williamson 11 May '16

11 May '16

QEMU provides two fw_cfg files to support IGD. The first holds the OpRegion data which holds the Video BIOS Table (VBT). This needs to be copied into reserved memory and the address stored in the ASL Storage register of the device at 0xFC offset in PCI config space. The OpRegion is generally 8KB. This file is named "etc/igd-opregion". The second file tells us the required size of the stolen memory space for the device. This is a dummy file, it has no backing so we only allocate the space … [View More]without copying anything into it. This space requires 1MB alignment and is generally either 1MB or 2MB, depending on the hardware config. If the user has opted in QEMU to expose additional stolen memory beyond the GTT (GGMS), the GMS may add an additional 32MB to 512MB. The base address of the reserved memory allocated for this is written back to the Base Data of Stolen Memory register (BDSM) at PCI config offset 0x5C on the device. This file is named "etc/igd-bdsm". Signed-off-by: Alex Williamson <alex.williamson(a)redhat.com> --- v4: Back to a single patch thanks to Kevin's suggestion to use memalign_tmphigh() for larger allocations. Now creating reserved space for stolen memory and writing the value to the BDSM register is queued off the existence of a fw_cfg file, just like the OpRegion. The only difference is that we don't copy the contents, just use the meta data. src/fw/pciinit.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 0ed5dfb..dc2e433 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -269,6 +269,49 @@ static void ich9_smbus_setup(struct pci_device *dev, void *arg) pci_config_writeb(bdf, ICH9_SMB_HOSTC, ICH9_SMB_HOSTC_HST_EN); } +static void intel_igd_setup(struct pci_device *dev, void *arg) +{ + struct romfile_s *opregion = romfile_find("etc/igd-opregion"); + struct romfile_s *bdsm = romfile_find("etc/igd-bdsm"); + void *addr; + u16 bdf = dev->bdf; + + if (opregion && opregion->size) { + addr = memalign_high(PAGE_SIZE, opregion->size); + if (!addr) { + warn_noalloc(); + return; + } + + if (opregion->copy(opregion, addr, opregion->size) < 0) { + free(addr); + return; + } + + pci_config_writel(bdf, 0xFC, cpu_to_le32((u32)addr)); + + dprintf(1, "Intel IGD OpRegion enabled at 0x%08x, size %dKB, dev " + "%02x:%02x.%x\n", (u32)addr, opregion->size >> 10, + pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf)); + } + + if (bdsm && bdsm->size) { + addr = memalign_tmphigh(1024 * 1024, bdsm->size); + if (!addr) { + warn_noalloc(); + return; + } + + e820_add((u32)addr, bdsm->size, E820_RESERVED); + + pci_config_writel(bdf, 0x5C, cpu_to_le32((u32)addr)); + + dprintf(1, "Intel IGD BDSM enabled at 0x%08x, size %dMB, dev " + "%02x:%02x.%x\n", (u32)addr, bdsm->size >> 20, + pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf)); + } +} + static const struct pci_device_id pci_device_tbl[] = { /* PIIX3/PIIX4 PCI to ISA bridge */ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, @@ -302,6 +345,10 @@ static const struct pci_device_id pci_device_tbl[] = { PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_setup), PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_setup), + /* Intel IGD OpRegion setup */ + PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, + intel_igd_setup), + PCI_DEVICE_END, }; [View Less]

4 6

[PATCH] fw/pci: add Q35 S3 support
by Marcel Apfelbaum 01 Mar '16

01 Mar '16

Following the i440fx example, save the LPC, SMBUS and PCIEXBAR bdfs between OS sleeps and use them to re-configure the corresponding registers. Signed-off-by: Marcel Apfelbaum <marcel(a)redhat.com> --- Hi, The patch was tested with Win7 and Fedora 23 guests. Any comments are welcomed. Thanks, Marcel src/fw/pciinit.c | 73 +++++++++++++++++++++++++++++++++++++++++++------------- 1 file changed, 56 insertions(+), 17 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index … [View More]5da6cf6..e44bab0 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -149,6 +149,22 @@ static void piix_isa_bridge_setup(struct pci_device *pci, void *arg) dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]); } +static void mch_isa_lpc_setup(u16 bdf) +{ + /* pm io base */ + pci_config_writel(bdf, ICH9_LPC_PMBASE, + acpi_pm_base | ICH9_LPC_PMBASE_RTE); + + /* acpi enable, SCI: IRQ9 000b = irq9*/ + pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN); + + /* set root complex register block BAR */ + pci_config_writel(bdf, ICH9_LPC_RCBA, + ICH9_LPC_RCBA_ADDR | ICH9_LPC_RCBA_EN); +} + +static int ICH9LpcBDF = -1; + /* ICH9 LPC PCI to ISA bridge */ /* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */ static void mch_isa_bridge_setup(struct pci_device *dev, void *arg) @@ -176,16 +192,10 @@ static void mch_isa_bridge_setup(struct pci_device *dev, void *arg) outb(elcr[1], ICH9_LPC_PORT_ELCR2); dprintf(1, "Q35 LPC init: elcr=%02x %02x\n", elcr[0], elcr[1]); - /* pm io base */ - pci_config_writel(bdf, ICH9_LPC_PMBASE, - acpi_pm_base | ICH9_LPC_PMBASE_RTE); + ICH9LpcBDF = bdf; - /* acpi enable, SCI: IRQ9 000b = irq9*/ - pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN); + mch_isa_lpc_setup(bdf); - /* set root complex register block BAR */ - pci_config_writel(bdf, ICH9_LPC_RCBA, - ICH9_LPC_RCBA_ADDR | ICH9_LPC_RCBA_EN); e820_add(ICH9_LPC_RCBA_ADDR, 16*1024, E820_RESERVED); acpi_pm1a_cnt = acpi_pm_base + 0x04; @@ -244,11 +254,8 @@ static void piix4_pm_setup(struct pci_device *pci, void *arg) pmtimer_setup(acpi_pm_base + 0x08); } -/* ICH9 SMBUS */ -/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_SMBUS */ -static void ich9_smbus_setup(struct pci_device *dev, void *arg) +static void ich9_smbus_enable(u16 bdf) { - u16 bdf = dev->bdf; /* map smbus into io space */ pci_config_writel(bdf, ICH9_SMB_SMB_BASE, (acpi_pm_base + 0x100) | PCI_BASE_ADDRESS_SPACE_IO); @@ -257,6 +264,17 @@ static void ich9_smbus_setup(struct pci_device *dev, void *arg) pci_config_writeb(bdf, ICH9_SMB_HOSTC, ICH9_SMB_HOSTC_HST_EN); } +int ICH9SmbusBDF = -1; + +/* ICH9 SMBUS */ +/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_SMBUS */ +static void ich9_smbus_setup(struct pci_device *dev, void *arg) +{ + ICH9SmbusBDF = dev->bdf; + + ich9_smbus_enable(dev->bdf); +} + static const struct pci_device_id pci_device_tbl[] = { /* PIIX3/PIIX4 PCI to ISA bridge */ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, @@ -293,6 +311,9 @@ static const struct pci_device_id pci_device_tbl[] = { PCI_DEVICE_END, }; +static int MCHMmcfgBDF = -1; +static void mch_mmconfig_setup(u16 bdf); + void pci_resume(void) { if (!CONFIG_QEMU) { @@ -302,6 +323,18 @@ void pci_resume(void) if (PiixPmBDF >= 0) { piix4_pm_config_setup(PiixPmBDF); } + + if (ICH9LpcBDF >= 0) { + mch_isa_lpc_setup(ICH9LpcBDF); + } + + if (ICH9SmbusBDF >= 0) { + ich9_smbus_enable(ICH9SmbusBDF); + } + + if(MCHMmcfgBDF >= 0) { + mch_mmconfig_setup(MCHMmcfgBDF); + } } static void pci_bios_init_device(struct pci_device *pci) @@ -388,18 +421,24 @@ static void i440fx_mem_addr_setup(struct pci_device *dev, void *arg) pci_slot_get_irq = piix_pci_slot_get_irq; } -static void mch_mem_addr_setup(struct pci_device *dev, void *arg) +static void mch_mmconfig_setup(u16 bdf) { u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR; - u32 size = Q35_HOST_BRIDGE_PCIEXBAR_SIZE; - - /* setup mmconfig */ - u16 bdf = dev->bdf; u32 upper = addr >> 32; u32 lower = (addr & 0xffffffff) | Q35_HOST_BRIDGE_PCIEXBAREN; pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, 0); pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR + 4, upper); pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, lower); +} + +static void mch_mem_addr_setup(struct pci_device *dev, void *arg) +{ + u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR; + u32 size = Q35_HOST_BRIDGE_PCIEXBAR_SIZE; + + /* setup mmconfig */ + MCHMmcfgBDF = dev->bdf; + mch_mmconfig_setup(dev->bdf); e820_add(addr, size, E820_RESERVED); /* setup pci i/o window (above mmconfig) */ -- 2.4.3 [View Less]

3 3

Entering protected mode (and back) in option ROM
by Bob Moore 29 Feb '16

29 Feb '16

Hello, I have a need to access 32 bit address space from within a 16 bit option ROM I'm writing. As a test I added code to load the gdt as required to set up 32 bit protected mode but I've encountered a problem. Below are my code and gdt structures. My issue is that when the ljmp is executed the model reboots (this is running on seabios under Qemu). I suspect a GP violation but can't seem to put my finger on it. I tried defining an idt containing a handler that hangs (i.e. jmp .) but was … [View More]

1 0

[PATCH 0/2] tpm2 logging
by Kevin O'Connor 29 Feb '16

29 Feb '16

Hi Stefan, What do you think about something like these two patches in place of your last patch 10? Basically using 'struct tcg_pcr_event2_sha1' instead of introducing a new 'struct log_entry'. -Kevin Kevin O'Connor (2): tpm: Unify tpm_fill_hash()/tpm_log_extend_event() and use in BIOS interface tpm: Write logs in TPM 2 format src/std/tcg.h | 35 ++++++++++++++ src/tcgbios.c | 145 +++++++++++++++++++++++++++++++++++++++------------------- 2 files changed, 133 insertions(+), 47 deletions(-) -- 2.5.0

2 9

[PATCH] ahci: set transfer mode according to the capabilities of connected drive
by Gerd Hoffmann 29 Feb '16

29 Feb '16

Use case: cf cards behind sata-ide bridge, which might not support the default transfer mode. Based on a patch by Werner Zeh <werner.zeh(a)siemens.com>, with some minor tweaks applied. Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/hw/ahci.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/hw/ata.h | 5 +++++ 2 files changed, 63 insertions(+) diff --git a/src/hw/ahci.c b/src/hw/ahci.c index 9310850..ea862f2 100644 --- a/src/hw/ahci.c +++ b/src/… [View More]hw/ahci.c @@ -515,6 +515,64 @@ static int ahci_port_setup(struct ahci_port_s *port) , ata_extract_version(buffer) , (u32)adjsize, adjprefix); port->prio = bootprio_find_ata_device(ctrl->pci_tmp, pnr, 0); + + s8 multi_dma = -1; + s8 pio_mode = -1; + s8 udma_mode = -1; + // If bit 2 in word 53 is set, udma information is valid in word 88. + if (buffer[53] & 0x04) { + udma_mode = 6; + while ((udma_mode >= 0) && + !((buffer[88] & 0x7f) & ( 1 << udma_mode ))) { + udma_mode--; + } + } + // If bit 1 in word 53 is set, multiword-dma and advanced pio modes + // are available in words 63 and 64. + if (buffer[53] & 0x02) { + pio_mode = 4; + multi_dma = 3; + while ((multi_dma >= 0) && + !((buffer[63] & 0x7) & ( 1 << multi_dma ))) { + multi_dma--; + } + while ((pio_mode >= 3) && + !((buffer[64] & 0x3) & ( 1 << ( pio_mode - 3 ) ))) { + pio_mode--; + } + + } + dprintf(2, "AHCI/%d: supported modes: udma %d, multi-dma %d, pio %d\n", + port->pnr, udma_mode, multi_dma, pio_mode); + + sata_prep_simple(&port->cmd->fis, ATA_CMD_SET_FEATURES); + port->cmd->fis.feature = ATA_SET_FEATRUE_TRANSFER_MODE; + // Select used mode. UDMA first, then Multi-DMA followed by + // advanced PIO modes 3 or 4. If non, set default PIO. + if (udma_mode >= 0) { + dprintf(1, "AHCI/%d: Set transfer mode to UDMA-%d\n", + port->pnr, udma_mode); + port->cmd->fis.sector_count = ATA_TRANSFER_MODE_ULTRA_DMA + | udma_mode; + } else if (multi_dma >= 0) { + dprintf(1, "AHCI/%d: Set transfer mode to Multi-DMA-%d\n", + port->pnr, multi_dma); + port->cmd->fis.sector_count = ATA_TRANSFER_MODE_MULTIWORD_DMA + | multi_dma; + } else if (pio_mode >= 3) { + dprintf(1, "AHCI/%d: Set transfer mode to PIO-%d\n", + port->pnr, pio_mode); + port->cmd->fis.sector_count = ATA_TRANSFER_MODE_PIO_FLOW_CTRL + | pio_mode; + } else { + dprintf(1, "AHCI/%d: Set transfer mode to default PIO\n", + port->pnr); + port->cmd->fis.sector_count = ATA_TRANSFER_MODE_DEFAULT_PIO; + } + rc = ahci_command(port, 1, 0, 0, 0); + if (rc < 0) { + dprintf(1, "AHCI/%d: Set transfer mode failed.\n", port->pnr); + } } else { // found cdrom (atapi) port->drive.type = DTYPE_AHCI_ATAPI; diff --git a/src/hw/ata.h b/src/hw/ata.h index cd14e59..9de2490 100644 --- a/src/hw/ata.h +++ b/src/hw/ata.h @@ -155,4 +155,9 @@ void ata_setup(void); #define ATA_CMD_READ_NATIVE_MAX_ADDRESS 0xF8 #define ATA_CMD_SET_MAX 0xF9 +#define ATA_SET_FEATRUE_TRANSFER_MODE 0x03 +#define ATA_TRANSFER_MODE_ULTRA_DMA 0x40 +#define ATA_TRANSFER_MODE_MULTIWORD_DMA 0x20 +#define ATA_TRANSFER_MODE_PIO_FLOW_CTRL 0x08 +#define ATA_TRANSFER_MODE_DEFAULT_PIO 0x00 #endif // ata.h -- 1.8.3.1 [View Less]

2 2

Re: [SeaBIOS] Serial keyboard support?
by Kevin O'Connor 25 Feb '16

25 Feb '16

On Thu, Feb 25, 2016 at 10:02:34AM -0800, Dustin Brazeau wrote: > As far as I can tell SeaBIOS does not currently support keyboard input over > serial. I was wondering if there is an unofficial patch that could add > support for this before I start looking into implementing it myself. Thanks. For traditional serial ports, sgabios generally fills that role. See the SeaBIOS coreboot wiki for info on sgabios: http://www.coreboot.org/SeaBIOS#Adding_sgabios_support -Kevin

1 0

Serial keyboard support?
by Dustin Brazeau 25 Feb '16

25 Feb '16

As far as I can tell SeaBIOS does not currently support keyboard input over serial. I was wondering if there is an unofficial patch that could add support for this before I start looking into implementing it myself. Thanks.

1 0

[PATCH] ld: fix .text section address alignment
by Roger Pau Monne 24 Feb '16

24 Feb '16

According to the output from readelf, the .text section should be aligned to 16: Section Headers: [Nr] Name Type Addr Off Size ES Flg Lk Inf Al [ 0] (null) NULL 00000000 000000 000000 00 0 0 0 [ 1] .text PROGBITS 000de300 000300 021d00 00 AX 0 0 16 [...] This however doesn't seem to be enforced when the relocations are generated. The following patch tries to address this by making sure the space used … [View More]

4 8

Re: [SeaBIOS] AHCI: Set transfer mode according to the capabilities of connected drive
by Kevin O'Connor 20 Feb '16

20 Feb '16

On Mon, Feb 15, 2016 at 12:00:48PM +0000, Zeh, Werner wrote: > Hi Kevin. > > We had some issues with some connected AHCI devices in SeaBIOS. We > have connected some CF-Cards by using a simple SATA<->IDE bridge to > the mainboard and in some cases, the drive (which is the CF-card) > was not recognized correctly. After some deeper analysis we found > that SeaBIOS does not set up the transfer rate which is used to > communicate to the drive. The supported transfer … [View More]

2 1

Error while compiling Seabios for Arch Linux ARM
by Xavier de Rauville 19 Feb '16

19 Feb '16

Greetings I am currently trying to compile Seabios for Arch Linux ARM and I've encountered an error during the compilation that appears to be caused by a misconfiguration in the file downloaded from here: http://code.coreboot.org/p/seabios/downloads/get/seabios-1.9.0.tar.gz I have attached a log containing the entire stdout and stderr stream output for Arch Linux's makepkg command but I think these might be the only lines of interest: Compile checking out/src/misc.o cc -Iout/ -Isrc -… [View More]

4 4

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

SeaBIOS February 2016