SeaBIOS July 2015

seabios@seabios.org

14 participants
33 discussions

[PATCH] timer: Add CONFIG_TSC_TIMER build option to disable the CPU TSC timer
by Kevin O'Connor 23 Jul '15

23 Jul '15

Allow users to remove the CPU timestamp counter support at compile time. The PMTIMER is frequently used instead of the TSC and this compile time option allows one to strip a few bytes from the final binary. This change also defaults the internal timer to use the PIT based timer until the PMTIMER or TSC is detected. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/Kconfig | 10 ++++++++-- src/hw/timer.c | 23 ++++++++--------------- 2 files changed, 16 insertions(+), 17 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 14c38fb..b14e554 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -316,10 +316,16 @@ menu "Hardware support" help Initialize the Memory Type Range Registers (on emulators). config PMTIMER - bool "Use ACPI timer" + bool "Support ACPI timer" default y help - Use the ACPI timer instead of the TSC for timekeeping (on qemu). + Detect and use the ACPI timer for timekeeping. + config TSC_TIMER + bool "Support CPU timestamp counter as timer" + default y + help + Support for using the CPU timestamp counter as an internal + timing source. endmenu menu "BIOS interfaces" diff --git a/src/hw/timer.c b/src/hw/timer.c index 5edc9fd..882b772 100644 --- a/src/hw/timer.c +++ b/src/hw/timer.c @@ -49,8 +49,8 @@ #define PMTIMER_HZ 3579545 // Underlying Hz of the PM Timer #define PMTIMER_TO_PIT 3 // Ratio of pmtimer rate to pit rate -u32 TimerKHz VARFSEG; -u16 TimerPort VARFSEG; +u32 TimerKHz VARFSEG = DIV_ROUND_UP(PMTIMER_HZ, 1000 * PMTIMER_TO_PIT); +u16 TimerPort VARFSEG = PORT_PIT_COUNTER0; u8 ShiftTSC VARFSEG; @@ -92,6 +92,7 @@ tsctimer_setup(void) t = (t + 1) >> 1; } TimerKHz = DIV_ROUND_UP((u32)t, 1000 * PMTIMER_TO_PIT); + TimerPort = 0; dprintf(1, "CPU Mhz=%u\n", (TimerKHz << ShiftTSC) / 1000); } @@ -100,24 +101,16 @@ tsctimer_setup(void) void timer_setup(void) { - if (CONFIG_PMTIMER && TimerPort) { - dprintf(3, "pmtimer already configured; will not calibrate TSC\n"); + if (!CONFIG_TSC_TIMER || (CONFIG_PMTIMER && TimerPort != PORT_PIT_COUNTER0)) return; - } + // Check if CPU has a timestamp counter u32 eax, ebx, ecx, edx, cpuid_features = 0; cpuid(0, &eax, &ebx, &ecx, &edx); if (eax > 0) cpuid(1, &eax, &ebx, &ecx, &cpuid_features); - - if (!(cpuid_features & CPUID_TSC)) { - TimerPort = PORT_PIT_COUNTER0; - TimerKHz = DIV_ROUND_UP(PMTIMER_HZ, 1000 * PMTIMER_TO_PIT); - dprintf(3, "386/486 class CPU. Using TSC emulation\n"); - return; - } - - tsctimer_setup(); + if (cpuid_features & CPUID_TSC) + tsctimer_setup(); } void @@ -154,7 +147,7 @@ static u32 timer_read(void) { u16 port = GET_GLOBAL(TimerPort); - if (!port) + if (CONFIG_TSC_TIMER && !port) // Read from CPU TSC return rdtscll() >> GET_GLOBAL(ShiftTSC); if (CONFIG_PMTIMER && port != PORT_PIT_COUNTER0) -- 1.9.3

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[PATCH] timer: Delay timestamp counter init until after pmtimer is probed
by Kevin O'Connor 22 Jul '15

22 Jul '15

Delay call to timer_setup() until after the xxx_platform_setup() calls so that the pmtimer can be detected first. Most modern machines will have a pmtimer and calibrating the timestamp counter is frequently unnecessary. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/post.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/post.c b/src/post.c index 8cb7b7c..6803585 100644 --- a/src/post.c +++ b/src/post.c @@ -168,13 +168,15 @@ platform_hardware_setup(void) pic_setup(); thread_setup(); mathcp_setup(); - timer_setup(); - clock_setup(); // Platform specific setup qemu_platform_setup(); coreboot_platform_setup(); + // Setup timers and periodic clock interrupt + timer_setup(); + clock_setup(); + // Initialize TPM tpm_setup(); } -- 1.9.3

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[PATCH] ps2: Don't wait 100ms to discard possible extra reset receive byte
by Kevin O'Connor 22 Jul '15

22 Jul '15

The existing PS2 port code waits 100ms to see if the device attached to the keyboard port responds to a reset command with two bytes (instead of the normal one byte). If an extra byte is received, it is discarded. Receiving two bytes would be unusual and waiting to check for that event is unnecessary because the next command in the keyboard init sequence already seamlessly discards any extra bytes in the command queue. This patch eliminates the 100ms wait, which notably reduces the SeaBIOS boot time on QEMU. This patch also forces PS2 mice to always respond with two bytes during a reset sequence (instead of just one byte), which is a good sanity check. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/hw/ps2port.c | 15 ++++++++------- src/hw/ps2port.h | 2 +- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/src/hw/ps2port.c b/src/hw/ps2port.c index 4558a6e..c368afc 100644 --- a/src/hw/ps2port.c +++ b/src/hw/ps2port.c @@ -242,8 +242,8 @@ __ps2_command(int aux, int command, u8 *param) if (ret) goto fail; - if (command == ATKBD_CMD_RESET_BAT) { - // Reset is special wrt timeouts and bytes received. + if ((u8)command == (u8)ATKBD_CMD_RESET_BAT) { + // Reset is special wrt timeouts. // Send command. ret = ps2_sendbyte(aux, command, 1000); @@ -255,11 +255,12 @@ __ps2_command(int aux, int command, u8 *param) if (ret < 0) goto fail; param[0] = ret; - ret = ps2_recvbyte(aux, 0, 100); - if (ret < 0) - // Some devices only respond with one byte on reset. - ret = 0; - param[1] = ret; + if (receive > 1) { + ret = ps2_recvbyte(aux, 0, 500); + if (ret < 0) + goto fail; + param[1] = ret; + } } else if (command == ATKBD_CMD_GETID) { // Getid is special wrt bytes received. diff --git a/src/hw/ps2port.h b/src/hw/ps2port.h index dc0e430..1338406 100644 --- a/src/hw/ps2port.h +++ b/src/hw/ps2port.h @@ -26,7 +26,7 @@ #define ATKBD_CMD_GETID 0x02f2 #define ATKBD_CMD_ENABLE 0x00f4 #define ATKBD_CMD_RESET_DIS 0x00f5 -#define ATKBD_CMD_RESET_BAT 0x02ff +#define ATKBD_CMD_RESET_BAT 0x01ff // Mouse commands #define PSMOUSE_CMD_SETSCALE11 0x00e6 -- 1.9.3

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[PATCH] ich9: initialise RCBA register through LPC interface
by Paulo Alcantara 14 Jul '15

14 Jul '15

This patch initialises root complex register block BAR in order to support TCO watchdog emulation features on QEMU. Signed-off-by: Paulo Alcantara <pcacjr(a)zytor.com> --- src/fw/dev-q35.h | 3 +++ src/fw/pciinit.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/src/fw/dev-q35.h b/src/fw/dev-q35.h index c6f8bd9..201825d 100644 --- a/src/fw/dev-q35.h +++ b/src/fw/dev-q35.h @@ -27,6 +27,9 @@ #define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4) #define ICH9_LPC_PORT_ELCR1 0x4d0 #define ICH9_LPC_PORT_ELCR2 0x4d1 +#define ICH9_LPC_RCBA 0xf0 +#define ICH9_LPC_RCBA_ADDR 0xfed1c000 +#define ICH9_LPC_RCBA_EN 0x1 #define PCI_DEVICE_ID_INTEL_ICH9_SMBUS 0x2930 #define ICH9_SMB_SMB_BASE 0x20 #define ICH9_SMB_HOSTC 0x40 diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index ac39d23..defccf3 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -183,6 +183,10 @@ static void mch_isa_bridge_setup(struct pci_device *dev, void *arg) /* acpi enable, SCI: IRQ9 000b = irq9*/ pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN); + /* set root complex register block BAR */ + pci_config_writel(bdf, ICH9_LPC_RCBA, + ICH9_LPC_RCBA_ADDR | ICH9_LPC_RCBA_EN); + acpi_pm1a_cnt = acpi_pm_base + 0x04; pmtimer_setup(acpi_pm_base + 0x08); } -- 2.1.0

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[PATCH] ps2: Support mode for polling the PS2 port instead of using irqs
by Kevin O'Connor 14 Jul '15

14 Jul '15

Some recent hardware has trouble with routing PS2 port interrupts while the interrupt controller is in legacy routing mode. This patch adds a config mechanism (via "etc/ps2-poll-only") to force the PS2 code into a polling only mode so that interrupts are not required. It is not recommended to use this polling mode on hardware that does properly support PS2 irqs, because some very old (DOS-era) programs depend on the BIOS PS2 irq behavior. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- It has been reported that some chromebooks can't use PS2 interrupts. The google seabios repo has a patch (implemented differently) to address this (eg, 2bc098e85). I don't actually have the impacted hardware, but I have tested this patch by forcing polling mode on both QEMU and real hardware and can verify that polling mode works. --- docs/Runtime_config.md | 1 + src/clock.c | 2 ++ src/hw/ps2port.c | 46 ++++++++++++++++++++++++++++++++++++++-------- src/hw/ps2port.h | 1 + 4 files changed, 42 insertions(+), 8 deletions(-) diff --git a/docs/Runtime_config.md b/docs/Runtime_config.md index 4ac0eae..962a8a9 100644 --- a/docs/Runtime_config.md +++ b/docs/Runtime_config.md @@ -180,6 +180,7 @@ There are several additional configuration options available in the | boot-fail-wait | If no boot devices are found SeaBIOS will reboot after 60 seconds. Set this to the amount of time (in milliseconds) to customize the reboot delay or set to -1 to disable rebooting when no boot devices are found | extra-pci-roots | If the target machine has multiple independent root buses set this to a positive value. The SeaBIOS PCI probe will then search for the given number of extra root buses. | ps2-keyboard-spinup | Some laptops that emulate PS2 keyboards don't respond to keyboard commands immediately after powering on. One may specify the amount of time (in milliseconds) here to allow as additional time for the keyboard to become responsive. When this field is set, SeaBIOS will repeatedly attempt to detect the keyboard until the keyboard is found or the specified timeout is reached. +| ps2-poll-only | SeaBIOS normally sets up the PS2 port to generate interrupts on keyboard and mouse events. One may set this field to a non-zero value to have SeaBIOS periodically poll the PS2 port for events instead. This may be useful on machines that do not properly route PS2 port interrupts. | optionroms-checksum | Option ROMs are required to have correct checksums. However, some option ROMs in the wild don't correctly follow the specifications and have bad checksums. Set this to a zero value to allow SeaBIOS to execute them anyways. | pci-optionrom-exec | Controls option ROM execution for roms found on PCI devices (as opposed to roms found in CBFS/fw_cfg). Valid values are 0: Execute no ROMs, 1: Execute only VGA ROMs, 2: Execute all ROMs. The default is 2 (execute all ROMs). | s3-resume-vga-init | Set this to a non-zero value to instruct SeaBIOS to run the vga rom on an S3 resume. diff --git a/src/clock.c b/src/clock.c index 28c168c..ee2b53f 100644 --- a/src/clock.c +++ b/src/clock.c @@ -8,6 +8,7 @@ #include "biosvar.h" // SET_BDA #include "bregs.h" // struct bregs #include "hw/pic.h" // pic_eoi1 +#include "hw/ps2port.h" // ps2_check_event #include "hw/rtc.h" // rtc_read #include "hw/usb-hid.h" // usb_check_event #include "output.h" // debug_enter @@ -297,6 +298,7 @@ handle_08(void) // Check for internal events. floppy_tick(); usb_check_event(); + ps2_check_event(); // chain to user timer tick INT #0x1c struct bregs br; diff --git a/src/hw/ps2port.c b/src/hw/ps2port.c index 04995c8..4558a6e 100644 --- a/src/hw/ps2port.c +++ b/src/hw/ps2port.c @@ -210,7 +210,8 @@ ps2_sendbyte(int aux, u8 command, int timeout) return 0; } -u8 Ps2ctr VARLOW; +u8 Ps2ctr VARLOW = I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; +u8 Ps2poll VARFSEG; static int __ps2_command(int aux, int command, u8 *param) @@ -232,6 +233,7 @@ __ps2_command(int aux, int command, u8 *param) yield(); // Enable port command is being sent to. + SET_LOW(Ps2ctr, newctr); if (aux) newctr &= ~I8042_CTR_AUXDIS; else @@ -308,6 +310,7 @@ __ps2_command(int aux, int command, u8 *param) fail: // Restore interrupts and keyboard/mouse. + SET_LOW(Ps2ctr, ps2ctr); ret2 = i8042_command(I8042_CMD_CTL_WCTR, &ps2ctr); if (ret2) return ret2; @@ -341,9 +344,11 @@ ps2_mouse_command(int command, u8 *param) // Update ps2ctr for mouse enable/disable. if (command == PSMOUSE_CMD_ENABLE || command == PSMOUSE_CMD_DISABLE) { + u8 ps2poll = GET_GLOBAL(Ps2poll); u8 ps2ctr = GET_LOW(Ps2ctr); if (command == PSMOUSE_CMD_ENABLE) - ps2ctr = (ps2ctr | I8042_CTR_AUXINT) & ~I8042_CTR_AUXDIS; + ps2ctr = ((ps2ctr | (ps2poll ? 0 : I8042_CTR_AUXINT)) + & ~I8042_CTR_AUXDIS); else ps2ctr = (ps2ctr | I8042_CTR_AUXDIS) & ~I8042_CTR_AUXINT; SET_LOW(Ps2ctr, ps2ctr); @@ -414,6 +419,30 @@ done: pic_eoi1(); } +void +ps2_check_event(void) +{ + if (! CONFIG_PS2PORT || !GET_GLOBAL(Ps2poll)) + return; + u8 ps2ctr = GET_LOW(Ps2ctr); + if ((ps2ctr & (I8042_CTR_KBDDIS|I8042_CTR_AUXDIS)) + == (I8042_CTR_KBDDIS|I8042_CTR_AUXDIS)) + return; + for (;;) { + u8 status = inb(PORT_PS2_STATUS); + if (!(status & I8042_STR_OBF)) + break; + u8 data = inb(PORT_PS2_DATA); + if (status & I8042_STR_AUXDATA) { + if (!(ps2ctr & I8042_CTR_AUXDIS)) + process_mouse(data); + } else { + if (!(ps2ctr & I8042_CTR_KBDDIS)) + process_key(data); + } + } +} + /**************************************************************** * Setup @@ -446,9 +475,6 @@ ps2_keyboard_setup(void *data) return; } - // Disable keyboard and mouse events. - SET_LOW(Ps2ctr, I8042_CTR_KBDDIS | I8042_CTR_AUXDIS); - /* ------------------- keyboard side ------------------------*/ /* reset keyboard and self test (keyboard side) */ @@ -482,7 +508,8 @@ ps2_keyboard_setup(void *data) return; // Keyboard Mode: disable mouse, scan code convert, enable kbd IRQ - SET_LOW(Ps2ctr, I8042_CTR_AUXDIS | I8042_CTR_XLATE | I8042_CTR_KBDINT); + Ps2ctr = (I8042_CTR_AUXDIS | I8042_CTR_XLATE + | (Ps2poll ? 0 : I8042_CTR_KBDINT)); /* Enable keyboard */ ret = ps2_kbd_command(ATKBD_CMD_ENABLE, NULL); @@ -500,8 +527,11 @@ ps2port_setup(void) return; dprintf(3, "init ps2port\n"); - enable_hwirq(1, FUNC16(entry_09)); - enable_hwirq(12, FUNC16(entry_74)); + Ps2poll = romfile_loadint("etc/ps2-poll-only", 0); + if (!Ps2poll) { + enable_hwirq(1, FUNC16(entry_09)); + enable_hwirq(12, FUNC16(entry_74)); + } run_thread(ps2_keyboard_setup, NULL); } diff --git a/src/hw/ps2port.h b/src/hw/ps2port.h index e5d9014..dc0e430 100644 --- a/src/hw/ps2port.h +++ b/src/hw/ps2port.h @@ -61,6 +61,7 @@ void i8042_reboot(void); int ps2_kbd_command(int command, u8 *param); int ps2_mouse_command(int command, u8 *param); +void ps2_check_event(void); void ps2port_setup(void); #endif // ps2port.h -- 1.9.3

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[PATCH 00/17] Block driver command dispatch cleanup
by Kevin O'Connor 14 Jul '15

14 Jul '15

This series implements some code reorganization in an attempt to simplify the disk driver command dispatch system. The series should have no user-visible changes - it's mostly just code reorg. At the end of the series, the command dispatch for "scsi style" devices is removed in favor of a single dispatch system for all drives. The series also makes the supported runtime modes (ie, 32bit or 16bit) of drivers more explicit. This series is also available at: https://github.com/KevinOConnor/seabios/tree/testing -Kevin Kevin O'Connor (17): block: Split process_op() command dispatch up into multiple functions block: Introduce default_process_op() with common command handling codes block: Route scsi style commands through 'struct disk_op_s' blockcmd: Introduce scsi_fill_cmd() ata: Handle ATA ATAPI drives directly via 'struct disk_op_s' requests ahci: Handle AHCI ATAPI drives directly via 'struct disk_op_s' requests usb-msc: Handle USB drives directly via 'struct disk_op_s' requests usb-uas: Handle USB drives directly via 'struct disk_op_s' requests lsi-scsi: Handle LSI drives directly via 'struct disk_op_s' requests esp-scsi: Handle ESP drives directly via 'struct disk_op_s' requests megasas: Handle Megasas drives directly via 'struct disk_op_s' requests virtio-scsi: Handle virtio drives directly via 'struct disk_op_s' requests pvscsi: Move pvscsi_fill_req() code into pvscsi_cmd() pvscsi: Handle pvscsi drives directly via 'struct disk_op_s' requests blockcmd: Remove unused scsi_process_op() and cdb_cmd_data() blockcmd: Convert cdb_is_read() to scsi_is_read() block: Rename process_XXX_op() functions to XXX_process_op() src/block.c | 152 +++++++++++++++++++++++++++++++-------------------- src/block.h | 14 ++++- src/cdrom.c | 15 ++--- src/hw/ahci.c | 29 ++++------ src/hw/ahci.h | 4 +- src/hw/ata.c | 17 +++--- src/hw/ata.h | 5 +- src/hw/blockcmd.c | 138 +++++++++++++++------------------------------- src/hw/blockcmd.h | 4 +- src/hw/esp-scsi.c | 33 +++++------ src/hw/esp-scsi.h | 2 +- src/hw/floppy.c | 2 +- src/hw/lsi-scsi.c | 32 +++++------ src/hw/lsi-scsi.h | 2 +- src/hw/megasas.c | 12 ++-- src/hw/megasas.h | 2 +- src/hw/pvscsi.c | 62 ++++++++------------- src/hw/pvscsi.h | 2 +- src/hw/ramdisk.c | 8 +-- src/hw/sdcard.c | 12 +--- src/hw/usb-msc.c | 14 +++-- src/hw/usb-msc.h | 2 +- src/hw/usb-uas.c | 6 +- src/hw/usb-uas.h | 2 +- src/hw/virtio-blk.c | 12 +--- src/hw/virtio-blk.h | 2 +- src/hw/virtio-scsi.c | 37 +++++-------- src/hw/virtio-scsi.h | 2 +- src/util.h | 8 +-- 29 files changed, 283 insertions(+), 349 deletions(-) -- 1.9.3

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Re: [SeaBIOS] [PATCHv2] coreboot: Try to auto-detect if the CBFS anchor pointer is a relative pointer
by Kevin O'Connor 14 Jul '15

14 Jul '15

On Wed, Jul 08, 2015 at 06:02:32PM -0700, Julius Werner wrote: > I guess this heuristic should be very unlikely to fail with the > current cbfstool implementation, so I'd be fine with it (at least as > long as SeaBIOS is x86-only... non-x86 CBFS put the header close to > the start address instead). > > Still, is anyone except Chrome OS actually using CONFIG_CBFS_LOCATION > and absolute offsets? Thanks for reviewing. SeaBIOS is x86 only. As far as I know only the Chrome machines use CONFIG_CBFS_LOCATION. >Because we have completely switched over now, > and the absolute offset was hacked in as part of our SeaBIOS build > script which is now updated, so at least with our SDK you can't really > build a new SeaBIOS with the old-style absolute offset unless you > intentionally revert some stuff. If there's no other system out there > that still relies on absolute offsets, I'd suggest to just switch over > to the new relative style completely. That's a good point. There are a couple of people building Chromebox roms though, and I'm a little leery of breaking their pre-existing build scripts. (Syching the build scripts with a particular SeaBIOS commit is annoying for those just wishing to try out the latest build.) So, I'm inclined to commit this hack, but view it as something that can get removed in a year or so. Thanks again, -Kevin

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Re: [SeaBIOS] Reducing SeaBIOS kernel entry time
by Marc Marí 09 Jul '15

09 Jul '15

On Wed, 8 Jul 2015 09:10:14 +0100 Stefan Hajnoczi <stefanha(a)gmail.com> wrote: > On Sat, Jul 4, 2015 at 6:57 PM, Kevin O'Connor <kevin(a)koconnor.net> > wrote: > > On Fri, Jul 03, 2015 at 03:12:14PM +0100, Stefan Hajnoczi wrote: > >> On Fri, Jul 3, 2015 at 2:13 PM, Kevin O'Connor > >> <kevin(a)koconnor.net> wrote: > >> > I took a look a month or so ago: > >> > > >> > http://article.gmane.org/gmane.comp.emulators.kvm.devel/136207 > >> > > >> > Last test I ran I had SeaBIOS down to 16ms (not including the > >> > time to deploy or jump to the linux kernel). More reductions > >> > are also possible - the above was just with Kconfig settings. > >> > I've been measuring the time for different configurations and setups. The conclusion is that the main bottleneck to boot QEMU is fw_cfg. Running a default SeaBIOS configuration gives these times (in seconds): (QEMU startup time is the time between the execution and the first kvm_entry, BIOS startup time is the time between the first kvm_entry and the ROM booting, and fw_cfg is the time between the ROM booting and the jump to the Linux kernel). QEMU startup time: .033 BIOS startup time: .154 fw_cfg setup time: .375 And these results are more or less the same in QBoot, when using fw_cfg: QEMU startup time: .026 BIOS startup time: .013 fw_cfg setup time: .373 The difference between SeaBIOS and QBoot is big, but, as I said, this SeaBIOS is not stripped-down. Using the .config that Kevin sent, I can get .01 seconds, but I cannot boot a ROM (I still have to play with the configuration options until it boots). Probably it can do it in less than 20 msec, which not far from QBoot. On the other side, QBoot with cbfs can boot really fast: QEMU startup time: .027 Kernel setup time: .017 Total time: .045 And I'll check CoreBoot once more, to try to figure out why it takes so long. Thanks Marc

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[PATCH] coreboot: Try to auto-detect if the CBFS anchor pointer is a relative pointer
by Kevin O'Connor 09 Jul '15

09 Jul '15

If CONFIG_CBFS_LOCATION is set to a non-zero value then it means the CBFS flash is not at the very end of memory. In this case, it's unclear if the anchor pointer is an absolute pointer or if it is relative to CONFIG_CBFS_LOCATION. Some devices have been using absolute pointers, but it appears some devices are now using relative pointers there. Since the anchor pointer almost always points to a structure in the last 64K of the rom, it should be possible to auto-detect if the pointer is relative or not. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- This parallels a commit in the Google seabios repo (commit a7539dcb). However, that patch unconditionally changes to relative pointers - which would defintely not work if the CBFS was setup with absolute pointers. I'm hoping auto-detecting absolute vs relative will work in practice, and therefore the same code can be used on both new and old devices. --- src/fw/coreboot.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/fw/coreboot.c b/src/fw/coreboot.c index 8fd8449..e0f997d 100644 --- a/src/fw/coreboot.c +++ b/src/fw/coreboot.c @@ -421,6 +421,9 @@ coreboot_cbfs_init(void) return; struct cbfs_header *hdr = *(void **)(CONFIG_CBFS_LOCATION - 4); + if (CBFS_HEADER_MAGIC && (u32)hdr > CONFIG_CBFS_LOCATION) + // Looks like the pointer is relative to CONFIG_CBFS_LOCATION + hdr = (void*)hdr + CONFIG_CBFS_LOCATION; if (hdr->magic != cpu_to_be32(CBFS_HEADER_MAGIC)) { dprintf(1, "Unable to find CBFS (ptr=%p; got %x not %x)\n" , hdr, hdr->magic, cpu_to_be32(CBFS_HEADER_MAGIC)); -- 1.9.3

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Re: [SeaBIOS] Reducing SeaBIOS kernel entry time
by Kevin O'Connor 08 Jul '15

08 Jul '15

On Fri, Jul 03, 2015 at 03:12:14PM +0100, Stefan Hajnoczi wrote: > On Fri, Jul 3, 2015 at 2:13 PM, Kevin O'Connor <kevin(a)koconnor.net> wrote: > > I took a look a month or so ago: > > > > http://article.gmane.org/gmane.comp.emulators.kvm.devel/136207 > > > > Last test I ran I had SeaBIOS down to 16ms (not including the time to > > deploy or jump to the linux kernel). More reductions are also > > possible - the above was just with Kconfig settings. > > > > Let me know if you want more info on how I did that. > > That sounds interesting. Do you have a .config or git branch? See attached SeaBIOS config. I profiled the results following the directions at: http://www.seabios.org/Debugging#Timing_debug_messages The QEMU command line I used is: qemu-system-x86_64 -k en-us -snapshot -L test -chardev pipe,path=qemudebugpipe,id=seabios -device isa-debugcon,iobase=0x402,chardev=seabios -enable-kvm To get to these low start times (~16ms on my old AMD system) I disabled debug messages in SeaBIOS. (The debug messages themselves take a few milliseconds.) So, in order to do profiling via the debug output, I manually added two small debug port writes (see seabios patch below). I end up seeing results like this on my machine: ======= Sat Jul 4 13:36:25 2015 (adjust=0.0us) 00.000: 1 00.014: 2 00.015: 2 As discussed in the thread linked to above, these numbers could be improved further by making code changes (to seabios and/or qemu). These tests were just with minimal seabios Kconfig changes. Finally, note that this SeaBIOS setup is so stripped down that it can't actually boot an OS. The goal of the experiment was to time SeaBIOS to the point where one could add an optimized Linux deployment scheme to SeaBIOS - such as Paolo's idea of putting a kernel in a "flash" based memory mapped region. Thus, the seabios numbers above would also need to include the cost of the kernel deployment and launching, as well as the qemu startup costs, in order for them to be truly meaningful. -Kevin --- a/src/boot.c +++ b/src/boot.c @@ -714,6 +714,7 @@ do_boot(int seq_nr) if (seq_nr >= BEVCount) boot_fail(); + outb('2', 0x402); outb('\n', 0x402); // Boot the given BEV type. struct bev_s *ie = &BEV[seq_nr]; switch (ie->type) { diff --git a/src/post.c b/src/post.c index 6157b50..9fd5f8f 100644 --- a/src/post.c +++ b/src/post.c @@ -329,6 +329,7 @@ handle_post(void) { if (!CONFIG_QEMU && !CONFIG_COREBOOT) return; + outb('1', 0x402); outb('\n', 0x402); serial_debug_preinit(); debug_banner();

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SeaBIOS July 2015