November 2014 - SeaBIOS - mail.coreboot.org

[PATCH] pciinit: Fix build warning in mch_pci_slot_get_irq()

by Kevin O'Connor

Some old versions of gcc warn that 'irq might be used uninitialized'. Replace the switch statement with an if statement to suppress the warning. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/fw/pciinit.c | 23 +++++++---------------- 1 file changed, 7 insertions(+), 16 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index fd5dfb9..3e6308a 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -115,27 +115,18 @@ static int piix_pci_slot_get_irq(struct pci_device *pci, int pin) static int mch_pci_slot_get_irq(struct pci_device *pci, int pin) { - int irq, slot, pin_addend = 0; - + int pin_addend = 0; while (pci->parent != NULL) { pin_addend += pci_bdf_to_dev(pci->bdf); pci = pci->parent; } - slot = pci_bdf_to_dev(pci->bdf); - - switch (slot) { - /* Slots 0-24 rotate slot:pin mapping similar to piix above, but - with a different starting index - see q35-acpi-dsdt.dsl */ - case 0 ... 24: - irq = pci_irqs[(pin - 1 + pin_addend + slot) & 3]; - break; + u8 slot = pci_bdf_to_dev(pci->bdf); + if (slot <= 24) + /* Slots 0-24 rotate slot:pin mapping similar to piix above, but + with a different starting index - see q35-acpi-dsdt.dsl */ + return pci_irqs[(pin - 1 + pin_addend + slot) & 3]; /* Slots 25-31 all use LNKA mapping (or LNKE, but A:D = E:H) */ - case 25 ... 31: - irq = pci_irqs[(pin - 1 + pin_addend) & 3]; - break; - } - - return irq; + return pci_irqs[(pin - 1 + pin_addend) & 3]; } /* PIIX3/PIIX4 PCI to ISA bridge */ -- 1.9.3

5 years, 2 months

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[PATCH] Fix build issue on gcc34

by Kevin O'Connor

Older versions of gcc may not inline on_extra_stack() and thus cause a link error when compiling in 32bit segmented mode. Test for MODE16 explicitly in stack_hop_back() to prevent the problem. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/stacks.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stacks.c b/src/stacks.c index 6f40cbe..0c033d1 100644 --- a/src/stacks.c +++ b/src/stacks.c @@ -430,7 +430,7 @@ stack_hop_back(u32 eax, u32 edx, void *func) { if (!MODESEGMENT) return call16_back(eax, edx, func); - if (!on_extra_stack()) + if (!MODE16 || !on_extra_stack()) return ((u32 (*)(u32, u32))func)(eax, edx); ASSERT16(); u16 bkup_ss; -- 1.9.3

5 years, 2 months

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new tag request for seabios

by Pandey, Sunil K

Hello, I'm looking for a fix in http://code.coreboot.org/p/seabios/source/tree/master/scripts/layoutrom.py file. Apparently the fix is already in the master, but it's hard for me to use directly from master. Currently all existing tags are old and doesn't reflect latest layoutrom.py changes. Can you please create a new tag from master so that I can use it in my project? I'm trying to compile seabios code with Intel compiler, but it keep failing because of layoutrom.py file __func__ check. Thanks, Sunil Pandey

5 years, 2 months

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[PATCH] Use an aligned stack offset when entering on the extra stack

by Kevin O'Connor

The size of 'struct bregs' is not evenly divisible by four and where the assembler placed a 'struct bregs' on the extra stack as part of entering into the C functions it caused the C functions to run with a non-aligned stack. It's technically not correct to use an unaligned stack and it is certainly less efficient. This patch avoids using BREGS_size (the sizeof struct bregs) and instead introduces PUSHBREGS_size (the size of the general purpose registers in struct bregs) in the assembler. Where the code actually did use the %cs:%ip and flags, an extra 8 (instead of 6) bytes are added to maintain a sane alignment. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/asm-offsets.c | 1 - src/entryfuncs.S | 2 ++ src/romlayout.S | 24 ++++++++++++------------ vgasrc/vgaentry.S | 20 ++++++++++---------- 4 files changed, 24 insertions(+), 23 deletions(-) diff --git a/src/asm-offsets.c b/src/asm-offsets.c index 576bf34..b98f3b5 100644 --- a/src/asm-offsets.c +++ b/src/asm-offsets.c @@ -20,5 +20,4 @@ void foo(void) OFFSET(BREGS_edi, bregs, edi); OFFSET(BREGS_flags, bregs, flags); OFFSET(BREGS_code, bregs, code); - DEFINE(BREGS_size, sizeof(struct bregs)); } diff --git a/src/entryfuncs.S b/src/entryfuncs.S index cc1f433..7368bb6 100644 --- a/src/entryfuncs.S +++ b/src/entryfuncs.S @@ -9,6 +9,8 @@ * Macros for save and restore of 'struct bregs' registers ****************************************************************/ +#define PUSHBREGS_size 32 + // Save registers (matches struct bregs) to stack .macro PUSHBREGS pushl %eax diff --git a/src/romlayout.S b/src/romlayout.S index 7a5df0e..c1751e1 100644 --- a/src/romlayout.S +++ b/src/romlayout.S @@ -257,7 +257,7 @@ entry_pmm: movw %cx, %ds shll $4, %ecx movl $_cfunc32flat_handle_pmm, %eax // Setup: call32(handle_pmm, args, -1) - leal BREGS_size-6+12(%esp, %ecx), %edx // %edx points to start of args + leal PUSHBREGS_size+12(%esp, %ecx), %edx // %edx points to start of args movl $-1, %ecx calll call32 movw %ax, BREGS_eax(%esp) // Modify %ax:%dx to return %eax @@ -284,7 +284,7 @@ entry_pnp_real: PUSHBREGS movw %ss, %cx // Move %ss to %ds movw %cx, %ds - leal BREGS_size-6+12(%esp), %eax // %eax points to start of u16 args + leal PUSHBREGS_size+12(%esp), %eax // %eax points to start of u16 args calll handle_pnp movw %ax, BREGS_eax(%esp) // Modify %eax to return %ax POPBREGS @@ -433,11 +433,11 @@ irqentry_extrastack: movl $_zonelow_seg, %eax movl %eax, %ds movl StackPos, %eax - subl $BREGS_size+8, %eax + subl $PUSHBREGS_size+8, %eax SAVEBREGS_POP_DSEAX popl %ecx - movl %esp, BREGS_size(%eax) - movw %ss, BREGS_size+4(%eax) + movl %esp, PUSHBREGS_size(%eax) + movw %ss, PUSHBREGS_size+4(%eax) movw %ds, %dx // Setup %ss/%esp and call function movw %dx, %ss @@ -445,8 +445,8 @@ irqentry_extrastack: calll *%ecx movl %esp, %eax // Restore registers and return - movw BREGS_size+4(%eax), %ss - movl BREGS_size(%eax), %esp + movw PUSHBREGS_size+4(%eax), %ss + movl PUSHBREGS_size(%eax), %esp RESTOREBREGS_DSEAX iretw @@ -460,11 +460,11 @@ irqentry_arg_extrastack: movl $_zonelow_seg, %eax movl %eax, %ds movl StackPos, %eax - subl $BREGS_size+8, %eax + subl $PUSHBREGS_size+16, %eax SAVEBREGS_POP_DSEAX // Save registers on extra stack popl %ecx - movl %esp, BREGS_size+0(%eax) - movw %ss, BREGS_size+4(%eax) + movl %esp, PUSHBREGS_size+8(%eax) + movw %ss, PUSHBREGS_size+12(%eax) popl BREGS_code(%eax) popw BREGS_flags(%eax) @@ -474,8 +474,8 @@ irqentry_arg_extrastack: calll *%ecx movl %esp, %eax // Restore registers and return - movw BREGS_size+4(%eax), %ss - movl BREGS_size+0(%eax), %esp + movw PUSHBREGS_size+12(%eax), %ss + movl PUSHBREGS_size+8(%eax), %esp popl %edx popw %dx pushw BREGS_flags(%eax) diff --git a/vgasrc/vgaentry.S b/vgasrc/vgaentry.S index c05502d..f9cf656 100644 --- a/vgasrc/vgaentry.S +++ b/vgasrc/vgaentry.S @@ -112,10 +112,10 @@ entry_10_extrastack: pushw %ds // Set %ds:%eax to space on ExtraStack pushl %eax movw %cs:ExtraStackSeg, %ds - movl $(CONFIG_VGA_EXTRA_STACK_SIZE-BREGS_size-8), %eax + movl $(CONFIG_VGA_EXTRA_STACK_SIZE-PUSHBREGS_size-16), %eax SAVEBREGS_POP_DSEAX // Save registers on extra stack - movl %esp, BREGS_size+0(%eax) - movw %ss, BREGS_size+4(%eax) + movl %esp, PUSHBREGS_size+8(%eax) + movw %ss, PUSHBREGS_size+12(%eax) popl BREGS_code(%eax) popw BREGS_flags(%eax) @@ -125,8 +125,8 @@ entry_10_extrastack: VGA_CALLL handle_10 movl %esp, %eax // Restore registers and return - movw BREGS_size+4(%eax), %ss - movl BREGS_size+0(%eax), %esp + movw PUSHBREGS_size+12(%eax), %ss + movl PUSHBREGS_size+8(%eax), %esp popl %edx popw %dx pushw BREGS_flags(%eax) @@ -148,10 +148,10 @@ entry_timer_hook_extrastack: pushw %ds // Set %ds:%eax to space on ExtraStack pushl %eax movw %cs:ExtraStackSeg, %ds - movl $(CONFIG_VGA_EXTRA_STACK_SIZE-BREGS_size-8), %eax + movl $(CONFIG_VGA_EXTRA_STACK_SIZE-PUSHBREGS_size-8), %eax SAVEBREGS_POP_DSEAX - movl %esp, BREGS_size(%eax) - movw %ss, BREGS_size+4(%eax) + movl %esp, PUSHBREGS_size(%eax) + movw %ss, PUSHBREGS_size+4(%eax) movw %ds, %dx // Setup %ss/%esp and call function movw %dx, %ss @@ -159,7 +159,7 @@ entry_timer_hook_extrastack: calll handle_timer_hook movl %esp, %eax // Restore registers and return - movw BREGS_size+4(%eax), %ss - movl BREGS_size(%eax), %esp + movw PUSHBREGS_size+4(%eax), %ss + movl PUSHBREGS_size(%eax), %esp RESTOREBREGS_DSEAX ljmpw *%cs:Timer_Hook_Resume -- 1.9.3

5 years, 2 months

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[PATCH 0/2] cbvga text emulation and software cursor

by Kevin O'Connor

This is a resend of two previous patches that improve the text emulation of the "coreboot native vga" SeaVGABIOS support. The main difference in this version is that the support requires both a compile time define (CONFIG_VGA_EMULATE_TEXT) as well as runtime enablement. The net effect of this is that the code wont try to blink the cursor if a bootloader explicitly switches into graphics mode. This is also available at: https://github.com/KevinOConnor/seabios/tree/testing -Kevin Kevin O'Connor (2): vgabios: Support emulating text mode attributes while in graphics mode vgabios: Add software cursor capability vgasrc/Kconfig | 6 ++++ vgasrc/cbvga.c | 10 +++++-- vgasrc/vbe.c | 5 ++-- vgasrc/vgabios.c | 13 ++++++-- vgasrc/vgabios.h | 14 ++++++++- vgasrc/vgaentry.S | 30 +++++++++++++++++++ vgasrc/vgafb.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++++-- vgasrc/vgainit.c | 34 +++++++++++++++++++++ 8 files changed, 188 insertions(+), 13 deletions(-) -- 1.9.3

5 years, 2 months

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Re: [SeaBIOS] [PATCH 1/4] xhci: Update the times for usb command timeouts.

by Kevin O'Connor

On Sun, Jun 22, 2014 at 05:54:17PM +0200, Idwer Vollering wrote: > > So, this looks different from Matt's report. What appears to be > > happening in the above is that the device shows up originally as a > > high speed device (see "[High]" above). However, when the set_address > > command is sent to it, it appears that the device effectively > > disconnects and then reconnects as a super speed device (see "change > > port #2" and "change port #4" above - port 2==port 4 - see ("offset 1" > > / "offset 3" above)). > > > > You can try increasing the xchi_event_wait timeout which fixes Matt's > > issue, but I think we tried this on your hardware before with no luck. > > Indeed, changing 1000 to 5000 or USB_TIME_COMMAND in > src/hw/usb-xhci.c:501 didn't matter. Can you retry with the patch series I just posted? It's also at: https://github.com/KevinOConnor/seabios/tree/testing It may help with this device. -Kevin

5 years, 2 months

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[PATCH] megasas: read addional PCI I/O bar

by Hannes Reinecke

Some newer cards have the I/O bar at BAR 0, so we need to check that, too, if we cannot get an address for BAR 2. Without this patch the new 'megasas-gen2' emulation in qemu is not detected. Signed-off-by: Hannes Reinecke <hare(a)suse.de> --- src/megasas.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/megasas.c b/src/megasas.c index f4eeba0..167fc32 100644 --- a/src/megasas.c +++ b/src/megasas.c @@ -353,6 +353,10 @@ init_megasas(struct pci_device *pci) u32 iobase = pci_config_readl(pci->bdf, PCI_BASE_ADDRESS_2) & PCI_BASE_ADDRESS_IO_MASK; + if (!iobase) + iobase = pci_config_readl(pci->bdf, PCI_BASE_ADDRESS_0) + & PCI_BASE_ADDRESS_IO_MASK; + dprintf(1, "found MegaRAID SAS at %02x:%02x.%x, io @ %x\n", pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf), iobase); -- 1.8.4.5

5 years, 2 months

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Re: [SeaBIOS] how sea bios set VGA bar address?

by Gerd Hoffmann

Hi, > so i wonder where in source code of seabios calculate PCI BAR address? src/fw/pciinit.c initializes all pci devices and assigns addresses to the bars. bars are sorted by size for best packing, so the addresses they end up depends on the size and also which other devices are present. > and also, i wonder why qemu's vga pci bar address is different from > virtualbox's vga pci bar address though > both of devices are classified as same 'vga' device(class id number : > 0x30) There is no need for it to have a fixed address. > (in Virtualbox, VGA PIC BAR ADDRESS always starts from e0000000 and it > is VBE standard) I doubt it is VBE standard. cheers, Gerd

5 years, 2 months

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how sea bios set VGA bar address?

by 유준봉

Hi SeaBios!! I'm qemu user and i want to modify qemu vga device to start BAR Address from 0xE0000000 As you know, Qemu uses SEABIOS as system bios but when i look into Qemu Debug console, right using command "info pci" then it just shows value for PCI BAR address : 0xf0000000 and it seems that VGA PCI BAR address change by the size of VGA RAM(VRAM) size (if VRAM is 128MB, BAR address = 0xf0000000, if it is 256MB, BAR address = 0xe0000000) It seems during booting time seabios calculate VGA PCI BAR address as 0xf000000 when its VRAM size is 128MB. so i wonder where in source code of seabios calculate PCI BAR address? and also, i wonder why qemu's vga pci bar address is different from virtualbox's vga pci bar address though both of devices are classified as same 'vga' device(class id number : 0x30) (in Virtualbox, VGA PIC BAR ADDRESS always starts from e0000000 and it is VBE standard)

5 years, 2 months

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[PATCH] edd: Fix buffer size field for EDD 3.x

by Kevin Wolf

The full 66 bytes of the EDD 3.x buffer were already filled, but the size field wasn't updated so that we would return that only the first 30 bytes of it are valid (like for 2.x). Fix the size field. Signed-off-by: Kevin Wolf <kwolf(a)redhat.com> --- src/block.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/block.c b/src/block.c index 7892be5..46afca0 100644 --- a/src/block.c +++ b/src/block.c @@ -339,6 +339,7 @@ fill_generic_edd(u16 seg, struct int13dpt_s *param_far, struct drive_s *drive_gf return DISK_RET_SUCCESS; // EDD 3.x + SET_FARVAR(seg, param_far->size, 66); SET_FARVAR(seg, param_far->key, 0xbedd); SET_FARVAR(seg, param_far->dpi_length, t13 ? 44 : 36); SET_FARVAR(seg, param_far->reserved1, 0); -- 1.8.3.1

5 years, 2 months

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SeaBIOS November 2014