SeaBIOS January 2013

seabios@seabios.org

27 participants
47 discussions

[PATCH 0/2] q35: Fix seabios IRQ mapping and setup
by Alex Williamson 23 Jan '13

23 Jan '13

This seems like the easier approach from my RFC yesterday. Instead of trying to make ich9 interrupt mapping look like piix, just add a new slot-to-irq function so we can not only get bus 0 devices, but root ports fixed as well. The change from piix mapping is subtle, but required for device assignment. Additionally, fix the PIRQn initialization value, enabling the interrupts for boot ROMs. Thanks, Alex --- Alex Williamson (2): q35: Enable all PIRQn IRQs at startup q35: Add new PCI slot to irq routing function src/pciinit.c | 41 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 36 insertions(+), 5 deletions(-)

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[RFC PATCH 0/2] Q35/ICH9 interrupt routing
by Alex Williamson 21 Jan '13

21 Jan '13

I was trying to revive the patch to add Qemu INTx routing support for Q35 and stumbled on some rather broken interrupt routing problems. Sadly a seabios release claiming Q35 support snuck out already, but I'd like to at least discuss these before Qemu 1.4 even though they may not get fixed for that release either. ICH9 adds 4 more PCI interrupt routing registers, so in addition to the previous PIRQ[A:D], we now also have PIRQ[E:H]. AIUI, each pin can operate in either PIC or APIC mode based on whether the IRQEN bit of each register is clear or set respectively. In PIC mode bits 3:0 of the PIRQn register identifiy the ISA compatible interrupt to trigger. In APIC mode each PIRQn is statically mapped to an APIC pin, where PIRQA->16, PIRQB->17, ..., PIRQH->23. The first problem we encounter is that the system boots into PIC mode but we're programming the PIRQn registers into APIC mode. After fixing that, we quickly notice that seabios has a single function for programming PCI interrupt line registers based on the PIIX mapping of PIRQn registers. A comment in the Qemu source indicates the slot:pin to PIRQn mapping is arbitrary so long as Qemu and ACPI match, disregarding that boot ROMs may also use interrupts and have no ACPI support. Solutions to this are either to create an ICH9 specific mapping function or to adjust slot:pin mappings to match PIIX. I've done the latter here, but it's incomplete as slots 25-31 have directly programmable mappings. I'm looking for comments on how to proceed. Do we want to try to meld ICH9 to be more PIIX compatible or do we want to do our own thing. I suspect there are still a number of holes in ICH9 irq programming no matter which path we take and these in particular are likely to be challenging for migration compatibility. Thanks, Alex --- Alex Williamson (2): q35: Fix PIC-mode interrupt setup q35: Fix ACPI _PRT routing to match PIIX src/pciinit.c | 6 +-- src/q35-acpi-dsdt.dsl | 100 +++++++++++++++++++++++++------------------------ 2 files changed, 52 insertions(+), 54 deletions(-)

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[PATCH 0/3][RFC] More post init order reorg
by Kevin O'Connor 21 Jan '13

21 Jan '13

Additional changes intended to clarify the early initialization ("preinit") order. -Kevin Kevin O'Connor (3): POST: Reorganize post entry and "preinit" functions. POST: Move cpu caching and dma setup to platform_hardware_setup(). POST: Merge platform preinit() calls. src/coreboot.c | 6 +-- src/paravirt.c | 10 +++- src/paravirt.h | 3 +- src/post.c | 152 +++++++++++++++++++++++++++++++------------------------- src/resume.c | 4 +- src/romlayout.S | 2 +- src/util.h | 2 +- src/xen.c | 57 +++++++++++---------- src/xen.h | 1 - 9 files changed, 127 insertions(+), 110 deletions(-) -- 1.7.11.7

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[PATCH 0/3][RFC] POST changes to help with CSM
by Kevin O'Connor 21 Jan '13

21 Jan '13

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Re: [SeaBIOS] [PATCH RFC] Quite hacky patch to get USB ehci working on bare metal.
by Nils 21 Jan '13

21 Jan '13

Hello Christian, Op dinsdag 15-01-2013 om 08:16 uur [tijdzone +0100], schreef Christian Gmeiner: > This RFC version works better... with the old one every 3rd boot some > ehci bulk transfers timed out. Verified > with my ellisys usb explorer. I will spend 1-3 hours today to get some > sort of OS booting via USB. > > > > > BTW, the current usb-ehci code does work on "bare metal" on several > > different boards. What board(s) did this help on? > > This patch helps on a lx800 platform with a cs5536. As this patch is > RFC I am quite happy if some USB > expert can share his/her thoughts. > -- > Christian Gmeiner, MSc Nice to see that you are making progress. I would like to test your patch but unfortunately i don`t have a geode board at the moment. I hope to get some back in a few weeks. I am curious if you see the same problems as i had with Seabios USB-ohci hid. My USB keyboard and mouse did not work. Greetings, Nils.

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[PATCH] POST: Move QEMU specific ramsize and BIOS table setup to paravirt.c.
by Kevin O'Connor 21 Jan '13

21 Jan '13

Don't clutter post.c with the gory details of QEMU memory sizing and BIOS table creation. Instead, move that code to paravirt.c. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/paravirt.c | 56 ++++++++++++++++++++++++++++++++++++++++++ src/paravirt.h | 2 ++ src/post.c | 77 ++++++++-------------------------------------------------- 3 files changed, 68 insertions(+), 67 deletions(-) diff --git a/src/paravirt.c b/src/paravirt.c index f180261..9022186 100644 --- a/src/paravirt.c +++ b/src/paravirt.c @@ -13,9 +13,65 @@ #include "ioport.h" // outw #include "paravirt.h" // qemu_cfg_preinit #include "smbios.h" // struct smbios_structure_header +#include "memmap.h" // add_e820 +#include "cmos.h" // CMOS_* +#include "acpi.h" // acpi_setup +#include "mptable.h" // mptable_setup +#include "pci.h" // create_pirtable int qemu_cfg_present; +void +qemu_ramsize_preinit(void) +{ + // On emulators, get memory size from nvram. + u32 rs = ((inb_cmos(CMOS_MEM_EXTMEM2_LOW) << 16) + | (inb_cmos(CMOS_MEM_EXTMEM2_HIGH) << 24)); + if (rs) + rs += 16 * 1024 * 1024; + else + rs = (((inb_cmos(CMOS_MEM_EXTMEM_LOW) << 10) + | (inb_cmos(CMOS_MEM_EXTMEM_HIGH) << 18)) + + 1 * 1024 * 1024); + RamSize = rs; + add_e820(0, rs, E820_RAM); + + // Check for memory over 4Gig + u64 high = ((inb_cmos(CMOS_MEM_HIGHMEM_LOW) << 16) + | ((u32)inb_cmos(CMOS_MEM_HIGHMEM_MID) << 24) + | ((u64)inb_cmos(CMOS_MEM_HIGHMEM_HIGH) << 32)); + RamSizeOver4G = high; + add_e820(0x100000000ull, high, E820_RAM); + + /* reserve 256KB BIOS area at the end of 4 GB */ + add_e820(0xfffc0000, 256*1024, E820_RESERVED); + + u32 count = qemu_cfg_e820_entries(); + if (count) { + struct e820_reservation entry; + int i; + + for (i = 0; i < count; i++) { + qemu_cfg_e820_load_next(&entry); + add_e820(entry.address, entry.length, entry.type); + } + } else if (kvm_para_available()) { + // Backwards compatibility - provide hard coded range. + // 4 pages before the bios, 3 pages for vmx tss pages, the + // other page for EPT real mode pagetable + add_e820(0xfffbc000, 4*4096, E820_RESERVED); + } +} + +void +qemu_biostable_setup(void) +{ + pirtable_setup(); + mptable_setup(); + smbios_setup(); + acpi_setup(); +} + static void qemu_cfg_select(u16 f) { diff --git a/src/paravirt.h b/src/paravirt.h index 765a6c1..4f2d5b8 100644 --- a/src/paravirt.h +++ b/src/paravirt.h @@ -43,6 +43,8 @@ static inline int kvm_para_available(void) extern int qemu_cfg_present; +void qemu_ramsize_preinit(void); +void qemu_biostable_setup(void); void qemu_cfg_preinit(void); int qemu_cfg_show_boot_menu(void); void qemu_cfg_get_uuid(u8 *uuid); diff --git a/src/post.c b/src/post.c index dbf4944..33b51b7 100644 --- a/src/post.c +++ b/src/post.c @@ -15,13 +15,9 @@ #include "ahci.h" // ahci_setup #include "memmap.h" // add_e820 #include "pic.h" // pic_setup -#include "pci.h" // create_pirtable -#include "acpi.h" // acpi_bios_init #include "bregs.h" // struct bregs -#include "mptable.h" // mptable_init #include "boot.h" // IPL #include "usb.h" // usb_setup -#include "smbios.h" // smbios_init #include "paravirt.h" // qemu_cfg_port_probe #include "xen.h" // xen_preinit #include "ps2port.h" // ps2port_setup @@ -40,33 +36,12 @@ static void ramsize_preinit(void) { dprintf(3, "Find memory size\n"); - if (CONFIG_COREBOOT) { + if (CONFIG_COREBOOT) coreboot_preinit(); - } else if (usingXen()) { + else if (usingXen()) xen_ramsize_preinit(); - } else { - // On emulators, get memory size from nvram. - u32 rs = ((inb_cmos(CMOS_MEM_EXTMEM2_LOW) << 16) - | (inb_cmos(CMOS_MEM_EXTMEM2_HIGH) << 24)); - if (rs) - rs += 16 * 1024 * 1024; - else - rs = (((inb_cmos(CMOS_MEM_EXTMEM_LOW) << 10) - | (inb_cmos(CMOS_MEM_EXTMEM_HIGH) << 18)) - + 1 * 1024 * 1024); - RamSize = rs; - add_e820(0, rs, E820_RAM); - - // Check for memory over 4Gig - u64 high = ((inb_cmos(CMOS_MEM_HIGHMEM_LOW) << 16) - | ((u32)inb_cmos(CMOS_MEM_HIGHMEM_MID) << 24) - | ((u64)inb_cmos(CMOS_MEM_HIGHMEM_HIGH) << 32)); - RamSizeOver4G = high; - add_e820(0x100000000ull, high, E820_RAM); - - /* reserve 256KB BIOS area at the end of 4 GB */ - add_e820(0xfffc0000, 256*1024, E820_RESERVED); - } + else + qemu_ramsize_preinit(); // Don't declare any memory between 0xa0000 and 0x100000 add_e820(BUILD_LOWRAM_END, BUILD_BIOS_ADDR-BUILD_LOWRAM_END, E820_HOLE); @@ -74,22 +49,6 @@ ramsize_preinit(void) // Mark known areas as reserved. add_e820(BUILD_BIOS_ADDR, BUILD_BIOS_SIZE, E820_RESERVED); - u32 count = qemu_cfg_e820_entries(); - if (count) { - struct e820_reservation entry; - int i; - - for (i = 0; i < count; i++) { - qemu_cfg_e820_load_next(&entry); - add_e820(entry.address, entry.length, entry.type); - } - } else if (kvm_para_available()) { - // Backwards compatibility - provide hard coded range. - // 4 pages before the bios, 3 pages for vmx tss pages, the - // other page for EPT real mode pagetable - add_e820(0xfffbc000, 4*4096, E820_RESERVED); - } - dprintf(1, "Ram Size=0x%08x (0x%016llx high)\n", RamSize, RamSizeOver4G); } @@ -204,27 +163,6 @@ device_hardware_setup(void) } static void -biostable_setup(void) -{ - if (CONFIG_COREBOOT) { - coreboot_biostable_setup(); - return; - } - if (usingXen()) { - xen_biostable_setup(); - return; - } - - pirtable_setup(); - - mptable_setup(); - - smbios_setup(); - - acpi_setup(); -} - -static void platform_hardware_setup(void) { // Init base pc hardware. @@ -249,7 +187,12 @@ platform_hardware_setup(void) smp_setup(); // Setup external BIOS interface tables - biostable_setup(); + if (CONFIG_COREBOOT) + coreboot_biostable_setup(); + else if (usingXen()) + xen_biostable_setup(); + else + qemu_biostable_setup(); } static void -- 1.7.11.7

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[PATCH] pmm: Use 'struct segoff_s' in pmm header.
by Kevin O'Connor 20 Jan '13

20 Jan '13

Minor cleanup - use 'struct segoff_s' instead of a manual segment/offset pair. Also, while at it, define the header signature at compile time instead of at run-time. (Defining at run-time is a hold over from when variable changes were persistent across soft-reboots.) Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/pmm.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/src/pmm.c b/src/pmm.c index 653c9e2..1657c10 100644 --- a/src/pmm.c +++ b/src/pmm.c @@ -416,8 +416,7 @@ struct pmmheader { u8 version; u8 length; u8 checksum; - u16 entry_offset; - u16 entry_seg; + struct segoff_s entry; u8 reserved[5]; } PACKED; @@ -427,9 +426,9 @@ extern struct pmmheader PMMHEADER; #if CONFIG_PMM struct pmmheader PMMHEADER __aligned(16) VAR16EXPORT = { + .signature = PMM_SIGNATURE, .version = 0x01, .length = sizeof(PMMHEADER), - .entry_seg = SEG_BIOS, }; #endif @@ -545,9 +544,6 @@ handle_pmm(u16 *args) return ret; } -// romlayout.S -extern void entry_pmm(void); - void pmm_setup(void) { @@ -556,8 +552,7 @@ pmm_setup(void) dprintf(3, "init PMM\n"); - PMMHEADER.signature = PMM_SIGNATURE; - PMMHEADER.entry_offset = (u32)entry_pmm - BUILD_BIOS_ADDR; + PMMHEADER.entry = FUNC16(entry_pmm); PMMHEADER.checksum -= checksum(&PMMHEADER, sizeof(PMMHEADER)); } @@ -570,5 +565,5 @@ pmm_finalize(void) dprintf(3, "finalize PMM\n"); PMMHEADER.signature = 0; - PMMHEADER.entry_offset = 0; + PMMHEADER.entry.segoff = 0; } -- 1.7.11.7

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[ANNOUNCE] SeaBIOS 1.7.2
by Kevin O'Connor 19 Jan '13

19 Jan '13

The 1.7.2 version of SeaBIOS has now been released. For more information on the release, please see: http://seabios.org/Releases New in this release: * Support for ICH9 host chipset ("q35") on emulators * Support for booting from LSI MegaRAID SAS controllers * Support for using the ACPI PM timer on emulators * Improved Geode VGA BIOS support. * Several bug fixes For information on obtaining SeaBIOS, please see: http://seabios.org/Download

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[WIP PATCH 3/3] Add initial CSM support
by David Woodhouse 18 Jan '13

18 Jan '13

Not particularly functional, but it's a start... Build with CONFIG_CSM enabled (and CONFIG_RELOCATE_INIT disabled) and drop the resulting bios.bin into OvmfPkg/Csm/Csm16/Csm16.bin in your EDK-II build tree, then build with 'build -D CSM_ENABLE'. You'll see it initialise SeaBIOS as a CSM as it's starting up, and then crash in a storm of what Qemu's debug log says is 'hardware INT=0x68'... which I suppose is what I have to debug next... Signed-off-by: David Woodhouse <David.Woodhouse(a)intel.com> --- Makefile | 2 +- src/Kconfig | 7 +++ src/csm.c | 142 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/post.c | 3 ++ src/romlayout.S | 7 +++ src/shadow.c | 6 +-- 6 files changed, 163 insertions(+), 4 deletions(-) create mode 100644 src/csm.c diff --git a/Makefile b/Makefile index f28d86c..cb8ecdf 100644 --- a/Makefile +++ b/Makefile @@ -13,7 +13,7 @@ SRCBOTH=misc.c stacks.c pmm.c output.c util.c block.c floppy.c ata.c mouse.c \ pnpbios.c pirtable.c vgahooks.c ramdisk.c pcibios.c blockcmd.c \ usb.c usb-uhci.c usb-ohci.c usb-ehci.c usb-hid.c usb-msc.c \ virtio-ring.c virtio-pci.c virtio-blk.c virtio-scsi.c apm.c ahci.c \ - usb-uas.c lsi-scsi.c esp-scsi.c megasas.c + usb-uas.c lsi-scsi.c esp-scsi.c megasas.c csm.c SRC16=$(SRCBOTH) system.c disk.c font.c SRC32FLAT=$(SRCBOTH) post.c shadow.c memmap.c coreboot.c boot.c \ acpi.c smm.c mptable.c smbios.c pciinit.c optionroms.c mtrr.c \ diff --git a/src/Kconfig b/src/Kconfig index 0b112ed..f35b0f5 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -27,6 +27,13 @@ endchoice help Configure to be used by xen hvmloader, for a HVM guest. + config CSM + bool "Build as Compatibilty Support Module for EFI BIOS" + default n + help + Configure to be used by EFI firmware as Compatibility Support + module (CSM) to provide legacy BIOS services. + config THREADS bool "Parallelize hardware init" default y diff --git a/src/csm.c b/src/csm.c new file mode 100644 index 0000000..7ff173b --- /dev/null +++ b/src/csm.c @@ -0,0 +1,142 @@ +// CSM table generation (for providing legacy BIOS support to EFI) +// +// Copyright © 2012 Intel Corporation +// +// This file may be distributed under the terms of the GNU LGPLv3 license. + +#include "config.h" // CONFIG_* +#include "csm.h" +#include "util.h" // checksum +#include "bregs.h" + + +#if CONFIG_CSM +extern void entry_csm16(void); +EFI_COMPATIBILITY16_TABLE csm_compat_table VAR16EXPORT __aligned(16) = { + .Signature = 0x24454649, + .TableChecksum = 0 /* Filled in by checkrom.py */, + .TableLength = sizeof(csm_compat_table), + .Compatibility16CallSegment = SEG_BIOS, + .Compatibility16CallOffset = 0 /* Filled in by checkrom.py */, + .OemIdStringPointer = (u32)"SeaBIOS", +}; +#endif + +extern void handle_post(void); +extern void _cfunc32flat_handle_csm16(struct bregs *); + +EFI_TO_COMPATIBILITY16_INIT_TABLE *csm_init_table; +EFI_TO_COMPATIBILITY16_BOOT_TABLE *csm_boot_table; + +/* Legacy16InitializeYourself */ +void handle_csm_0000(struct bregs *regs) +{ + dprintf(3, "Legacy16InitializeYourself table %04x:%04x\n", regs->es, + regs->bx); + + csm_init_table = MAKE_FLATPTR(regs->es, regs->bx); + + dprintf(3, "BiosLessThan1MB %08x\n", csm_init_table->BiosLessThan1MB); + dprintf(3, "HiPmmMemory %08x\n", csm_init_table->HiPmmMemory); + dprintf(3, "HiPmmMemorySize %08x\n", csm_init_table->HiPmmMemorySizeInBytes); + dprintf(3, "ReverseThunk %04x:%04x\n", csm_init_table->ReverseThunkCallSegment, + csm_init_table->ReverseThunkCallOffset); + dprintf(3, "NumE820Entries %08x\n", csm_init_table->NumberE820Entries); + dprintf(3, "OsMemoryAbove1M %08x\n", csm_init_table->OsMemoryAbove1Mb); + dprintf(3, "ThunkStart %08x\n", csm_init_table->ThunkStart); + dprintf(3, "ThunkSize %08x\n", csm_init_table->ThunkSizeInBytes); + dprintf(3, "LoPmmMemory %08x\n", csm_init_table->LowPmmMemory); + dprintf(3, "LoPmmMemorySize %08x\n", csm_init_table->LowPmmMemorySizeInBytes); + + handle_post(); + regs->ax = 0; +} + +/* Legacy16UpdateBbs */ +void handle_csm_0001(struct bregs *regs) +{ + dprintf(3, "Legacy16UpdateBbs table %04x:%04x\n", regs->es, regs->bx); + + csm_boot_table = MAKE_FLATPTR(regs->es, regs->bx); + dprintf(3, "MajorVersion %04x\n", csm_boot_table->MajorVersion); + dprintf(3, "MinorVersion %04x\n", csm_boot_table->MinorVersion); + dprintf(3, "AcpiTable %08x\n", csm_boot_table->AcpiTable); + dprintf(3, "SmbiosTable %08x\n", csm_boot_table->SmbiosTable); + dprintf(3, "SmbiosTableLength %08x\n", csm_boot_table->SmbiosTableLength); +// dprintf(3, "SioData %08x\n", csm_boot_table->SioData); + dprintf(3, "DevicePathType %04x\n", csm_boot_table->DevicePathType); + dprintf(3, "PciIrqMask %04x\n", csm_boot_table->PciIrqMask); + dprintf(3, "NumberE820Entries %08x\n", csm_boot_table->NumberE820Entries); +// dprintf(3, "HddInfo %08x\n", csm_boot_table->HddInfo); + dprintf(3, "NumberBbsEntries %08x\n", csm_boot_table->NumberBbsEntries); + dprintf(3, "BBsTable %08x\n", csm_boot_table->BbsTable); + dprintf(3, "SmmTable %08x\n", csm_boot_table->SmmTable); + dprintf(3, "OsMemoryAbove1Mb %08x\n", csm_boot_table->OsMemoryAbove1Mb); + dprintf(3, "UnconventionalDeviceTable %08x\n", csm_boot_table->UnconventionalDeviceTable); + + regs->ax = 0; +} + +/* Legacy16DispatchOprom */ +void handle_csm_0005(struct bregs *regs) +{ + EFI_DISPATCH_OPROM_TABLE *rom = MAKE_FLATPTR(regs->es, regs->bx); + + dprintf(3, "Legacy16DispatchOprom rom %p\n", rom); + + dprintf(3, "OpromSegment %04x\n", rom->OpromSegment); + dprintf(3, "RuntimeSegment %04x\n", rom->RuntimeSegment); + + /* FIXME: Actually do it! */ + + regs->ax = 0; +} + +/* Legacy16GetTableAddress */ +void handle_csm_0006(struct bregs *regs) +{ + u16 size = regs->cx; + u16 align = regs->dx; + u16 region = regs->bx; // (1 for F000 seg, 2 for E000 seg, 0 for either) + void *chunk; + + /* FIXME: I don't know if we can allocate in the E000 segment at all. */ + dprintf(3, "Legacy16GetTableAddress size %x align %x region %d\n", + size, align, region); + chunk = pmm_malloc(&ZoneFSeg, PMM_DEFAULT_HANDLE, size, align); + dprintf(3, "Legacy16GetTableAddress size %x align %x region %d yields %p\n", + size, align, region, chunk); + if (chunk) { + regs->ds = FLATPTR_TO_SEG(chunk); + regs->bx = FLATPTR_TO_OFFSET(chunk); + regs->ax = 0; + } else { + regs->ax = 1; + } +} + +void __VISIBLE +handle_csm16(struct bregs *regs) +{ + if (MODESEGMENT) { + void *flatptr = MAKE_FLATPTR(GET_SEG(SS), regs); + call32(_cfunc32flat_handle_csm16, (u32)flatptr, 0); + return; + } + dprintf(3, "handle_csm16 AX=%04x\n", regs->ax); + + switch(regs->ax) { + case 0000: handle_csm_0000(regs); break; + case 0001: handle_csm_0001(regs); break; +// case 0002: handle_csm_0002(regs); break; +// case 0003: handle_csm_0003(regs); break; +// case 0004: handle_csm_0004(regs); break; + case 0005: handle_csm_0005(regs); break; + case 0006: handle_csm_0006(regs); break; +// case 0007: handle_csm_0007(regs); break; +// case 0008: hamdle_csm_0008(regs); break; + default: regs->al = 1; + } + + dprintf(3, "handle_csm16 returning AX=%04x\n", regs->ax); +} diff --git a/src/post.c b/src/post.c index f3b56b8..dc07e8b 100644 --- a/src/post.c +++ b/src/post.c @@ -225,6 +225,9 @@ maininit(void) init_ivt(); init_bda(); + if (CONFIG_CSM) + return; + // Init base pc hardware. pic_setup(); timer_setup(); diff --git a/src/romlayout.S b/src/romlayout.S index 8125277..f1a276e 100644 --- a/src/romlayout.S +++ b/src/romlayout.S @@ -468,6 +468,13 @@ irqentryarg: DECL_IRQ_ENTRY hwpic1 DECL_IRQ_ENTRY hwpic2 +#if CONFIG_CSM + EXPORTFUNC entry_csm16 +entry_csm16: + ENTRY_ARG handle_csm16 + iretw +#endif + // int 18/19 are special - they reset stack and call into 32bit mode. DECLFUNC entry_19 entry_19: diff --git a/src/shadow.c b/src/shadow.c index a2195da..881d5a6 100644 --- a/src/shadow.c +++ b/src/shadow.c @@ -119,7 +119,7 @@ static const struct pci_device_id dram_controller_make_readonly_tbl[] = { void make_bios_writable(void) { - if (CONFIG_COREBOOT || usingXen()) + if (CONFIG_COREBOOT || CONFIG_CSM || usingXen()) return; dprintf(3, "enabling shadow ram\n"); @@ -148,7 +148,7 @@ make_bios_writable(void) void make_bios_readonly(void) { - if (CONFIG_COREBOOT || usingXen()) + if (CONFIG_COREBOOT || CONFIG_CSM || usingXen()) return; dprintf(3, "locking shadow ram\n"); @@ -161,7 +161,7 @@ make_bios_readonly(void) void qemu_prep_reset(void) { - if (CONFIG_COREBOOT) + if (CONFIG_COREBOOT || CONFIG_CSM ) return; // QEMU doesn't map 0xc0000-0xfffff back to the original rom on a // reset, so do that manually before invoking a hard reset. -- 1.8.0.2 -- dwmw2

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[PATCH 2/3] Complete and checksum EFI_COMPATIBILITY16_TABLE at build time
by David Woodhouse 17 Jan '13

17 Jan '13

GCC, for reasons unknown, will refuse to compile code such as extern int bar; uint16_t foo = &bar; The assembler would happily emit a R_386_16 relocation for this if asked nicely, and all would be well. But instead, GCC complains about the initialiser not being constant. So we tend to fill in 16-bit offsets at run-time, which is only moderately inefficient. But for the CSM table used by EFI, it doesn't work. We need the offset to be present in the *image*, before a line of our own code has been run. Likewise the checksum. This special-cases the table and entry point in checkrom.py rather than attempting to do something generic. I did have a functional generic implementation which could be invoked from csm.c along the lines of CHECKSUM(csm_compat_table, TableChecksum) ... and which would emit the required offsetof(typeof(\1), \2) into a special data section which was elided from the final build but parsed by 'objdump -s' and the location of the table to be checksummed was inferred from the name of the *variable* that got put into that special section... seriously, it's better just to special-case it. It was baroque enough just for the checksums, and filling in the entry point which required access to *two* symbols was probably going to involve emitting a *string* into that special build-data section. It had to die. So yes, we have hard-coded symbol names, and even magic numbers in the python script for table offsets etc., but that's because this is an ABI. It doesn't change, and neither do any of the other tables that we might now consider filling at build time just to avoid having to spend time on doing so at runtime. Signed-off-by: David Woodhouse <David.Woodhouse(a)intel.com> --- tools/checkrom.py | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/tools/checkrom.py b/tools/checkrom.py index 69d65e8..00a652a 100755 --- a/tools/checkrom.py +++ b/tools/checkrom.py @@ -8,6 +8,17 @@ import sys import layoutrom +def subst(data, offset, new): + return data[:offset] + new + data[offset + len(new):] + +def checksum(data, start, size, csum): + sumbyte = 0 + while size: + sumbyte = sumbyte + ord(data[start + size - 1]) + size = size - 1 + sumbyte = (0x100 - sumbyte) & 0xff + return subst(data, start+csum, chr(sumbyte)) + def main(): # Get args objinfo, rawfile, outfile = sys.argv[1:] @@ -45,6 +56,22 @@ def main(): datasize, expdatasize) sys.exit(1) + # Fix up CSM Compatibility16 table + if 'csm_compat_table' in symbols and 'entry_csm16' in symbols: + # Field offsets within EFI_COMPATIBILITY16_TABLE + ENTRY_FIELD_OFS = 14 # Compatibility16CallOffset (UINT16) + SIZE_FIELD_OFS = 5 # TableLength (UINT8) + CSUM_FIELD_OFS = 4 # TableChecksum (UINT8) + + tableofs = symbols['csm_compat_table'].offset - symbols['code32flat_start'].offset + entry_addr = symbols['entry_csm16'].offset - layoutrom.BUILD_BIOS_ADDR + byte1 = chr(entry_addr & 0xff) + byte2 = chr(entry_addr >> 8) + rawdata = subst(rawdata, tableofs+ENTRY_FIELD_OFS, byte1+byte2) + + tablesize = ord(rawdata[tableofs+SIZE_FIELD_OFS]) + rawdata = checksum(rawdata, tableofs, tablesize, CSUM_FIELD_OFS) + # Print statistics runtimesize = datasize if '_reloc_abs_start' in symbols: -- 1.8.0.2 -- dwmw2

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SeaBIOS January 2013