SeaBIOS March 2012

seabios@seabios.org

31 participants
85 discussions

[PATCH] scsi: do not send MODE SENSE except to QEMU disks

by Paolo Bonzini

This is the simplest way to avoid breaking boot on USB sticks that stall when asked for the MODE SENSE page 4. Some old sticks do not support the MODE SENSE command at all and just return a "medium may have changed" unit attention condition when SeaBIOS sends it! Reported-by: Dave Frodin <dave(a)camp.se-eng.com> Signed-off-by: Paolo Bonzini <pbonzini(a)redhat.com> --- src/blockcmd.c | 36 +++++++++++++++++++++++------------- 1 files changed, 23 insertions(+), 13 deletions(-) diff --git a/src/blockcmd.c b/src/blockcmd.c index 2769573..b4a1e37 100644 --- a/src/blockcmd.c +++ b/src/blockcmd.c @@ -139,19 +139,29 @@ scsi_init_drive(struct drive_s *drive, const char *s, int prio) dprintf(1, "%s blksize=%d sectors=%d\n" , s, drive->blksize, (unsigned)drive->sectors); - struct cdbres_mode_sense_geom geomdata; - ret = cdb_mode_sense_geom(&dop, &geomdata); - if (ret == 0) { - u32 cylinders; - cylinders = geomdata.cyl[0] << 16; - cylinders |= geomdata.cyl[1] << 8; - cylinders |= geomdata.cyl[2]; - if (cylinders && geomdata.heads && - drive->sectors <= 0xFFFFFFFFULL && - ((u32)drive->sectors % (geomdata.heads * cylinders) == 0)) { - drive->pchs.cylinders = cylinders; - drive->pchs.heads = geomdata.heads; - drive->pchs.spt = (u32)drive->sectors / (geomdata.heads * cylinders); + // We do not recover from USB stalls, so try to be safe and avoid + // sending the command if the (obsolete, but still provided by QEMU) + // fixed disk geometry page may not be supported. + // + // We could also send the command only to small disks (e.g. <504MiB) + // but some old USB keys only support a very small subset of SCSI which + // does not even include the MODE SENSE command! + // + if (! CONFIG_COREBOOT && memcmp(vendor, "QEMU ", 8) == 0) { + struct cdbres_mode_sense_geom geomdata; + ret = cdb_mode_sense_geom(&dop, &geomdata); + if (ret == 0) { + u32 cylinders; + cylinders = geomdata.cyl[0] << 16; + cylinders |= geomdata.cyl[1] << 8; + cylinders |= geomdata.cyl[2]; + if (cylinders && geomdata.heads && + drive->sectors <= 0xFFFFFFFFULL && + ((u32)drive->sectors % (geomdata.heads * cylinders) == 0)) { + drive->pchs.cylinders = cylinders; + drive->pchs.heads = geomdata.heads; + drive->pchs.spt = (u32)drive->sectors / (geomdata.heads * cylinders); + } } } -- 1.7.7.6

9 years, 1 month

Re: [SeaBIOS] vgabios testing

by Kevin O'Connor

On Mon, Mar 05, 2012 at 04:41:27PM +0000, Julian Pidancet wrote: > On Mon, Mar 5, 2012 at 4:21 PM, Kevin O'Connor <kevin(a)koconnor.net> wrote: > > On Mon, Mar 05, 2012 at 04:05:11PM +0000, Julian Pidancet wrote: > >> Replacing instructions and handling displacement is probably going to > >> be a huge pain. > > > > I don't think that will be an issue. One can tell gcc to generate > > assembler and then post-process that. The gcc created assembler is > > still label based so no positional issues should arise. > > > Yes you're right. Post-processing the intermediate assembly will > definitely be a huge win. I put together the below as a quick hack. It boots to DOS okay. I'm not sure the exact test case for x86emu and I didn't test that. It's just a quick hack, but it should highlight the idea. -Kevin diff --git a/Makefile b/Makefile index 5d834b7..6cba6d5 100644 --- a/Makefile +++ b/Makefile @@ -31,7 +31,7 @@ COMMONCFLAGS = -I$(OUT) -Os -MD -g \ -Wall -Wno-strict-aliasing -Wold-style-definition \ $(call cc-option,$(CC),-Wtype-limits,) \ -m32 -march=i386 -mregparm=3 -mpreferred-stack-boundary=2 \ - -mrtd -minline-all-stringops \ + -minline-all-stringops \ -freg-struct-return -ffreestanding -fno-delete-null-pointer-checks \ -ffunction-sections -fdata-sections -fno-common COMMONCFLAGS += $(call cc-option,$(CC),-nopie,) @@ -193,7 +193,12 @@ SRCVGA=src/output.c src/util.c src/pci.c \ CFLAGS16VGA = $(CFLAGS16INC) -Isrc -$(OUT)vgaccode16.o: $(OUT)autoconf.h ; $(call whole-compile, $(CFLAGS16VGA), $(SRCVGA),$@) +$(OUT)vgaccode16.raw.s: $(OUT)autoconf.h ; $(call whole-compile, $(CFLAGS16VGA) -S, $(SRCVGA),$@) + +$(OUT)vgaccode16.o: $(OUT)vgaccode16.raw.s + @echo " Fixup VGA rom assembler" + $(Q)$(PYTHON) ./tools/vgafixup.py $< $(OUT)vgaccode16.s + $(Q)as --32 src/code16gcc.s $(OUT)vgaccode16.s -o $@ $(OUT)vgaentry.o: vgaentry.S $(OUT)autoconf.h @echo " Compiling (16bit) $@" diff --git a/tools/vgafixup.py b/tools/vgafixup.py new file mode 100644 index 0000000..db37037 --- /dev/null +++ b/tools/vgafixup.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python +# Work around x86emu bugs by replacing problematic instructions. +# +# Copyright (C) 2012 Kevin O'Connor <kevin(a)koconnor.net> +# +# This file may be distributed under the terms of the GNU GPLv3 license. + +import sys + +def main(): + infilename, outfilename = sys.argv[1:] + infile = open(infilename, 'rb') + out = [] + for line in infile: + sline = line.strip() + if sline == 'ret': + out.append('retw $2\n') + elif sline == 'leave': + out.append('movl %ebp, %esp ; popl %ebp\n') + else: + out.append(line) + infile.close() + outfile = open(outfilename, 'wb') + outfile.write(''.join(out)) + outfile.close() + +if __name__ == '__main__': + main() diff --git a/vgasrc/clext.c b/vgasrc/clext.c index e5dce35..fc5459a 100644 --- a/vgasrc/clext.c +++ b/vgasrc/clext.c @@ -526,7 +526,7 @@ ASM16( "a0h_callback:" "cli\n" "hlt\n" - "retf"); + "lretw"); static void clext_1012a0(struct bregs *regs)

9 years, 1 month

vgabios testing

by Gerd Hoffmann

Hi, Did some more testing of the vgabios today, two issues popped up: (1) screen isn't cleared in some cases. Visible with grub1 in text mode. When it displays the menu a few stray chars are visible. Even more obvious it becomes when hitting 'c' then to get a prompt, then alot of the menu is still visible. (2) The Xorg Server has trouble, the VESA driver doesn't work. There are also some good news: linux kernel with vesafb active works fine, likewise winxp guests. cheers, Gerd [ 90.904] (II) Loading sub module "vbe" [ 90.904] (II) LoadModule: "vbe" [ 90.904] (II) Loading /usr/lib/xorg/modules/libvbe.so [ 90.905] (II) Module vbe: vendor="X.Org Foundation" [ 90.905] compiled for 1.10.4, module version = 1.1.0 [ 90.905] ABI class: X.Org Video Driver, version 10.0 [ 90.905] (II) Loading sub module "int10" [ 90.905] (II) LoadModule: "int10" [ 90.906] (II) Loading /usr/lib/xorg/modules/libint10.so [ 90.909] (II) Module int10: vendor="X.Org Foundation" [ 90.909] compiled for 1.10.4, module version = 1.0.0 [ 90.909] ABI class: X.Org Video Driver, version 10.0 [ 90.909] (II) VESA(0): initializing int10 [ 90.912] (II) VESA(0): Bad V_BIOS checksum [ 90.912] (II) VESA(0): Primary V_BIOS segment is: 0xc000 [ 97.832] Backtrace: [ 97.833] 0: Xorg (xorg_backtrace+0x3c) [0x80a408c] [ 97.833] 1: Xorg (0x8048000+0x60496) [0x80a8496] [ 97.833] 2: (vdso) (__kernel_rt_sigreturn+0x0) [0x2c040c] [ 97.837] 3: /usr/lib/xorg/modules/libint10.so (0x2ed000+0x47e2) [0x2f17e2] [ 97.837] 4: /usr/lib/xorg/modules/libint10.so (0x2ed000+0x343a) [0x2f043a] [ 97.837] 5: /usr/lib/xorg/modules/libint10.so (0x2ed000+0xe02e) [0x2fb02e] [ 97.837] 6: /usr/lib/xorg/modules/libint10.so (0x2ed000+0x13134) [0x300134] [ 97.837] 7: /usr/lib/xorg/modules/libint10.so (0x2ed000+0xdd56) [0x2fad56] [ 97.837] 8: /usr/lib/xorg/modules/libint10.so (xf86ExecX86int10+0x5d) [0x2f135d] [ 97.837] 9: /usr/lib/xorg/modules/libvbe.so (VBEExtendedInit+0x92) [0x2cc102] [ 97.837] 10: /usr/lib/xorg/modules/drivers/vesa_drv.so (0x2b5000+0x29db) [0x2b79db] [ 97.837] 11: Xorg (InitOutput+0x84b) [0x80b93cb] [ 97.837] 12: Xorg (0x8048000+0x1c1e5) [0x80641e5] [ 97.837] 13: /lib/libc.so.6 (__libc_start_main+0xf3) [0x72a3f3] [ 97.847] 14: Xorg (0x8048000+0x1c6a1) [0x80646a1] [ 97.848] Segmentation fault at address 0xb7e55000 [ 97.848] Fatal server error: [ 97.848] Caught signal 11 (Segmentation fault). Server aborting [ 97.850] [ 97.850]

9 years, 1 month

[PATCH v2 0/6] pci: 64bit support

by Gerd Hoffmann

Hi, New revision of my 64bit pci patches. This is what I'm using to play with 64bit PCI bars (ivshmem + qxl devices) and bridge support (patches from mst). Changes in v2: * tried to reduce the stack footprint of 64bit hex number printing. * changed patch splitting to make them (hopefully) more readable. * full support for bridges with 64bit memory windows, even nested. Also availabe from: git://git.kraxel.org/seabios pci64 enjoy, Gerd Gerd Hoffmann (6): output: add 64bit hex print support pci: split device discovery into multiple steps pci: 64bit support. pci: bridges can have two regions too pci: fix bridge ressource allocation. pci: add prefmem64 src/acpi-dsdt.dsl | 7 ++ src/acpi-dsdt.hex | 72 ++++++++++++--- src/config.h | 2 + src/output.c | 23 ++++- src/pci.h | 14 ++- src/pciinit.c | 272 ++++++++++++++++++++++++++++++++++++++--------------- 6 files changed, 294 insertions(+), 96 deletions(-)

9 years, 1 month

[Seabios] [PATCH 0/6] 64bit PCI BARs allocations (take 2)

by Alexey Korolev

Hi, This patch series enables 64bit BAR support in seabios. It has a bit different approach for resources accounting, We did this because we wanted: a) Provide 64bit bar support for PCI BARs and bridges with 64bit memory window. b) Allow migration to 64bit bit ranges if we did not fit into 32bit range c) Keep implementation simple. There are still have two main passes to enumerate resources and map devices, but structures are changed. We introduced two new structures: pci_region and pci_region_entry. The pci_region structure includes a list of pci_region_entries. Each pci_region_entry could be a PCI bar or a downstream PCI region (bridge). Each entry has a set of attributes: type (IO, MEM, PREFMEM), is64bit (if address can be over 4GB), size, base address, PCI device owner, and a pointer to the pci_region it belongs to. In the first pass we fill the pci_regions with entries and discover topology. In the second pass we try assigning memory addresses to pci_regions. If there is not enough space available the 64bit entries of root regions will be migrated to 64bit bit ranges and then we try assigning memory addresses again. Then each entry of each region will be mapped. The patch series includes 6 patches. In the 1st patch we introduce new structures. In the 2nd patch we introduce support functions for basic hlist operations, plus modify service functions to support 64bits address ranges. Note: I've seen similar hlist operations in post memory manager and stack location operations, it makes sense to move them to a header file. In the 3rd patch a new function to fill pci_region structures with entries, and discover topology is added. In the 4th patch we define address range for pci_region structure, migrate entries to 64bits address range if necessary, and program PCI BAR addresses and bridge regions. In the 6th patch we clear old code. And last patch is proposed by Michael Tsirkin, it contains changes in acpi-dsdt.dsl file those are necessary to support 64bit BARs in Windows. src/acpi-dsdt.dsl | 7 + src/acpi-dsdt.hex | 72 ++++++-- src/config.h | 2 + src/pci.h | 6 - src/pciinit.c | 509 +++++++++++++++++++++++++++++----------------------- 5 files changed, 352 insertions(+), 244 deletions(-) Note: At the moment there are three issues related to support of 64bit BARs in qemu (head of master branch). It's very likely they will be fixed in next qemu release. The 1st one is described here (this issue causing problems if 64bit BAR is mapped below 4GB and Linux guest OS version is < 2.6.27): http://www.mail-archive.com/qemu-devel@nongnu.org/msg94522.html The 2nd one is just a typo in i440fx init code (this issue is causing problems if somebody is going to access 64bit PCI memory - memory will be inaccessible): http://www.mail-archive.com/qemu-devel@nongnu.org/msg99423.html The 3nd issue is related to a case of HUGE PCI bars when BAR size is 4GB and over. Qemu for some reasons reports zero size in this case. New seabios should handle huge bars well. I've sent the patches for the first two issues. If they are all applied problems except the "huge BARs issue" should gone.

9 years, 1 month

Re: [SeaBIOS] [PATCH] vgabios: Fetch _rom_header_size from the global segment when computing the ROM's checksum

by Kevin O'Connor

On Mon, Mar 05, 2012 at 02:20:45PM +0000, Julian Pidancet wrote: > Otherwise, checksum_far is getting called with zero as the length > parameter, and the ROM checksum in the header end up beeing zero > after vga_post() is called. Thanks - good catch. I've added this to my queue. -Kevin

9 years, 1 month

Re: [SeaBIOS] vgabios testing

by Kevin O'Connor

On Mon, Mar 05, 2012 at 04:05:11PM +0000, Julian Pidancet wrote: > On Mon, Mar 5, 2012 at 3:33 PM, Kevin O'Connor <kevin(a)koconnor.net> wrote: > > > > Looking at the current generated code, it would seem that the only > > problematic instructions actually created by gcc in the current > > SeaVGABIOS code are "leavel" and "retl". (I don't see "enterl" > > generated, there are currently no function pointers, and there wont be > > any 32bit far calls/returns.) I wonder if we could post-process the > > assembler and replace "retl" with "retw $2" and "leavel" with "movl > > %ebp, %esp ; popl %ebp". Do you see any issues with that? > > > > Well, it is not a very elegant solution, but it seems to be the best > plan we have so far. > > I can see two problems: > > 1) If you look at the patch I tried to submit to xorg-devel. Other > instructions are concerned, in particular some forms of call (opcode > 0xFF). Which means that if we decide to write a postprocess tool, > we'll have to check that the ROM doesn't use those instructions. Agreed. If it's just "calll *%ereg" then it can probably just be replaced with "pushw $0 ; callw *%reg". > 2) Replacing instructions in the binary is simple, as long as the new > instruction is the same size as the replaced instruction. > > 66 c3 retl (2 bytes) > c2 02 00 ret $0x2 (3 bytes) > > 66 c9 leavel (2 bytes) > 66 89 ec mov %ebp,%esp (3 bytes) > 66 5d pop %ebp (1 bytes) > > Replacing instructions and handling displacement is probably going to > be a huge pain. I don't think that will be an issue. One can tell gcc to generate assembler and then post-process that. The gcc created assembler is still label based so no positional issues should arise. -Kevin

9 years, 1 month

Re: [SeaBIOS] vgabios testing

by Kevin O'Connor

On Sun, Mar 04, 2012 at 08:08:12PM +0000, Julian Pidancet wrote: > On Sun, Mar 4, 2012 at 7:54 PM, Kevin O'Connor <kevin(a)koconnor.net> wrote: > > > > The only thing I can think of would be to post-process the assembler > > and replace "retl" instructions with "retw $2" instructions. I'm not > > sure if it would work and it would be real ugly. > > > > As I mentionned, ret is not the only instruction causing problems. > I've identified issues with leave, enter, iret, and even some forms of > the call instruction, and the list is probaly not complete yet. So it > could be even more complicated that we think. > > It looks like x86emu was never tested with gcc produced code before. > And it looks like handling of the 0x66 instruction prefix has been > neglected in a lot of different places in the code. Looking at the current generated code, it would seem that the only problematic instructions actually created by gcc in the current SeaVGABIOS code are "leavel" and "retl". (I don't see "enterl" generated, there are currently no function pointers, and there wont be any 32bit far calls/returns.) I wonder if we could post-process the assembler and replace "retl" with "retw $2" and "leavel" with "movl %ebp, %esp ; popl %ebp". Do you see any issues with that? -Kevin

9 years, 1 month

[PATCH] seabios: acpi: Add _STA for PCI hotplug slots

by Alex Williamson

When a Status method is provided on a slot, the OSPM evaluates _STA in response to the device check notify on the slot. This allows some degree of a handshake between the platform and the OSPM that the hotplug has been acknowledged. In order to implement _STA, we need to know which slots have devices. A slot with device returns 0x0F, a slot without a device returns Zero. We get this information from Qemu using the 0xae08 I/O port register. This was previously the read-side of the register written to commit a device eject and always returned 0 on read. It now returns a bitmap of present slots, so we know that reading 0 means we have and old Qemu and dynamically modify our SSDT to rename the _STA methods. This is necessary to allow backwards compatibility. The _STA method also writes the slot identifier to I/O port register 0xae00 as an acknowledgment of the hotplug request. Signed-off-by: Alex Williamson <alex.williamson(a)redhat.com> --- src/acpi-dsdt.dsl | 36 ++- src/acpi-dsdt.hex | 124 ++++++---- src/acpi.c | 27 ++ src/ssdt-pcihp.dsl | 3 src/ssdt-pcihp.hex | 658 ++++++++++++++++++++++++++++++++++++++++++++-------- 5 files changed, 686 insertions(+), 162 deletions(-) diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl index 7082b65..6b87086 100644 --- a/src/acpi-dsdt.dsl +++ b/src/acpi-dsdt.dsl @@ -119,17 +119,15 @@ DefinitionBlock ( prt_slot3(0x001f), }) - OperationRegion(PCST, SystemIO, 0xae00, 0x08) + OperationRegion(PCST, SystemIO, 0xae00, 0x0c) Field (PCST, DWordAcc, NoLock, WriteAsZeros) { - PCIU, 32, - PCID, 32, - } - - OperationRegion(SEJ, SystemIO, 0xae08, 0x04) - Field (SEJ, DWordAcc, NoLock, WriteAsZeros) - { - B0EJ, 32, + // PCI Up/ACK + PUPA, 32, + // PCI Down + PDWN, 32, + // PCI Present/Eject + PPEJ, 32, } Name (_CRS, ResourceTemplate () @@ -462,10 +460,20 @@ DefinitionBlock ( /* Methods called by hotplug devices */ Method (PCEJ, 1, NotSerialized) { // _EJ0 method - eject callback - Store(ShiftLeft(1, Arg0), B0EJ) + Store(ShiftLeft(1, Arg0), PPEJ) Return (0x0) } + Method (PSTA, 1, NotSerialized) { + Store(ShiftLeft(1, Arg0), PUPA) + Store(PPEJ, Local0) + If (And(Local0, ShiftLeft(1, Arg0))) { + Return(0x0F) + } Else { + Return(Zero) + } + } + /* Hotplug notification method supplied by SSDT */ External (\_SB.PCI0.PCNT, MethodObj) @@ -473,12 +481,16 @@ DefinitionBlock ( Method(PCNF, 0) { // Local0 = iterator Store (Zero, Local0) + // Local1 = slots marked "up" + Store (PUPA, Local1) + // Local2 = slots marked "down" + Store (PDWN, Local2) While (LLess(Local0, 31)) { Increment(Local0) - If (And(PCIU, ShiftLeft(1, Local0))) { + If (And(Local1, ShiftLeft(1, Local0))) { PCNT(Local0, 1) } - If (And(PCID, ShiftLeft(1, Local0))) { + If (And(Local2, ShiftLeft(1, Local0))) { PCNT(Local0, 3) } } diff --git a/src/acpi-dsdt.hex b/src/acpi-dsdt.hex index 5dc7bb4..6d99f53 100644 --- a/src/acpi-dsdt.hex +++ b/src/acpi-dsdt.hex @@ -3,12 +3,12 @@ static unsigned char AmlCode[] = { 0x53, 0x44, 0x54, -0xd3, +0xeb, 0x10, 0x0, 0x0, 0x1, -0x2d, +0x10, 0x42, 0x58, 0x50, @@ -110,16 +110,16 @@ static unsigned char AmlCode[] = { 0x47, 0x42, 0x10, -0x44, -0x81, +0x40, +0x80, 0x5f, 0x53, 0x42, 0x5f, 0x5b, 0x82, -0x4c, -0x80, +0x48, +0x7f, 0x50, 0x43, 0x49, @@ -2014,47 +2014,27 @@ static unsigned char AmlCode[] = { 0x0, 0xae, 0xa, -0x8, +0xc, 0x5b, 0x81, -0x10, +0x15, 0x50, 0x43, 0x53, 0x54, 0x43, 0x50, -0x43, -0x49, 0x55, +0x50, +0x41, 0x20, 0x50, -0x43, -0x49, 0x44, +0x57, +0x4e, 0x20, -0x5b, -0x80, -0x53, -0x45, -0x4a, -0x5f, -0x1, -0xb, -0x8, -0xae, -0xa, -0x4, -0x5b, -0x81, -0xb, -0x53, -0x45, -0x4a, -0x5f, -0x43, -0x42, -0x30, +0x50, +0x50, 0x45, 0x4a, 0x20, @@ -3039,8 +3019,8 @@ static unsigned char AmlCode[] = { 0x4a, 0x20, 0x10, -0x46, -0x5, +0x42, +0x8, 0x2e, 0x5f, 0x53, @@ -3062,14 +3042,52 @@ static unsigned char AmlCode[] = { 0x1, 0x68, 0x0, -0x42, -0x30, +0x50, +0x50, 0x45, 0x4a, 0xa4, 0x0, 0x14, -0x38, +0x25, +0x50, +0x53, +0x54, +0x41, +0x1, +0x70, +0x79, +0x1, +0x68, +0x0, +0x50, +0x55, +0x50, +0x41, +0x70, +0x50, +0x50, +0x45, +0x4a, +0x60, +0xa0, +0xb, +0x7b, +0x60, +0x79, +0x1, +0x68, +0x0, +0x0, +0xa4, +0xa, +0xf, +0xa1, +0x3, +0xa4, +0x0, +0x14, +0x3e, 0x50, 0x43, 0x4e, @@ -3078,8 +3096,20 @@ static unsigned char AmlCode[] = { 0x70, 0x0, 0x60, +0x70, +0x50, +0x55, +0x50, +0x41, +0x61, +0x70, +0x50, +0x44, +0x57, +0x4e, +0x62, 0xa2, -0x2c, +0x26, 0x95, 0x60, 0xa, @@ -3087,12 +3117,9 @@ static unsigned char AmlCode[] = { 0x75, 0x60, 0xa0, -0x11, +0xe, 0x7b, -0x50, -0x43, -0x49, -0x55, +0x61, 0x79, 0x1, 0x60, @@ -3105,12 +3132,9 @@ static unsigned char AmlCode[] = { 0x60, 0x1, 0xa0, -0x12, +0xf, 0x7b, -0x50, -0x43, -0x49, -0x44, +0x62, 0x79, 0x1, 0x60, diff --git a/src/acpi.c b/src/acpi.c index 107469f..056270b 100644 --- a/src/acpi.c +++ b/src/acpi.c @@ -486,13 +486,14 @@ build_ssdt(void) #include "ssdt-pcihp.hex" -#define PCI_RMV_BASE 0xae0c +#define PCI_HOTPLUG 0xae0c +#define PCI_PRES_EJ 0xae08 extern void link_time_assertion(void); static void* build_pcihp(void) { - u32 rmvc_pcrm; + u32 hotpluggable, present; int i; u8 *ssdt = malloc_high(sizeof ssdp_pcihp_aml); @@ -504,7 +505,7 @@ static void* build_pcihp(void) link_time_assertion(); } - rmvc_pcrm = inl(PCI_RMV_BASE); + hotpluggable = inl(PCI_HOTPLUG); for (i = 0; i < ARRAY_SIZE(aml_ej0_name); ++i) { /* Slot is in byte 2 in _ADR */ u8 slot = ssdp_pcihp_aml[aml_adr_dword[i] + 2] & 0x1F; @@ -514,11 +515,29 @@ static void* build_pcihp(void) free(ssdt); return NULL; } - if (!(rmvc_pcrm & (0x1 << slot))) { + if (!(hotpluggable & (0x1 << slot))) { memcpy(ssdt + aml_ej0_name[i], "EJ0_", 4); } } + /* Runtime patching of STA. If running on system that + * doesn't support the Present/Eject field, replace _STA + * with STA_ */ + if (ARRAY_SIZE(aml_sta_name) != ARRAY_SIZE(aml_adr_dword)) { + link_time_assertion(); + } + + present = inl(PCI_PRES_EJ); + for (i = 0; present == 0 && i < ARRAY_SIZE(aml_sta_name); ++i) { + /* Sanity check */ + if (memcmp(ssdp_pcihp_aml + aml_sta_name[i], "_STA", 4)) { + warn_internalerror(); + free(ssdt); + return NULL; + } + memcpy(ssdt + aml_sta_name[i], "STA_", 4); + } + return ssdt; } diff --git a/src/ssdt-pcihp.dsl b/src/ssdt-pcihp.dsl index 4b435b8..376476a 100644 --- a/src/ssdt-pcihp.dsl +++ b/src/ssdt-pcihp.dsl @@ -10,6 +10,7 @@ DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1) /* Objects supplied by DSDT */ External (\_SB.PCI0, DeviceObj) External (\_SB.PCI0.PCEJ, MethodObj) + External (\_SB.PCI0.PSTA, MethodObj) Scope(\_SB.PCI0) { /* Bulk generated PCI hotplug devices */ @@ -23,6 +24,8 @@ DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1) Name (_ADR, 0x##slot##0000) \ ACPI_EXTRACT_METHOD_STRING aml_ej0_name \ Method (_EJ0, 1) { Return(PCEJ(0x##slot)) } \ + ACPI_EXTRACT_METHOD_STRING aml_sta_name \ + Method (_STA, 0) { Return(PSTA(0x##slot)) } \ Name (_SUN, 0x##slot) \ } diff --git a/src/ssdt-pcihp.hex b/src/ssdt-pcihp.hex index b15ad5a..f060c94 100644 --- a/src/ssdt-pcihp.hex +++ b/src/ssdt-pcihp.hex @@ -1,80 +1,113 @@ static unsigned short aml_adr_dword[] = { 0x3e, -0x62, -0x88, -0xae, -0xd4, -0xfa, -0x120, -0x146, -0x16c, -0x192, -0x1b8, -0x1de, -0x204, -0x22a, -0x250, -0x276, -0x29c, -0x2c2, -0x2e8, -0x30e, -0x334, -0x35a, -0x380, -0x3a6, -0x3cc, -0x3f2, -0x418, -0x43e, -0x464, -0x48a, -0x4b0 +0x6f, +0xa3, +0xd7, +0x10b, +0x13f, +0x173, +0x1a7, +0x1db, +0x20f, +0x243, +0x277, +0x2ab, +0x2df, +0x313, +0x347, +0x37b, +0x3af, +0x3e3, +0x417, +0x44b, +0x47f, +0x4b3, +0x4e7, +0x51b, +0x54f, +0x583, +0x5b7, +0x5eb, +0x61f, +0x653 +}; +static unsigned short aml_sta_name[] = { +0x51, +0x83, +0xb7, +0xeb, +0x11f, +0x153, +0x187, +0x1bb, +0x1ef, +0x223, +0x257, +0x28b, +0x2bf, +0x2f3, +0x327, +0x35b, +0x38f, +0x3c3, +0x3f7, +0x42b, +0x45f, +0x493, +0x4c7, +0x4fb, +0x52f, +0x563, +0x597, +0x5cb, +0x5ff, +0x633, +0x667 }; static unsigned short aml_ej0_name[] = { 0x44, -0x68, -0x8e, -0xb4, -0xda, -0x100, -0x126, -0x14c, -0x172, -0x198, -0x1be, -0x1e4, -0x20a, -0x230, -0x256, -0x27c, -0x2a2, -0x2c8, -0x2ee, -0x314, -0x33a, -0x360, -0x386, -0x3ac, -0x3d2, -0x3f8, -0x41e, -0x444, -0x46a, -0x490, -0x4b6 +0x75, +0xa9, +0xdd, +0x111, +0x145, +0x179, +0x1ad, +0x1e1, +0x215, +0x249, +0x27d, +0x2b1, +0x2e5, +0x319, +0x34d, +0x381, +0x3b5, +0x3e9, +0x41d, +0x451, +0x485, +0x4b9, +0x4ed, +0x521, +0x555, +0x589, +0x5bd, +0x5f1, +0x625, +0x659 }; static unsigned char ssdp_pcihp_aml[] = { 0x53, 0x53, 0x44, 0x54, -0x44, -0x6, +0xf5, +0x7, 0x0, 0x0, 0x1, -0x94, +0xcd, 0x42, 0x58, 0x50, @@ -102,8 +135,8 @@ static unsigned char ssdp_pcihp_aml[] = { 0x10, 0x20, 0x10, -0x4f, -0x61, +0x40, +0x7d, 0x5c, 0x2e, 0x5f, @@ -116,7 +149,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x30, 0x5b, 0x82, -0x22, +0x2f, 0x53, 0x30, 0x31, @@ -144,6 +177,19 @@ static unsigned char ssdp_pcihp_aml[] = { 0x45, 0x4a, 0x1, +0x14, +0xc, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0x1, 0x8, 0x5f, 0x53, @@ -152,7 +198,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x1, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x30, 0x32, @@ -181,6 +227,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x2, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x2, 0x8, 0x5f, 0x53, @@ -190,7 +250,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x2, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x30, 0x33, @@ -219,6 +279,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x3, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x3, 0x8, 0x5f, 0x53, @@ -228,7 +302,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x3, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x30, 0x34, @@ -257,6 +331,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x4, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x4, 0x8, 0x5f, 0x53, @@ -266,7 +354,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x30, 0x35, @@ -295,6 +383,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x5, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x5, 0x8, 0x5f, 0x53, @@ -304,7 +406,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x5, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x30, 0x36, @@ -333,6 +435,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x6, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x6, 0x8, 0x5f, 0x53, @@ -342,7 +458,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x6, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x30, 0x37, @@ -371,6 +487,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x7, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x7, 0x8, 0x5f, 0x53, @@ -380,7 +510,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x7, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x30, 0x38, @@ -409,6 +539,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x8, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x8, 0x8, 0x5f, 0x53, @@ -418,7 +562,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x8, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x30, 0x39, @@ -447,6 +591,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x9, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x9, 0x8, 0x5f, 0x53, @@ -456,7 +614,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x9, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x30, 0x41, @@ -485,6 +643,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0xa, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0xa, 0x8, 0x5f, 0x53, @@ -494,7 +666,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0xa, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x30, 0x42, @@ -523,6 +695,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0xb, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0xb, 0x8, 0x5f, 0x53, @@ -532,7 +718,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0xb, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x30, 0x43, @@ -561,6 +747,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0xc, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0xc, 0x8, 0x5f, 0x53, @@ -570,7 +770,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0xc, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x30, 0x44, @@ -599,6 +799,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0xd, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0xd, 0x8, 0x5f, 0x53, @@ -608,7 +822,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0xd, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x30, 0x45, @@ -637,6 +851,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0xe, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0xe, 0x8, 0x5f, 0x53, @@ -646,7 +874,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0xe, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x30, 0x46, @@ -675,6 +903,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0xf, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0xf, 0x8, 0x5f, 0x53, @@ -684,7 +926,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0xf, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x31, 0x30, @@ -713,6 +955,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x10, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x10, 0x8, 0x5f, 0x53, @@ -722,7 +978,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x10, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x31, 0x31, @@ -751,6 +1007,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x11, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x11, 0x8, 0x5f, 0x53, @@ -760,7 +1030,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x11, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x31, 0x32, @@ -789,6 +1059,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x12, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x12, 0x8, 0x5f, 0x53, @@ -798,7 +1082,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x12, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x31, 0x33, @@ -827,6 +1111,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x13, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x13, 0x8, 0x5f, 0x53, @@ -836,7 +1134,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x13, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x31, 0x34, @@ -865,6 +1163,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x14, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x14, 0x8, 0x5f, 0x53, @@ -874,7 +1186,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x14, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x31, 0x35, @@ -903,6 +1215,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x15, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x15, 0x8, 0x5f, 0x53, @@ -912,7 +1238,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x15, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x31, 0x36, @@ -941,6 +1267,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x16, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x16, 0x8, 0x5f, 0x53, @@ -950,7 +1290,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x16, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x31, 0x37, @@ -979,6 +1319,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x17, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x17, 0x8, 0x5f, 0x53, @@ -988,7 +1342,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x17, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x31, 0x38, @@ -1017,6 +1371,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x18, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x18, 0x8, 0x5f, 0x53, @@ -1026,7 +1394,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x18, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x31, 0x39, @@ -1055,6 +1423,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x19, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x19, 0x8, 0x5f, 0x53, @@ -1064,7 +1446,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x19, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x31, 0x41, @@ -1093,6 +1475,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x1a, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x1a, 0x8, 0x5f, 0x53, @@ -1102,7 +1498,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x1a, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x31, 0x42, @@ -1131,6 +1527,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x1b, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x1b, 0x8, 0x5f, 0x53, @@ -1140,7 +1550,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x1b, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x31, 0x43, @@ -1169,6 +1579,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x1c, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x1c, 0x8, 0x5f, 0x53, @@ -1178,7 +1602,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x1c, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x31, 0x44, @@ -1207,6 +1631,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x1d, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x1d, 0x8, 0x5f, 0x53, @@ -1216,7 +1654,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x1d, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x31, 0x45, @@ -1245,6 +1683,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x1e, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x1e, 0x8, 0x5f, 0x53, @@ -1254,7 +1706,7 @@ static unsigned char ssdp_pcihp_aml[] = { 0x1e, 0x5b, 0x82, -0x24, +0x32, 0x53, 0x31, 0x46, @@ -1283,6 +1735,20 @@ static unsigned char ssdp_pcihp_aml[] = { 0x4a, 0xa, 0x1f, +0x14, +0xd, +0x5f, +0x53, +0x54, +0x41, +0x0, +0xa4, +0x50, +0x53, +0x54, +0x41, +0xa, +0x1f, 0x8, 0x5f, 0x53,

9 years, 1 month

[PATCH] x86emu: Correctly handle 0x66 prefix for some instructions

by Julian Pidancet

Some instructions are not emulated correctly by x86emu when they are prefixed by the 0x66 opcode. I've identified problems in the emulation of these intructions: ret, enter, leave, iret and some forms of call. Most of the time, the problem is that these instructions should push or pop 32-bit values to/from the stack, instead of 16bit, when they are prefixed by the 0x66 special opcode. The SeaBIOS project aims to produce a complete legacy BIOS implementation as well as a VGA option ROM, entirely written in C and using the GCC compiler. In 16bit code produced by the GCC compiler, the 0x66 prefix is used almost everywhere. This patch is necessary to allow the SeaBIOS VGA option ROM to function with Xorg when using the vesa driver. Signed-off-by: Julian Pidancet <julian.pidancet(a)gmail.com> --- hw/xfree86/x86emu/ops.c | 194 ++++++++++++++++++++++++++++++++++------------ 1 files changed, 143 insertions(+), 51 deletions(-) diff --git a/hw/xfree86/x86emu/ops.c b/hw/xfree86/x86emu/ops.c index 5d3cac1..440b8dc 100644 --- a/hw/xfree86/x86emu/ops.c +++ b/hw/xfree86/x86emu/ops.c @@ -8487,7 +8487,11 @@ static void x86emuOp_ret_near_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF2("%x\n", imm); RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip); TRACE_AND_STEP(); - M.x86.R_IP = pop_word(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EIP = pop_long(); + } else { + M.x86.R_IP = pop_word(); + } M.x86.R_SP += imm; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -8503,7 +8507,11 @@ static void x86emuOp_ret_near(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("RET\n"); RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip); TRACE_AND_STEP(); - M.x86.R_IP = pop_word(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EIP = pop_long(); + } else { + M.x86.R_IP = pop_word(); + } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -8787,11 +8795,16 @@ static void x86emuOp_enter(u8 X86EMU_UNUSED(op1)) frame_pointer = M.x86.R_SP; if (nesting > 0) { for (i = 1; i < nesting; i++) { - M.x86.R_BP -= 2; - push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP)); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP -= 4; + push_long(fetch_data_long_abs(M.x86.R_SS, M.x86.R_BP)); + } else { + M.x86.R_BP -= 2; + push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP)); } - push_word(frame_pointer); } + push_word(frame_pointer); + } M.x86.R_BP = frame_pointer; M.x86.R_SP = (u16)(M.x86.R_SP - local); DECODE_CLEAR_SEGOVR(); @@ -8808,7 +8821,11 @@ static void x86emuOp_leave(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("LEAVE\n"); TRACE_AND_STEP(); M.x86.R_SP = M.x86.R_BP; - M.x86.R_BP = pop_word(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = pop_long(); + } else { + M.x86.R_BP = pop_word(); + } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -8827,8 +8844,13 @@ static void x86emuOp_ret_far_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF2("%x\n", imm); RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip); TRACE_AND_STEP(); - M.x86.R_IP = pop_word(); - M.x86.R_CS = pop_word(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_IP = pop_long(); + M.x86.R_CS = pop_long() & 0xffff; + } else { + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + } M.x86.R_SP += imm; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -8844,8 +8866,13 @@ static void x86emuOp_ret_far(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("RETF\n"); RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip); TRACE_AND_STEP(); - M.x86.R_IP = pop_word(); - M.x86.R_CS = pop_word(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_IP = pop_long(); + M.x86.R_CS = pop_long() & 0xffff; + } else { + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -8939,9 +8966,15 @@ static void x86emuOp_iret(u8 X86EMU_UNUSED(op1)) TRACE_AND_STEP(); - M.x86.R_IP = pop_word(); - M.x86.R_CS = pop_word(); - M.x86.R_FLG = pop_word(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_IP = pop_long(); + M.x86.R_CS = pop_long() & 0xffff; + M.x86.R_FLG = pop_long(); + } else { + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + M.x86.R_FLG = pop_word(); + } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -11168,19 +11201,36 @@ static void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) } break; case 2: /* call word ptr ... */ - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = destval; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(M.x86.R_EIP); + M.x86.R_EIP = destval; + } else { + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + } break; case 3: /* call far ptr ... */ - destval = fetch_data_word(destoffset); - destval2 = fetch_data_word(destoffset + 2); - TRACE_AND_STEP(); - push_word(M.x86.R_CS); - M.x86.R_CS = destval2; - push_word(M.x86.R_IP); - M.x86.R_IP = destval; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destval = fetch_data_long(destoffset); + destval2 = fetch_data_word(destoffset + 4); + TRACE_AND_STEP(); + push_long(M.x86.R_CS); + M.x86.R_CS = destval2; + push_long(M.x86.R_EIP); + M.x86.R_EIP = destval; + } else { + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + } break; case 4: /* jmp word ptr ... */ destval = fetch_data_word(destoffset); @@ -11250,19 +11300,36 @@ static void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) } break; case 2: /* call word ptr ... */ - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = destval; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(M.x86.R_EIP); + M.x86.R_EIP = destval; + } else { + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + } break; case 3: /* call far ptr ... */ - destval = fetch_data_word(destoffset); - destval2 = fetch_data_word(destoffset + 2); - TRACE_AND_STEP(); - push_word(M.x86.R_CS); - M.x86.R_CS = destval2; - push_word(M.x86.R_IP); - M.x86.R_IP = destval; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destval = fetch_data_long(destoffset); + destval2 = fetch_data_word(destoffset + 4); + TRACE_AND_STEP(); + push_long(M.x86.R_CS); + M.x86.R_CS = destval2; + push_long(M.x86.R_EIP); + M.x86.R_EIP = destval; + } else { + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + } break; case 4: /* jmp word ptr ... */ destval = fetch_data_word(destoffset); @@ -11332,19 +11399,36 @@ static void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) } break; case 2: /* call word ptr ... */ - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = destval; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(M.x86.R_EIP); + M.x86.R_EIP = destval; + } else { + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + } break; case 3: /* call far ptr ... */ - destval = fetch_data_word(destoffset); - destval2 = fetch_data_word(destoffset + 2); - TRACE_AND_STEP(); - push_word(M.x86.R_CS); - M.x86.R_CS = destval2; - push_word(M.x86.R_IP); - M.x86.R_IP = destval; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destval = fetch_data_long(destoffset); + destval2 = fetch_data_word(destoffset + 4); + TRACE_AND_STEP(); + push_long(M.x86.R_CS); + M.x86.R_CS = destval2; + push_long(M.x86.R_EIP); + M.x86.R_EIP = destval; + } else { + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + } break; case 4: /* jmp word ptr ... */ destval = fetch_data_word(destoffset); @@ -11412,11 +11496,19 @@ static void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) } break; case 2: /* call word ptr ... */ - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = *destreg; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_long(M.x86.R_EIP); + M.x86.R_EIP = *destreg; + } else { + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = *destreg; + } break; case 3: /* jmp far ptr ... */ DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); -- Julian Pidancet

9 years, 1 month

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SeaBIOS March 2012