SeaBIOS December 2012

seabios@seabios.org

15 participants
61 discussions

[RFC PATCH v4 21/30] Implement dimm-info
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

"query-dimm-info" and "info dimm" will give current state of all dimms in the system e.g. dimm0: on dimm1: off dimm2: off dimm3: on etc. Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- hmp-commands.hx | 2 ++ hmp.c | 17 +++++++++++++++++ hmp.h | 1 + hw/dimm.c | 43 +++++++++++++++++++++++++++++++++++++++++++ monitor.c | 7 +++++++ qapi-schema.json | 26 ++++++++++++++++++++++++++ 6 files changed, 96 insertions(+), 0 deletions(-) diff --git a/hmp-commands.hx b/hmp-commands.hx index 3fbd975..65d799e 100644 --- a/hmp-commands.hx +++ b/hmp-commands.hx @@ -1572,6 +1572,8 @@ show qdev device model list show roms @item info memory-total show memory-total +@item info dimm +show dimm @end table ETEXI diff --git a/hmp.c b/hmp.c index fb39b0d..f8456fd 100644 --- a/hmp.c +++ b/hmp.c @@ -635,6 +635,23 @@ void hmp_info_memory_total(Monitor *mon) monitor_printf(mon, "MemTotal: %lu\n", ram_total); } +void hmp_info_dimm(Monitor *mon) +{ + DimmInfoList *info; + DimmInfoList *item; + DimmInfo *dimm; + + info = qmp_query_dimm_info(NULL); + for (item = info; item; item = item->next) { + dimm = item->value; + monitor_printf(mon, "dimm %s : %s\n", dimm->dimm, + dimm->state ? "on" : "off"); + dimm->dimm = NULL; + } + + qapi_free_DimmInfoList(info); +} + void hmp_quit(Monitor *mon, const QDict *qdict) { monitor_suspend(mon); diff --git a/hmp.h b/hmp.h index 25a3a70..74ac061 100644 --- a/hmp.h +++ b/hmp.h @@ -37,6 +37,7 @@ void hmp_info_balloon(Monitor *mon); void hmp_info_pci(Monitor *mon); void hmp_info_block_jobs(Monitor *mon); void hmp_info_memory_total(Monitor *mon); +void hmp_info_dimm(Monitor *mon); void hmp_quit(Monitor *mon, const QDict *qdict); void hmp_stop(Monitor *mon, const QDict *qdict); void hmp_system_reset(Monitor *mon, const QDict *qdict); diff --git a/hw/dimm.c b/hw/dimm.c index f181e54..e79f23d 100644 --- a/hw/dimm.c +++ b/hw/dimm.c @@ -174,6 +174,18 @@ static DimmConfig *dimmcfg_find_from_name(DimmBus *bus, const char *name) return NULL; } +static DimmDevice *dimm_find_from_name(DimmBus *bus, const char *name) +{ + DimmDevice *slot; + + QTAILQ_FOREACH(slot, &bus->dimmlist, nextdimm) { + if (!strcmp(slot->qdev.id, name)) { + return slot; + } + } + return NULL; +} + void dimm_setup_fwcfg_layout(uint64_t *fw_cfg_slots) { DimmConfig *slot; @@ -203,6 +215,37 @@ uint64_t get_hp_memory_total(void) return info; } +DimmInfoList *qmp_query_dimm_info(Error **errp) +{ + DimmBus *bus; + DimmConfig *slot; + DimmInfoList *head = NULL, *info, *cur_item = NULL; + + QLIST_FOREACH(bus, &memory_buses, next) { + QTAILQ_FOREACH(slot, &bus->dimmconfig_list, nextdimmcfg) { + + info = g_malloc0(sizeof(*info)); + info->value = g_malloc0(sizeof(*info->value)); + info->value->dimm = g_malloc0(sizeof(char) * 32); + strcpy(info->value->dimm, slot->name); + if (dimm_find_from_name(bus, slot->name)) { + info->value->state = 1; + } else { + info->value->state = 0; + } + /* XXX: waiting for the qapi to support GSList */ + if (!cur_item) { + head = cur_item = info; + } else { + cur_item->next = info; + cur_item = info; + } + } + } + + return head; +} + static int dimm_init(DeviceState *s) { DimmBus *bus = DIMM_BUS(qdev_get_parent_bus(s)); diff --git a/monitor.c b/monitor.c index 6e87d0d..de1dcf1 100644 --- a/monitor.c +++ b/monitor.c @@ -2743,6 +2743,13 @@ static mon_cmd_t info_cmds[] = { .mhandler.info = do_trace_print_events, }, { + .name = "dimm", + .args_type = "", + .params = "", + .help = "show active and non active dimms", + .mhandler.info = hmp_info_dimm, + }, + { .name = NULL, }, }; diff --git a/qapi-schema.json b/qapi-schema.json index 33f88d6..5a20577 100644 --- a/qapi-schema.json +++ b/qapi-schema.json @@ -2914,6 +2914,32 @@ { 'command': 'query-memory-total', 'returns': 'int' } ## +# @DimmInfo: +# +# Information about status of a memory hotplug command +# +# @dimm: the Dimm associated with the result +# +# @result: the result of the hotplug command +# +# Since: 1.4 +# +## +{ 'type': 'DimmInfo', + 'data': {'dimm': 'str', 'state': 'bool'} } + +## +# @query-dimm-info: +# +# Returns total memory in bytes, including hotplugged dimms +# +# Returns: int +# +# Since: 1.4 +## +{ 'command': 'query-dimm-info', 'returns': ['DimmInfo'] } + +## # @QKeyCode: # # An enumeration of key name. -- 1.7.9

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[RFC PATCH v4 20/30] balloon: update with hotplugged memory
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

query-balloon and "info balloon" should report total memory available to the guest. balloon inflate/ deflate can also use all memory available to the guest (initial + hotplugged memory) Ballon driver has been minimaly tested with the patch, please review and test. Caveat: if the guest does not online hotplugged-memory, it's easy for a balloon inflate command to OOM a guest. Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- hw/virtio-balloon.c | 13 +++++++++---- 1 files changed, 9 insertions(+), 4 deletions(-) diff --git a/hw/virtio-balloon.c b/hw/virtio-balloon.c index dd1a650..149e8ba 100644 --- a/hw/virtio-balloon.c +++ b/hw/virtio-balloon.c @@ -22,6 +22,7 @@ #include "virtio-balloon.h" #include "kvm.h" #include "exec-memory.h" +#include "dimm.h" #if defined(__linux__) #include <sys/mman.h> @@ -147,10 +148,11 @@ static void virtio_balloon_set_config(VirtIODevice *vdev, VirtIOBalloon *dev = to_virtio_balloon(vdev); struct virtio_balloon_config config; uint32_t oldactual = dev->actual; + uint64_t hotplugged_ram_size = get_hp_memory_total(); memcpy(&config, config_data, 8); dev->actual = le32_to_cpu(config.actual); if (dev->actual != oldactual) { - qemu_balloon_changed(ram_size - + qemu_balloon_changed(ram_size + hotplugged_ram_size - (dev->actual << VIRTIO_BALLOON_PFN_SHIFT)); } } @@ -188,17 +190,20 @@ static void virtio_balloon_stat(void *opaque, BalloonInfo *info) info->actual = ram_size - ((uint64_t) dev->actual << VIRTIO_BALLOON_PFN_SHIFT); + info->actual += get_hp_memory_total(); } static void virtio_balloon_to_target(void *opaque, ram_addr_t target) { VirtIOBalloon *dev = opaque; + uint64_t hotplugged_ram_size = get_hp_memory_total(); - if (target > ram_size) { - target = ram_size; + if (target > ram_size + hotplugged_ram_size) { + target = ram_size + hotplugged_ram_size; } if (target) { - dev->num_pages = (ram_size - target) >> VIRTIO_BALLOON_PFN_SHIFT; + dev->num_pages = (ram_size + hotplugged_ram_size - target) >> + VIRTIO_BALLOON_PFN_SHIFT; virtio_notify_config(&dev->vdev); } } -- 1.7.9

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[RFC PATCH v4 19/30] Implement "info memory-total" and "query-memory-total"
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

Returns total physical memory available to guest in bytes, including hotplugged memory. Note that the number reported here may be different from what the guest sees e.g. if the guest has not logically onlined hotplugged memory. This functionality is provided independently of a balloon device, since a guest can be using ACPI memory hotplug without using a balloon device. v3->v4: Moved qmp command implementation to vl.c. This prevents a circular header dependency problem. Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- hmp-commands.hx | 2 ++ hmp.c | 7 +++++++ hmp.h | 1 + hw/dimm.c | 14 ++++++++++++++ hw/dimm.h | 1 + monitor.c | 7 +++++++ qapi-schema.json | 11 +++++++++++ qmp-commands.hx | 20 ++++++++++++++++++++ vl.c | 9 +++++++++ 9 files changed, 72 insertions(+), 0 deletions(-) diff --git a/hmp-commands.hx b/hmp-commands.hx index 010b8c9..3fbd975 100644 --- a/hmp-commands.hx +++ b/hmp-commands.hx @@ -1570,6 +1570,8 @@ show device tree show qdev device model list @item info roms show roms +@item info memory-total +show memory-total @end table ETEXI diff --git a/hmp.c b/hmp.c index 180ba2b..fb39b0d 100644 --- a/hmp.c +++ b/hmp.c @@ -628,6 +628,13 @@ void hmp_info_block_jobs(Monitor *mon) } } +void hmp_info_memory_total(Monitor *mon) +{ + uint64_t ram_total; + ram_total = (uint64_t)qmp_query_memory_total(NULL); + monitor_printf(mon, "MemTotal: %lu\n", ram_total); +} + void hmp_quit(Monitor *mon, const QDict *qdict) { monitor_suspend(mon); diff --git a/hmp.h b/hmp.h index 0ab03be..25a3a70 100644 --- a/hmp.h +++ b/hmp.h @@ -36,6 +36,7 @@ void hmp_info_spice(Monitor *mon); void hmp_info_balloon(Monitor *mon); void hmp_info_pci(Monitor *mon); void hmp_info_block_jobs(Monitor *mon); +void hmp_info_memory_total(Monitor *mon); void hmp_quit(Monitor *mon, const QDict *qdict); void hmp_stop(Monitor *mon, const QDict *qdict); void hmp_system_reset(Monitor *mon, const QDict *qdict); diff --git a/hw/dimm.c b/hw/dimm.c index e384952..f181e54 100644 --- a/hw/dimm.c +++ b/hw/dimm.c @@ -189,6 +189,20 @@ void dimm_setup_fwcfg_layout(uint64_t *fw_cfg_slots) } } +uint64_t get_hp_memory_total(void) +{ + DimmBus *bus; + DimmDevice *slot; + uint64_t info = 0; + + QLIST_FOREACH(bus, &memory_buses, next) { + QTAILQ_FOREACH(slot, &bus->dimmlist, nextdimm) { + info += slot->size; + } + } + return info; +} + static int dimm_init(DeviceState *s) { DimmBus *bus = DIMM_BUS(qdev_get_parent_bus(s)); diff --git a/hw/dimm.h b/hw/dimm.h index 75a6911..5130b2c 100644 --- a/hw/dimm.h +++ b/hw/dimm.h @@ -85,5 +85,6 @@ DimmBus *dimm_bus_create(Object *parent, const char *name, uint32_t max_dimms, dimm_calcoffset_fn pmc_set_offset); void dimm_config_create(char *id, uint64_t size, const char *bus, uint64_t node, uint32_t dimm_idx, uint32_t populated); +uint64_t get_hp_memory_total(void); #endif diff --git a/monitor.c b/monitor.c index c0e32d6..6e87d0d 100644 --- a/monitor.c +++ b/monitor.c @@ -2708,6 +2708,13 @@ static mon_cmd_t info_cmds[] = { .mhandler.info = hmp_info_balloon, }, { + .name = "memory-total", + .args_type = "", + .params = "", + .help = "show total memory size", + .mhandler.info = hmp_info_memory_total, + }, + { .name = "qtree", .args_type = "", .params = "", diff --git a/qapi-schema.json b/qapi-schema.json index 5dfa052..33f88d6 100644 --- a/qapi-schema.json +++ b/qapi-schema.json @@ -2903,6 +2903,17 @@ { 'command': 'query-target', 'returns': 'TargetInfo' } ## +# @query-memory-total: +# +# Returns total memory in bytes, including hotplugged dimms +# +# Returns: int +# +# Since: 1.4 +## +{ 'command': 'query-memory-total', 'returns': 'int' } + +## # @QKeyCode: # # An enumeration of key name. diff --git a/qmp-commands.hx b/qmp-commands.hx index 5c692d0..a99117a 100644 --- a/qmp-commands.hx +++ b/qmp-commands.hx @@ -2654,3 +2654,23 @@ EQMP .args_type = "", .mhandler.cmd_new = qmp_marshal_input_query_target, }, + + { + .name = "query-memory-total", + .args_type = "", + .mhandler.cmd_new = qmp_marshal_input_query_memory_total + }, +SQMP +query-memory-total +---------- + +Return total memory in bytes, including hotplugged dimms + +Example: + +-> { "execute": "query-memory-total" } +<- { + "return": 1073741824 + } + +EQMP diff --git a/vl.c b/vl.c index 8406933..80803c5 100644 --- a/vl.c +++ b/vl.c @@ -126,6 +126,7 @@ int main(int argc, char **argv) #include "hw/xen.h" #include "hw/qdev.h" #include "hw/loader.h" +#include "hw/dimm.h" #include "bt-host.h" #include "net.h" #include "net/slirp.h" @@ -442,6 +443,14 @@ StatusInfo *qmp_query_status(Error **errp) return info; } +int64_t qmp_query_memory_total(Error **errp) +{ + uint64_t info; + info = ram_size + get_hp_memory_total(); + + return (int64_t)info; +} + /***********************************************************/ /* real time host monotonic timer */ -- 1.7.9

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[RFC PATCH v4 18/30] Introduce paravirt interface QEMU_CFG_PCI_WINDOW
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

Qemu calculates the 32-bit and 64-bit PCI starting offsets based on initial memory and hotplug-able dimms. This info needs to be passed to Seabios for PCI initialization. Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- hw/fw_cfg.h | 1 + hw/pc_piix.c | 10 ++++++++++ hw/pc_q35.c | 9 +++++++++ 3 files changed, 20 insertions(+), 0 deletions(-) diff --git a/hw/fw_cfg.h b/hw/fw_cfg.h index 619a394..8b48493 100644 --- a/hw/fw_cfg.h +++ b/hw/fw_cfg.h @@ -27,6 +27,7 @@ #define FW_CFG_SETUP_SIZE 0x17 #define FW_CFG_SETUP_DATA 0x18 #define FW_CFG_FILE_DIR 0x19 +#define FW_CFG_PCI_WINDOW 0x1a #define FW_CFG_FILE_FIRST 0x20 #define FW_CFG_FILE_SLOTS 0x10 diff --git a/hw/pc_piix.c b/hw/pc_piix.c index 1a99852..b6633e8 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -48,6 +48,7 @@ # include <xen/hvm/hvm_info_table.h> #endif #include "piix_pci.h" +#include "fw_cfg.h" #define MAX_IDE_BUS 2 @@ -86,6 +87,7 @@ static void pc_init1(MemoryRegion *system_memory, MemoryRegion *pci_memory; MemoryRegion *rom_memory; void *fw_cfg = NULL; + uint64_t *pci_window_fw_cfg; I440FXState *i440fx_host; PIIX3State *piix3; @@ -141,6 +143,14 @@ static void pc_init1(MemoryRegion *system_memory, qdev_init_nofail(DEVICE(i440fx_host)); bochs_meminfo_bios_init(fw_cfg); + + pci_window_fw_cfg = g_malloc0(2 * 8); + pci_window_fw_cfg[0] = cpu_to_le64(i440fx_host->mch.below_4g_mem_size); + pci_window_fw_cfg[1] = cpu_to_le64(0x100000000ULL + + i440fx_host->mch.above_4g_mem_size); + fw_cfg_add_bytes(fw_cfg, FW_CFG_PCI_WINDOW, + (uint8_t *)pci_window_fw_cfg, 2 * 8); + i440fx_state = &i440fx_host->mch; pci_bus = i440fx_host->parent_obj.bus; /* Xen supports additional interrupt routes from the PCI devices to diff --git a/hw/pc_q35.c b/hw/pc_q35.c index 7ce0b53..e35814a 100644 --- a/hw/pc_q35.c +++ b/hw/pc_q35.c @@ -87,6 +87,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args) PCIDevice *ahci; qemu_irq *cmos_s3; void *fw_cfg = NULL; + uint64_t *pci_window_fw_cfg; pc_cpus_init(cpu_model); @@ -139,6 +140,14 @@ static void pc_q35_init(QEMUMachineInitArgs *args) /* pci */ qdev_init_nofail(DEVICE(q35_host)); bochs_meminfo_bios_init(fw_cfg); + + pci_window_fw_cfg = g_malloc0(2 * 8); + pci_window_fw_cfg[0] = cpu_to_le64(MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); + pci_window_fw_cfg[1] = cpu_to_le64(0x100000000ULL + + q35_host->mch.above_4g_mem_size); + fw_cfg_add_bytes(fw_cfg, FW_CFG_PCI_WINDOW, + (uint8_t *)pci_window_fw_cfg, 2 * 8); + host_bus = q35_host->host.pci.bus; /* create ISA bus */ lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, -- 1.7.9

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[RFC PATCH v4 17/30] pci: Use paravirt interface for pcimem_start and pcimem64_start
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

Initialize the 32-bit and 64-bit pci starting offsets from values passed in by the qemu paravirt interface QEMU_CFG_PCI_WINDOW. Qemu calculates the starting offsets based on initial memory and hotplug-able dimms. It's possible to avoid the new paravirt interface, and calculate pci ranges from srat entries. But the code changes are ugly, see: http://lists.gnu.org/archive/html/qemu-devel/2012-09/msg03548.html --- src/paravirt.c | 6 ++++++ src/paravirt.h | 2 ++ src/pciinit.c | 9 +++++++++ 3 files changed, 17 insertions(+), 0 deletions(-) diff --git a/src/paravirt.c b/src/paravirt.c index 4b5c441..f7517b9 100644 --- a/src/paravirt.c +++ b/src/paravirt.c @@ -347,3 +347,9 @@ void qemu_cfg_romfile_setup(void) dprintf(3, "Found fw_cfg file: %s (size=%d)\n", file->name, file->size); } } + +void qemu_cfg_get_pci_offsets(u64 *pcimem_start, u64 *pcimem64_start) +{ + qemu_cfg_read_entry(pcimem_start, QEMU_CFG_PCI_WINDOW, sizeof(u64)); + qemu_cfg_read((u8*)(pcimem64_start), sizeof(u64)); +} diff --git a/src/paravirt.h b/src/paravirt.h index a284c41..b53ff88 100644 --- a/src/paravirt.h +++ b/src/paravirt.h @@ -35,6 +35,7 @@ static inline int kvm_para_available(void) #define QEMU_CFG_BOOT_MENU 0x0e #define QEMU_CFG_MAX_CPUS 0x0f #define QEMU_CFG_FILE_DIR 0x19 +#define QEMU_CFG_PCI_WINDOW 0x1a #define QEMU_CFG_ARCH_LOCAL 0x8000 #define QEMU_CFG_ACPI_TABLES (QEMU_CFG_ARCH_LOCAL + 0) #define QEMU_CFG_SMBIOS_ENTRIES (QEMU_CFG_ARCH_LOCAL + 1) @@ -65,5 +66,6 @@ struct e820_reservation { u32 qemu_cfg_e820_entries(void); void* qemu_cfg_e820_load_next(void *addr); void qemu_cfg_romfile_setup(void); +void qemu_cfg_get_pci_offsets(u64 *pcimem_start, u64 *pcimem64_start); #endif diff --git a/src/pciinit.c b/src/pciinit.c index a406bbd..4103d2d 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -734,6 +734,7 @@ static void pci_bios_map_devices(struct pci_bus *busses) void pci_setup(void) { + u64 pv_pcimem_start, pv_pcimem64_start; if (CONFIG_COREBOOT || usingXen()) { // PCI setup already done by coreboot or Xen - just do probe. pci_probe_devices(); @@ -769,5 +770,13 @@ pci_setup(void) pci_bios_init_devices(); + /* if qemu gives us other pci window values, it means there are hotplug-able + * dimms. Adjust accordingly */ + qemu_cfg_get_pci_offsets(&pv_pcimem_start, &pv_pcimem64_start); + if (pv_pcimem_start > pcimem_start) + pcimem_start = pv_pcimem_start; + if (pv_pcimem64_start > pcimem64_start) + pcimem64_start = pv_pcimem64_start; + free(busses); } -- 1.7.9

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[RFC PATCH v4 16/30] pc: Add dimm paravirt SRAT info
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

The numa_fw_cfg paravirt interface is extended to include SRAT information for all hotplug-able dimms. There are 3 words for each hotplug-able memory slot, denoting start address, size and node proximity. The new info is appended after existing numa info, so that the fw_cfg layout does not break. This information is used by Seabios to build hotplug memory device objects at runtime. nb_numa_nodes is set to 1 by default (not 0), so that we always pass srat info to SeaBIOS. v3->v4: numa_fw_cfg needs to be initalized after memory controller sets up dimm ranges. Make changes for pc_piix and pc_q35 to set numa_fw_cfg after i440fx initialization. v2->v3: setting nb_numa_nodes to 1 is not needed v1->v2: Dimm SRAT info (#dimms) is appended at end of existing numa fw_cfg in order not to break existing layout Documentation of the new fwcfg layout is included in docs/specs/fwcfg.txt Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- docs/specs/fwcfg.txt | 28 ++++++++++++++++++++++++++++ hw/pc.c | 28 +++++++++++++++++++++++----- hw/pc.h | 1 + hw/pc_piix.c | 1 + hw/pc_q35.c | 8 +++++--- sysemu.h | 1 + 6 files changed, 59 insertions(+), 8 deletions(-) create mode 100644 docs/specs/fwcfg.txt diff --git a/docs/specs/fwcfg.txt b/docs/specs/fwcfg.txt new file mode 100644 index 0000000..e6fcd8f --- /dev/null +++ b/docs/specs/fwcfg.txt @@ -0,0 +1,28 @@ +QEMU<->BIOS Paravirt Documentation +-------------------------------------- + +This document describes paravirt data structures passed from QEMU to BIOS. + +fw_cfg SRAT paravirt info +-------------------- +The SRAT info passed from QEMU to BIOS has the following layout: + +----------------------------------------------------------------------------------------------- +#nodes | cpu0_pxm | cpu1_pxm | ... | cpulast_pxm | node0_mem | node1_mem | ... | nodelast_mem + +----------------------------------------------------------------------------------------------- +#dimms | dimm0_start | dimm0_sz | dimm0_pxm | ... | dimmlast_start | dimmlast_sz | dimmlast_pxm + +Entry 0 contains the number of numa nodes (nb_numa_nodes). + +Entries 1..max_cpus: The next max_cpus entries describe node proximity for each +one of the vCPUs in the system. + +Entries max_cpus+1..max_cpus+nb_numa_nodes+1: The next nb_numa_nodes entries +describe the memory size for each one of the NUMA nodes in the system. + +Entry max_cpus+nb_numa_nodes+1 contains the number of memory dimms (nb_hp_dimms) + +The last 3 * nb_hp_dimms entries are organized in triplets: Each triplet contains +the physical address offset, size (in bytes), and node proximity for the +respective dimm. diff --git a/hw/pc.c b/hw/pc.c index b11e7c4..025c356 100644 --- a/hw/pc.c +++ b/hw/pc.c @@ -51,6 +51,7 @@ #include "exec-memory.h" #include "arch_init.h" #include "bitmap.h" +#include "hw/dimm.h" /* debug PC/ISA interrupts */ //#define DEBUG_IRQ @@ -582,8 +583,6 @@ static void *bochs_bios_init(void) void *fw_cfg; uint8_t *smbios_table; size_t smbios_len; - uint64_t *numa_fw_cfg; - int i, j; PortioList *bochs_bios_port_list = g_new(PortioList, 1); portio_list_init(bochs_bios_port_list, bochs_bios_portio_list, @@ -607,11 +606,24 @@ static void *bochs_bios_init(void) fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg, sizeof(struct hpet_fw_config)); + + return fw_cfg; +} + +void bochs_meminfo_bios_init(void *fw_cfg) +{ + uint64_t *numa_fw_cfg; + uint64_t *hp_dimms_fw_cfg; + int i, j; + /* allocate memory for the NUMA channel: one (64bit) word for the number * of nodes, one word for each VCPU->node and one word for each node to * hold the amount of memory. + * Finally one word for the number of hotplug memory slots and three words + * for each hotplug memory slot (start address, size and node proximity). */ - numa_fw_cfg = g_malloc0((1 + max_cpus + nb_numa_nodes) * 8); + numa_fw_cfg = g_malloc0((2 + max_cpus + nb_numa_nodes + 3 * nb_hp_dimms) + * 8); numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); for (i = 0; i < max_cpus; i++) { for (j = 0; j < nb_numa_nodes; j++) { @@ -624,10 +636,16 @@ static void *bochs_bios_init(void) for (i = 0; i < nb_numa_nodes; i++) { numa_fw_cfg[max_cpus + 1 + i] = cpu_to_le64(node_mem[i]); } + + numa_fw_cfg[1 + max_cpus + nb_numa_nodes] = cpu_to_le64(nb_hp_dimms); + + hp_dimms_fw_cfg = numa_fw_cfg + 2 + max_cpus + nb_numa_nodes; + if (nb_hp_dimms) { + dimm_setup_fwcfg_layout(hp_dimms_fw_cfg); + } fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, - (1 + max_cpus + nb_numa_nodes) * 8); + (2 + max_cpus + nb_numa_nodes + 3 * nb_hp_dimms) * 8); - return fw_cfg; } static long get_file_size(FILE *f) diff --git a/hw/pc.h b/hw/pc.h index 2237e86..075514f 100644 --- a/hw/pc.h +++ b/hw/pc.h @@ -185,5 +185,6 @@ void pc_system_firmware_init(MemoryRegion *rom_memory); #define E820_UNUSABLE 5 int e820_add_entry(uint64_t, uint64_t, uint32_t); +void bochs_meminfo_bios_init(void *fw_cfg); #endif diff --git a/hw/pc_piix.c b/hw/pc_piix.c index fe995b9..1a99852 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -140,6 +140,7 @@ static void pc_init1(MemoryRegion *system_memory, i440fx_host->mch.above_4g_mem_size = above_4g_mem_size; qdev_init_nofail(DEVICE(i440fx_host)); + bochs_meminfo_bios_init(fw_cfg); i440fx_state = &i440fx_host->mch; pci_bus = i440fx_host->parent_obj.bus; /* Xen supports additional interrupt routes from the PCI devices to diff --git a/hw/pc_q35.c b/hw/pc_q35.c index e6375bf..7ce0b53 100644 --- a/hw/pc_q35.c +++ b/hw/pc_q35.c @@ -86,6 +86,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args) ICH9LPCState *ich9_lpc; PCIDevice *ahci; qemu_irq *cmos_s3; + void *fw_cfg = NULL; pc_cpus_init(cpu_model); @@ -111,9 +112,9 @@ static void pc_q35_init(QEMUMachineInitArgs *args) /* allocate ram and load rom/bios */ if (!xen_enabled()) { - pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline, - initrd_filename, below_4g_mem_size, above_4g_mem_size, - rom_memory, &ram_memory); + fw_cfg = pc_memory_init(get_system_memory(), kernel_filename, + kernel_cmdline, initrd_filename, below_4g_mem_size, + above_4g_mem_size, rom_memory, &ram_memory); } /* irq lines */ @@ -137,6 +138,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args) q35_host->mch.above_4g_mem_size = above_4g_mem_size; /* pci */ qdev_init_nofail(DEVICE(q35_host)); + bochs_meminfo_bios_init(fw_cfg); host_bus = q35_host->host.pci.bus; /* create ISA bus */ lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, diff --git a/sysemu.h b/sysemu.h index 1b6add2..86f729e 100644 --- a/sysemu.h +++ b/sysemu.h @@ -130,6 +130,7 @@ extern QEMUClock *rtc_clock; extern int nb_numa_nodes; extern uint64_t node_mem[MAX_NODES]; extern unsigned long *node_cpumask[MAX_NODES]; +extern int nb_hp_dimms; #define MAX_OPTION_ROMS 16 typedef struct QEMUOptionRom { -- 1.7.9

1 0

[RFC PATCH v4 15/30] q35: Add i440fx dram controller initialization
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

Create memory buses and introduce function to adjust memory map for hotplug-able dimms. Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- hw/pc_q35.c | 1 + hw/q35.c | 27 +++++++++++++++++++++++++++ hw/q35.h | 5 +++++ 3 files changed, 33 insertions(+), 0 deletions(-) diff --git a/hw/pc_q35.c b/hw/pc_q35.c index 3429a9a..e6375bf 100644 --- a/hw/pc_q35.c +++ b/hw/pc_q35.c @@ -41,6 +41,7 @@ #include "hw/ide/pci.h" #include "hw/ide/ahci.h" #include "hw/usb.h" +#include "fw_cfg.h" /* ICH9 AHCI has 6 ports */ #define MAX_SATA_PORTS 6 diff --git a/hw/q35.c b/hw/q35.c index efebc27..cc27d72 100644 --- a/hw/q35.c +++ b/hw/q35.c @@ -236,12 +236,39 @@ static void mch_reset(DeviceState *qdev) mch_update(mch); } +static hwaddr mch_dimm_offset(DeviceState *dev, uint64_t size) +{ + MCHPCIState *d = MCH_PCI_DEVICE(dev); + hwaddr ret; + + /* if dimm fits before pci hole, append it normally */ + if (d->below_4g_mem_size + size <= MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT) { + ret = d->below_4g_mem_size; + d->below_4g_mem_size += size; + } + /* otherwise place it above 4GB */ + else { + ret = 0x100000000LL + d->above_4g_mem_size; + d->above_4g_mem_size += size; + } + + return ret; +} + static int mch_init(PCIDevice *d) { int i; hwaddr pci_hole64_size; MCHPCIState *mch = MCH_PCI_DEVICE(d); + /* Initialize 2 GMC DRAM channels x 4 DRAM ranks each */ + mch->dram_channel[0] = dimm_bus_create(OBJECT(d), "membus.0", 4, + mch_dimm_offset); + mch->dram_channel[1] = dimm_bus_create(OBJECT(d), "membus.1", 4, + mch_dimm_offset); + /* Initialize paravirtual memory bus */ + mch->pv_dram_channel = dimm_bus_create(OBJECT(d), "membus.pv", 0, + mch_dimm_offset); /* setup pci memory regions */ memory_region_init_alias(&mch->pci_hole, "pci-hole", mch->pci_address_space, diff --git a/hw/q35.h b/hw/q35.h index e34f7c1..bf76dc8 100644 --- a/hw/q35.h +++ b/hw/q35.h @@ -34,6 +34,7 @@ #include "acpi.h" #include "acpi_ich9.h" #include "pam.h" +#include "dimm.h" #define TYPE_Q35_HOST_DEVICE "q35-pcihost" #define Q35_HOST_DEVICE(obj) \ @@ -56,6 +57,10 @@ typedef struct MCHPCIState { uint8_t smm_enabled; ram_addr_t below_4g_mem_size; ram_addr_t above_4g_mem_size; + /* GMCH allows for 2 DRAM channels x 4 DRAM ranks each */ + DimmBus * dram_channel[2]; + /* paravirtual memory bus */ + DimmBus *pv_dram_channel; } MCHPCIState; typedef struct Q35PCIHost { -- 1.7.9

1 0

[RFC PATCH v4 14/30] piix_pci: Add i440fx dram controller initialization
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

Also introduce function to adjust memory map for hotplug-able dimms. Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- hw/pc_piix.c | 6 +++--- hw/piix_pci.c | 30 ++++++++++++++++++++++++++++-- 2 files changed, 31 insertions(+), 5 deletions(-) diff --git a/hw/pc_piix.c b/hw/pc_piix.c index 6a9b508..fe995b9 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -95,9 +95,9 @@ static void pc_init1(MemoryRegion *system_memory, kvmclock_create(); } - if (ram_size >= 0xe0000000 ) { - above_4g_mem_size = ram_size - 0xe0000000; - below_4g_mem_size = 0xe0000000; + if (ram_size >= I440FX_PCI_HOLE_START) { + above_4g_mem_size = ram_size - I440FX_PCI_HOLE_START; + below_4g_mem_size = I440FX_PCI_HOLE_START; } else { above_4g_mem_size = 0; below_4g_mem_size = ram_size; diff --git a/hw/piix_pci.c b/hw/piix_pci.c index 7ca3c73..9866b1d 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -125,6 +125,25 @@ static const VMStateDescription vmstate_i440fx = { } }; +hwaddr i440fx_pmc_dimm_offset(DeviceState *dev, uint64_t size) +{ + PCII440FXState *d = I440FX_PCI_DEVICE(dev); + hwaddr ret; + + /* if dimm fits before pci hole, append it normally */ + if (d->below_4g_mem_size + size <= I440FX_PCI_HOLE_START) { + ret = d->below_4g_mem_size; + d->below_4g_mem_size += size; + } + /* otherwise place it above 4GB */ + else { + ret = 0x100000000LL + d->above_4g_mem_size; + d->above_4g_mem_size += size; + } + + return ret; +} + static void i440fx_pcihost_initfn(Object *obj) { I440FXState *s = I440FX_HOST_DEVICE(obj); @@ -148,8 +167,8 @@ static int i440fx_pcihost_init(SysBusDevice *dev) sysbus_add_io(dev, 0xcfc, &pci->data_mem); sysbus_init_ioports(&pci->busdev, 0xcfc, 4); - b = pci_bus_new(&s->parent_obj.busdev.qdev, NULL, s->mch.pci_address_space, - s->mch.address_space_io, 0); + b = pci_bus_new(&s->parent_obj.busdev.qdev, "pci.0", + s->mch.pci_address_space, s->mch.address_space_io, 0); s->parent_obj.bus = b; qdev_set_parent_bus(DEVICE(&s->mch), BUS(b)); qdev_init_nofail(DEVICE(&s->mch)); @@ -169,6 +188,13 @@ static int i440fx_initfn(PCIDevice *dev) pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 : ((uint64_t)1 << 62)); + + /* Initialize i440fx's DRAM channel, it can hold up to 8 DRAM ranks */ + f->dram_channel0 = dimm_bus_create(OBJECT(f), "membus.0", 8, + i440fx_pmc_dimm_offset); + /* Initialize paravirtual memory bus */ + f->pv_dram_channel = dimm_bus_create(OBJECT(f), "membus.pv", 0, + i440fx_pmc_dimm_offset); memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space, f->below_4g_mem_size, 0x100000000LL - f->below_4g_mem_size); -- 1.7.9

1 0

[RFC PATCH v4 13/30] piix_pci and pc_piix: refactor
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

Refactor code so that chipset initialization is similar to q35. This will allow memory map initialization at chipset qdev init time for both machines, as well as more similar code structure overall. Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- hw/pc_piix.c | 57 ++++++++++++--- hw/piix_pci.c | 225 ++++++++++++++------------------------------------------- 2 files changed, 100 insertions(+), 182 deletions(-) diff --git a/hw/pc_piix.c b/hw/pc_piix.c index 19e342a..6a9b508 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -47,6 +47,7 @@ #ifdef CONFIG_XEN # include <xen/hvm/hvm_info_table.h> #endif +#include "piix_pci.h" #define MAX_IDE_BUS 2 @@ -85,6 +86,8 @@ static void pc_init1(MemoryRegion *system_memory, MemoryRegion *pci_memory; MemoryRegion *rom_memory; void *fw_cfg = NULL; + I440FXState *i440fx_host; + PIIX3State *piix3; pc_cpus_init(cpu_model); @@ -127,21 +130,53 @@ static void pc_init1(MemoryRegion *system_memory, } if (pci_enabled) { - pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, &isa_bus, gsi, - system_memory, system_io, ram_size, - below_4g_mem_size, - 0x100000000ULL - below_4g_mem_size, - 0x100000000ULL + above_4g_mem_size, - (sizeof(hwaddr) == 4 - ? 0 - : ((uint64_t)1 << 62)), - pci_memory, ram_memory); + i440fx_host = I440FX_HOST_DEVICE(qdev_create(NULL, + TYPE_I440FX_HOST_DEVICE)); + i440fx_host->mch.ram_memory = ram_memory; + i440fx_host->mch.pci_address_space = pci_memory; + i440fx_host->mch.system_memory = get_system_memory(); + i440fx_host->mch.address_space_io = get_system_io();; + i440fx_host->mch.below_4g_mem_size = below_4g_mem_size; + i440fx_host->mch.above_4g_mem_size = above_4g_mem_size; + + qdev_init_nofail(DEVICE(i440fx_host)); + i440fx_state = &i440fx_host->mch; + pci_bus = i440fx_host->parent_obj.bus; + /* Xen supports additional interrupt routes from the PCI devices to + * the IOAPIC: the four pins of each PCI device on the bus are also + * connected to the IOAPIC directly. + * These additional routes can be discovered through ACPI. */ + if (xen_enabled()) { + piix3 = DO_UPCAST(PIIX3State, dev, + pci_create_simple_multifunction(pci_bus, -1, true, + "PIIX3-xen")); + pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq, + piix3, XEN_PIIX_NUM_PIRQS); + } else { + piix3 = DO_UPCAST(PIIX3State, dev, + pci_create_simple_multifunction(pci_bus, -1, true, + "PIIX3")); + pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, piix3, + PIIX_NUM_PIRQS); + pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); + } + piix3->pic = gsi; + isa_bus = DO_UPCAST(ISABus, qbus, + qdev_get_child_bus(&piix3->dev.qdev, "isa.0")); + + piix3_devfn = piix3->dev.devfn; + + ram_size = ram_size / 8 / 1024 / 1024; + if (ram_size > 255) { + ram_size = 255; + } + i440fx_state->dev.config[0x57] = ram_size; } else { pci_bus = NULL; - i440fx_state = NULL; isa_bus = isa_bus_new(NULL, system_io); no_hpet = 1; } + isa_bus_irqs(isa_bus, gsi); if (kvm_irqchip_in_kernel()) { @@ -157,7 +192,7 @@ static void pc_init1(MemoryRegion *system_memory, gsi_state->i8259_irq[i] = i8259[i]; } if (pci_enabled) { - ioapic_init_gsi(gsi_state, "i440fx"); + ioapic_init_gsi(gsi_state, NULL); } pc_register_ferr_irq(gsi[13]); diff --git a/hw/piix_pci.c b/hw/piix_pci.c index ba1b3de..7ca3c73 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -31,70 +31,15 @@ #include "range.h" #include "xen.h" #include "pam.h" +#include "piix_pci.h" -/* - * I440FX chipset data sheet. - * http://download.intel.com/design/chipsets/datashts/29054901.pdf - */ - -typedef struct I440FXState { - PCIHostState parent_obj; -} I440FXState; - -#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ -#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ -#define XEN_PIIX_NUM_PIRQS 128ULL -#define PIIX_PIRQC 0x60 - -typedef struct PIIX3State { - PCIDevice dev; - - /* - * bitmap to track pic levels. - * The pic level is the logical OR of all the PCI irqs mapped to it - * So one PIC level is tracked by PIIX_NUM_PIRQS bits. - * - * PIRQ is mapped to PIC pins, we track it by - * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with - * pic_irq * PIIX_NUM_PIRQS + pirq - */ -#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 -#error "unable to encode pic state in 64bit in pic_levels." -#endif - uint64_t pic_levels; - - qemu_irq *pic; - - /* This member isn't used. Just for save/load compatibility */ - int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; -} PIIX3State; - -struct PCII440FXState { - PCIDevice dev; - MemoryRegion *system_memory; - MemoryRegion *pci_address_space; - MemoryRegion *ram_memory; - MemoryRegion pci_hole; - MemoryRegion pci_hole_64bit; - PAMMemoryRegion pam_regions[13]; - MemoryRegion smram_region; - uint8_t smm_enabled; -}; - - -#define I440FX_PAM 0x59 -#define I440FX_PAM_SIZE 7 -#define I440FX_SMRAM 0x72 - -static void piix3_set_irq(void *opaque, int pirq, int level); -static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx); static void piix3_write_config_xen(PCIDevice *dev, uint32_t address, uint32_t val, int len); /* return the global irq number corresponding to a given device irq pin. We could also use the bus number to have a more precise mapping. */ -static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) +int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) { int slot_addend; slot_addend = (pci_dev->devfn >> 3) - 1; @@ -180,149 +125,86 @@ static const VMStateDescription vmstate_i440fx = { } }; -static int i440fx_pcihost_initfn(SysBusDevice *dev) +static void i440fx_pcihost_initfn(Object *obj) { - PCIHostState *s = PCI_HOST_BRIDGE(dev); + I440FXState *s = I440FX_HOST_DEVICE(obj); + object_initialize(&s->mch, TYPE_I440FX_PCI_DEVICE); + object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); +} - memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s, - "pci-conf-idx", 4); - sysbus_add_io(dev, 0xcf8, &s->conf_mem); - sysbus_init_ioports(&s->busdev, 0xcf8, 4); +static int i440fx_pcihost_init(SysBusDevice *dev) +{ + PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev); + I440FXState *s = I440FX_HOST_DEVICE(&dev->qdev); + PCIBus *b; + + memory_region_init_io(&pci->conf_mem, &pci_host_conf_le_ops, pci, + "pci-conf-idx", 4); + sysbus_add_io(dev, 0xcf8, &pci->conf_mem); + sysbus_init_ioports(&pci->busdev, 0xcf8, 4); + memory_region_init_io(&pci->data_mem, &pci_host_data_le_ops, pci, + "pci-conf-data", 4); - memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s, - "pci-conf-data", 4); - sysbus_add_io(dev, 0xcfc, &s->data_mem); - sysbus_init_ioports(&s->busdev, 0xcfc, 4); + sysbus_add_io(dev, 0xcfc, &pci->data_mem); + sysbus_init_ioports(&pci->busdev, 0xcfc, 4); + + b = pci_bus_new(&s->parent_obj.busdev.qdev, NULL, s->mch.pci_address_space, + s->mch.address_space_io, 0); + s->parent_obj.bus = b; + qdev_set_parent_bus(DEVICE(&s->mch), BUS(b)); + qdev_init_nofail(DEVICE(&s->mch)); return 0; } static int i440fx_initfn(PCIDevice *dev) { - PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); + int i; + PCII440FXState *f = DO_UPCAST(PCII440FXState, dev, dev); + hwaddr pci_hole64_size; - d->dev.config[I440FX_SMRAM] = 0x02; + f->dev.config[I440FX_SMRAM] = 0x02; - cpu_smm_register(&i440fx_set_smm, d); - return 0; -} + cpu_smm_register(&i440fx_set_smm, f); -static PCIBus *i440fx_common_init(const char *device_name, - PCII440FXState **pi440fx_state, - int *piix3_devfn, - ISABus **isa_bus, qemu_irq *pic, - MemoryRegion *address_space_mem, - MemoryRegion *address_space_io, - ram_addr_t ram_size, - hwaddr pci_hole_start, - hwaddr pci_hole_size, - hwaddr pci_hole64_start, - hwaddr pci_hole64_size, - MemoryRegion *pci_address_space, - MemoryRegion *ram_memory) -{ - DeviceState *dev; - PCIBus *b; - PCIDevice *d; - PCIHostState *s; - PIIX3State *piix3; - PCII440FXState *f; - unsigned i; - - dev = qdev_create(NULL, "i440FX-pcihost"); - s = PCI_HOST_BRIDGE(dev); - s->address_space = address_space_mem; - b = pci_bus_new(dev, NULL, pci_address_space, - address_space_io, 0); - s->bus = b; - object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL); - qdev_init_nofail(dev); - - d = pci_create_simple(b, 0, device_name); - *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d); - f = *pi440fx_state; - f->system_memory = address_space_mem; - f->pci_address_space = pci_address_space; - f->ram_memory = ram_memory; + pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 : + ((uint64_t)1 << 62)); memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space, - pci_hole_start, pci_hole_size); - memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole); + f->below_4g_mem_size, + 0x100000000LL - f->below_4g_mem_size); + memory_region_add_subregion(f->system_memory, f->below_4g_mem_size, + &f->pci_hole); memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64", f->pci_address_space, - pci_hole64_start, pci_hole64_size); + 0x100000000LL + f->above_4g_mem_size, + pci_hole64_size); if (pci_hole64_size) { - memory_region_add_subregion(f->system_memory, pci_hole64_start, + memory_region_add_subregion(f->system_memory, + 0x100000000LL + f->above_4g_mem_size, &f->pci_hole_64bit); } + memory_region_init_alias(&f->smram_region, "smram-region", f->pci_address_space, 0xa0000, 0x20000); memory_region_add_subregion_overlap(f->system_memory, 0xa0000, &f->smram_region, 1); memory_region_set_enabled(&f->smram_region, false); + init_pam(f->ram_memory, f->system_memory, f->pci_address_space, &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); for (i = 0; i < 12; ++i) { init_pam(f->ram_memory, f->system_memory, f->pci_address_space, - &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, + &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); } - - /* Xen supports additional interrupt routes from the PCI devices to - * the IOAPIC: the four pins of each PCI device on the bus are also - * connected to the IOAPIC directly. - * These additional routes can be discovered through ACPI. */ - if (xen_enabled()) { - piix3 = DO_UPCAST(PIIX3State, dev, - pci_create_simple_multifunction(b, -1, true, "PIIX3-xen")); - pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq, - piix3, XEN_PIIX_NUM_PIRQS); - } else { - piix3 = DO_UPCAST(PIIX3State, dev, - pci_create_simple_multifunction(b, -1, true, "PIIX3")); - pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, - PIIX_NUM_PIRQS); - pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq); - } - piix3->pic = pic; - *isa_bus = DO_UPCAST(ISABus, qbus, - qdev_get_child_bus(&piix3->dev.qdev, "isa.0")); - - *piix3_devfn = piix3->dev.devfn; - - ram_size = ram_size / 8 / 1024 / 1024; - if (ram_size > 255) - ram_size = 255; - (*pi440fx_state)->dev.config[0x57]=ram_size; - + f->dev.config[0x57] = f->below_4g_mem_size; i440fx_update_memory_mappings(f); - return b; -} - -PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, - ISABus **isa_bus, qemu_irq *pic, - MemoryRegion *address_space_mem, - MemoryRegion *address_space_io, - ram_addr_t ram_size, - hwaddr pci_hole_start, - hwaddr pci_hole_size, - hwaddr pci_hole64_start, - hwaddr pci_hole64_size, - MemoryRegion *pci_memory, MemoryRegion *ram_memory) - -{ - PCIBus *b; - - b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, isa_bus, pic, - address_space_mem, address_space_io, ram_size, - pci_hole_start, pci_hole_size, - pci_hole64_start, pci_hole64_size, - pci_memory, ram_memory); - return b; + return 0; } /* PIIX3 PCI to ISA bridge */ -static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) +void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) { qemu_set_irq(piix3->pic[pic_irq], !!(piix3->pic_levels & @@ -347,13 +229,13 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) piix3_set_irq_pic(piix3, pic_irq); } -static void piix3_set_irq(void *opaque, int pirq, int level) +void piix3_set_irq(void *opaque, int pirq, int level) { PIIX3State *piix3 = opaque; piix3_set_irq_level(piix3, pirq, level); } -static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) +PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { PIIX3State *piix3 = opaque; int irq = piix3->dev.config[PIIX_PIRQC + pin]; @@ -550,7 +432,7 @@ static void i440fx_class_init(ObjectClass *klass, void *data) } static const TypeInfo i440fx_info = { - .name = "i440FX", + .name = TYPE_I440FX_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PCII440FXState), .class_init = i440fx_class_init, @@ -561,15 +443,16 @@ static void i440fx_pcihost_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - k->init = i440fx_pcihost_initfn; + k->init = i440fx_pcihost_init; dc->fw_name = "pci"; dc->no_user = 1; } static const TypeInfo i440fx_pcihost_info = { - .name = "i440FX-pcihost", + .name = TYPE_I440FX_HOST_DEVICE, .parent = TYPE_PCI_HOST_BRIDGE, .instance_size = sizeof(I440FXState), + .instance_init = i440fx_pcihost_initfn, .class_init = i440fx_pcihost_class_init, }; -- 1.7.9

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[RFC PATCH v4 12/30] acpi_ich9 : Implement memory device hotplug registers
by Vasilis Liaskovitis 18 Dec '12

18 Dec '12

This implements acpi dimm hot-add capability for q35 (ich9). The logic is the same as for the pc machine (piix4). TODO: Fix acpi irq delivery bug. Currently there is a flood of irqs when delivering an acpi interrupt (should be just one). Guest complains as follows: "irq 9: nobody cared [...] Disabling IRQ #9" where #9 is the acpi irq Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> --- hw/acpi_ich9.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++-- hw/acpi_ich9.h | 7 +++++- hw/lpc_ich9.c | 2 +- 3 files changed, 65 insertions(+), 5 deletions(-) diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c index c5978d3..abafbb5 100644 --- a/hw/acpi_ich9.c +++ b/hw/acpi_ich9.c @@ -48,11 +48,14 @@ static void pm_update_sci(ICH9LPCPMRegs *pm) pm1a_sts = acpi_pm1_evt_get_sts(&pm->acpi_regs); - sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) & + sci_level = ((((pm1a_sts & pm->acpi_regs.pm1.evt.en) & (ACPI_BITMASK_RT_CLOCK_ENABLE | ACPI_BITMASK_POWER_BUTTON_ENABLE | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | - ACPI_BITMASK_TIMER_ENABLE)) != 0); + ACPI_BITMASK_TIMER_ENABLE)) != 0) || + (((pm->acpi_regs.gpe.sts[0] & pm->acpi_regs.gpe.en[0]) & + (ICH9_MEM_HOTPLUG_STATUS)) != 0)); + qemu_set_irq(pm->irq, sci_level); /* schedule a timer interruption if needed */ @@ -90,6 +93,29 @@ static const MemoryRegionOps ich9_gpe_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; +static uint32_t memhp_readb(void *opaque, uint32_t addr) +{ + ICH9LPCPMRegs *s = opaque; + uint32_t val = 0; + struct gpe_regs *g = &s->gperegs; + if (addr < DIMM_BITMAP_BYTES) { + val = (uint32_t) g->mems_sts[addr]; + } + ICH9_DEBUG("memhp read %x == %x\n", addr, val); + return val; +} + +static const MemoryRegionOps ich9_memhp_ops = { + .old_portio = (MemoryRegionPortio[]) { + { + .offset = 0, .len = DIMM_BITMAP_BYTES, .size = 1, + .read = memhp_readb, + }, + PORTIO_END_OF_LIST() + }, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width) { ICH9LPCPMRegs *pm = opaque; @@ -201,8 +227,31 @@ static void pm_powerdown_req(Notifier *n, void *opaque) acpi_pm1_evt_power_down(&pm->acpi_regs); } -void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3) +static void enable_mem_device(ICH9LPCState *s, int memdevice) { + struct gpe_regs *g = &s->pm.gperegs; + s->pm.acpi_regs.gpe.sts[0] |= ICH9_MEM_HOTPLUG_STATUS; + g->mems_sts[memdevice/8] |= (1 << (memdevice%8)); +} + +static int ich9_dimm_hotplug(DeviceState *qdev, DimmDevice *dev, int + add) +{ + PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, qdev); + ICH9LPCState *s = DO_UPCAST(ICH9LPCState, d, pci_dev); + DimmDevice *slot = DIMM(dev); + + if (add) { + enable_mem_device(s, slot->idx); + } + pm_update_sci(&s->pm); + return 0; +} + +void ich9_pm_init(void *device, qemu_irq sci_irq, qemu_irq cmos_s3) +{ + ICH9LPCState *lpc = (ICH9LPCState *)device; + ICH9LPCPMRegs *pm = &lpc->pm; memory_region_init(&pm->io, "ich9-pm", ICH9_PMIO_SIZE); memory_region_set_enabled(&pm->io, false); memory_region_add_subregion(get_system_io(), 0, &pm->io); @@ -220,6 +269,12 @@ void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3) 8); memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi); + memory_region_init_io(&pm->io_memhp, &ich9_memhp_ops, pm, "apci-memhp0", + DIMM_BITMAP_BYTES); + memory_region_add_subregion(get_system_io(), ICH9_MEM_BASE, &pm->io_memhp); + + dimm_bus_hotplug(ich9_dimm_hotplug, &lpc->d.qdev); + pm->irq = sci_irq; qemu_register_reset(pm_reset, pm); pm->powerdown_notifier.notify = pm_powerdown_req; diff --git a/hw/acpi_ich9.h b/hw/acpi_ich9.h index bc221d3..4419247 100644 --- a/hw/acpi_ich9.h +++ b/hw/acpi_ich9.h @@ -23,6 +23,9 @@ #include "acpi.h" +#define ICH9_MEM_BASE 0xaf80 +#define ICH9_MEM_HOTPLUG_STATUS 8 + typedef struct ICH9LPCPMRegs { /* * In ich9 spec says that pm1_cnt register is 32bit width and @@ -33,16 +36,18 @@ typedef struct ICH9LPCPMRegs { MemoryRegion io; MemoryRegion io_gpe; MemoryRegion io_smi; + MemoryRegion io_memhp; uint32_t smi_en; uint32_t smi_sts; qemu_irq irq; /* SCI */ + struct gpe_regs gperegs; uint32_t pm_io_base; Notifier powerdown_notifier; } ICH9LPCPMRegs; -void ich9_pm_init(ICH9LPCPMRegs *pm, +void ich9_pm_init(void *lpc, qemu_irq sci_irq, qemu_irq cmos_s3_resume); void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base); extern const VMStateDescription vmstate_ich9_pm; diff --git a/hw/lpc_ich9.c b/hw/lpc_ich9.c index 878a43e..0ef7af6 100644 --- a/hw/lpc_ich9.c +++ b/hw/lpc_ich9.c @@ -352,7 +352,7 @@ void ich9_lpc_pm_init(PCIDevice *lpc_pci, qemu_irq cmos_s3) qemu_irq *sci_irq; sci_irq = qemu_allocate_irqs(ich9_set_sci, lpc, 1); - ich9_pm_init(&lpc->pm, sci_irq[0], cmos_s3); + ich9_pm_init(lpc, sci_irq[0], cmos_s3); ich9_lpc_reset(&lpc->d.qdev); } -- 1.7.9

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SeaBIOS December 2012