> +void mch_mem_addr_init(struct pci_device *dev, void *arg)
> + u64 *start = (u64 *)arg;
> + /* mmconfig space */
> + *start = Q35_HOST_BRIDGE_PCIEXBAR_ADDR +
> + Q35_HOST_BRIDGE_PCIEXBAR_SIZE;
> + mtrr_base = *start;
Ah, I see. mtrr needs to cover mmconfig too, thats why it is separate
Does that actually work? Can you create mtrr entries for 0xb0000000 ->
0xffffffff? Maybe you need two, one 0xb0000000 -> 0xbfffffff and one
0xc0000000 -> 0xffffffff.
2012/10/8 Christian Gmeiner <christian.gmeiner at gmail.com>:
> HI all
> I am running into some usb problems with coreboot & seabios:
I have similar problems with Geode GX2.
Kevin has helped me doing some debugging. (see archives)
It has been a while but i recall having memory corruptions while using
With coreboot alone i had no memory problems.
I used a patched memtest86+ for testing.
See attached patch.
You have to adapt it to LX. (see memtest86 without the +)