October 2012 - SeaBIOS - mail.coreboot.org

Re: [SeaBIOS] [PATCH v2 8/9] seabios: q35: add basic hotplug support
by Paolo Bonzini Oct. 9, 2012

Oct. 9, 2012

Il 09/10/2012 05:35, Jason Baron ha scritto: > From: Jason Baron <jbaron(a)redhat.com> > > Add support for acpi hotplug to q35. Copied from the piix acpi table. > > Signed-off-by: Jason Baron <jbaron(a)redhat.com> Reviewed-by: Paolo Bonzini <pbonzini(a)redhat.com> > --- > src/q35-acpi-dsdt.dsl | 61 +++++++++++++++++++++++++++++++++++++++++++++---- > 1 files changed, 56 insertions(+), 5 deletions(-) > > diff --git a/src/q35-acpi-dsdt.dsl b/src/q35-acpi-dsdt.dsl > index 4e16d24..fb62323 100644 > --- a/src/q35-acpi-dsdt.dsl > +++ b/src/q35-acpi-dsdt.dsl > @@ -83,6 +83,21 @@ DefinitionBlock ( > Name (_ADR, 0x00) > Name (_UID, 1) > > + > + OperationRegion(PCST, SystemIO, 0xae00, 0x08) > + Field (PCST, DWordAcc, NoLock, WriteAsZeros) > + { > + PCIU, 32, > + PCID, 32, > + } > + > + OperationRegion(SEJ, SystemIO, 0xae08, 0x04) > + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) > + { > + B0EJ, 32, > + } > + > + > // _OSC: based on sample of ACPI3.0b spec > Name(SUPP,0) // PCI _OSC Support Field value > Name(CTRL,0) // PCI _OSC Control Field value > @@ -872,6 +887,41 @@ DefinitionBlock ( > } > } > > +/**************************************************************** > + * PCI hotplug > + ****************************************************************/ > + > + Scope(\_SB.PCI0) { > + /* Methods called by bulk generated PCI devices below */ > + > + /* Methods called by hotplug devices */ > + Method (PCEJ, 1, NotSerialized) { > + // _EJ0 method - eject callback > + Store(ShiftLeft(1, Arg0), B0EJ) > + Return (0x0) > + } > + > + /* Hotplug notification method supplied by SSDT */ > + External (\_SB.PCI0.PCNT, MethodObj) > + > + /* PCI hotplug notify method */ > + Method(PCNF, 0) { > + // Local0 = iterator > + Store (Zero, Local0) > + While (LLess(Local0, 31)) { > + Increment(Local0) > + If (And(PCIU, ShiftLeft(1, Local0))) { > + PCNT(Local0, 1) > + } > + If (And(PCID, ShiftLeft(1, Local0))) { > + PCNT(Local0, 3) > + } > + } > + Return(One) > + } > + > + } > + > Scope (\_GPE) > { > Name(_HID, "ACPI0006") > @@ -879,12 +929,13 @@ DefinitionBlock ( > Method(_L00) { > Return(0x01) > } > - Method(_L01) { > - // CPU hotplug event > - Return(\_SB.PRSC()) > + Method(_E01) { > + // PCI hotplug event > + Return(\_SB.PCI0.PCNF()) > } > - Method(_L02) { > - Return(0x01) > + Method(_E02) { > + // CPU hotplug event > + Return(\_SB.PRSC()) > } > Method(_L03) { > Return(0x01) >

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Re: [SeaBIOS] [PATCH v2 7/9] seabios: q35: Register PCI IRQs as active high in APIC mode
by Paolo Bonzini Oct. 9, 2012

Oct. 9, 2012

Il 09/10/2012 05:35, Jason Baron ha scritto: > From: Jan Kiszka <jan.kiszka(a)siemens.com> > > Seems important for Windows. > > Signed-off-by: Jan Kiszka <jan.kiszka(a)siemens.com> > Signed-off-by: Jason Baron <jbaron(a)redhat.com> Reviewed-by: Paolo Bonzini <pbonzini(a)redhat.com> > --- > src/q35-acpi-dsdt.dsl | 46 +++++++++++++++++++++++++++++++++------------- > 1 files changed, 33 insertions(+), 13 deletions(-) > > diff --git a/src/q35-acpi-dsdt.dsl b/src/q35-acpi-dsdt.dsl > index c9fa5c6..4e16d24 100644 > --- a/src/q35-acpi-dsdt.dsl > +++ b/src/q35-acpi-dsdt.dsl > @@ -161,19 +161,10 @@ DefinitionBlock ( > #define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG) > > #define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \ > - Package() { nr##ffff, 0, 0, gsi0 }, \ > - Package() { nr##ffff, 1, 0, gsi1 }, \ > - Package() { nr##ffff, 2, 0, gsi2 }, \ > - Package() { nr##ffff, 3, 0, gsi3 } > - > -#define GSIA 0x10 > -#define GSIB 0x11 > -#define GSIC 0x12 > -#define GSID 0x13 > -#define GSIE 0x14 > -#define GSIF 0x15 > -#define GSIG 0x16 > -#define GSIH 0x17 > + Package() { nr##ffff, 0, gsi0, 0 }, \ > + Package() { nr##ffff, 1, gsi1, 0 }, \ > + Package() { nr##ffff, 2, gsi2, 0 }, \ > + Package() { nr##ffff, 3, gsi3, 0 } > > #define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID) > #define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA) > @@ -778,6 +769,35 @@ DefinitionBlock ( > define_link(LNKF, 5, \_SB.PCI0.LPC.PRQF) > define_link(LNKG, 6, \_SB.PCI0.LPC.PRQG) > define_link(LNKH, 7, \_SB.PCI0.LPC.PRQH) > + > +#define define_gsi_link(link, uid, gsi) \ > + Device(link){ \ > + Name(_HID, EISAID("PNP0C0F")) \ > + Name(_UID, uid) \ > + Name(_PRS, ResourceTemplate() { \ > + Interrupt (, Level, ActiveHigh, \ > + Shared) \ > + { gsi } \ > + }) \ > + Method (_CRS, 0, NotSerialized) \ > + { \ > + Return (ResourceTemplate () { \ > + Interrupt (, Level, ActiveHigh, \ > + Shared) \ > + { gsi } \ > + }) \ > + } \ > + Method (_SRS, 1, NotSerialized) { } \ > + } \ > + > + define_gsi_link(GSIA, 0, 0x10) > + define_gsi_link(GSIB, 0, 0x11) > + define_gsi_link(GSIC, 0, 0x12) > + define_gsi_link(GSID, 0, 0x13) > + define_gsi_link(GSIE, 0, 0x14) > + define_gsi_link(GSIF, 0, 0x15) > + define_gsi_link(GSIG, 0, 0x16) > + define_gsi_link(GSIH, 0, 0x17) > } > > /* CPU hotplug */ >

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Re: [SeaBIOS] [PATCH v2 4/9] seabios: pci: enable SERR of normal device.
by Paolo Bonzini Oct. 9, 2012

Oct. 9, 2012

Il 09/10/2012 05:35, Jason Baron ha scritto: > From: Isaku Yamahata <yamahata(a)valinux.co.jp> > > enable SERR of normal device for AER. > > Signed-off-by: Isaku Yamahata <yamahata(a)valinux.co.jp> > Signed-off-by: Jason Baron <jbaron(a)redhat.com> Reviewed-by: Paolo Bonzini <pbonzini(a)redhat.com> > --- > src/pciinit.c | 3 ++- > 1 files changed, 2 insertions(+), 1 deletions(-) > > diff --git a/src/pciinit.c b/src/pciinit.c > index 0b4a9e4..7e76379 100644 > --- a/src/pciinit.c > +++ b/src/pciinit.c > @@ -218,7 +218,8 @@ static void pci_bios_init_device(struct pci_device *pci) > pci_init_device(pci_class_tbl, pci, NULL); > > /* enable memory mappings */ > - pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY); > + pci_config_maskw(bdf, PCI_COMMAND, 0, > + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR); > > /* map the interrupt */ > int pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN); >

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Re: [SeaBIOS] [PATCH v2 3/9] seabios: acpi, fadt: make while fadt initialization chipset specific
by Paolo Bonzini Oct. 9, 2012

Oct. 9, 2012

Il 09/10/2012 05:35, Jason Baron ha scritto: > From: Isaku Yamahata <yamahata(a)valinux.co.jp> > > make while fadt initialization chipset specific. > > Signed-off-by: Isaku Yamahata <yamahata(a)valinux.co.jp> > Signed-off-by: Jason Baron <jbaron(a)redhat.com> I wonder if long term we want to build as much ACPI stuff in QEMU as possible (so mch_mcfg_init would actually *consume* the MCFG instead of producing it). Reviewed-by: Paolo Bonzini <pbonzini(a)redhat.com> > --- > src/acpi.c | 34 ++++++++++++++++++---------------- > 1 files changed, 18 insertions(+), 16 deletions(-) > > diff --git a/src/acpi.c b/src/acpi.c > index 780c0ac..3577c70 100644 > --- a/src/acpi.c > +++ b/src/acpi.c > @@ -234,13 +234,31 @@ build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev) > #define PIIX4_GPE0_BLK 0xafe0 > #define PIIX4_GPE0_BLK_LEN 4 > > +#define PIIX4_PM_INTRRUPT 9 // irq 9 > + > static void piix4_fadt_init(struct pci_device *pci, void *arg) > { > struct fadt_descriptor_rev1 *fadt = arg; > + > + fadt->model = 1; > + fadt->reserved1 = 0; > + fadt->sci_int = cpu_to_le16(PIIX4_PM_INTRRUPT); > + fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD); > fadt->acpi_enable = PIIX4_ACPI_ENABLE; > fadt->acpi_disable = PIIX4_ACPI_DISABLE; > + fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE); > + fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04); > + fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08); > fadt->gpe0_blk = cpu_to_le32(PIIX4_GPE0_BLK); > + fadt->pm1_evt_len = 4; > + fadt->pm1_cnt_len = 2; > + fadt->pm_tmr_len = 4; > fadt->gpe0_blk_len = PIIX4_GPE0_BLK_LEN; > + fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported > + fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported > + /* WBINVD + PROC_C1 + SLP_BUTTON + RTC_S4 + USE_PLATFORM_CLOCK */ > + fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 7) | > + (1 << 15)); > } > > static const struct pci_device_id fadt_init_tbl[] = { > @@ -282,23 +300,7 @@ build_fadt(struct pci_device *pci) > fadt->firmware_ctrl = cpu_to_le32((u32)facs); > fadt->dsdt = 0; /* dsdt will be filled later in acpi_bios_init() > by fill_dsdt() */ > - fadt->model = 1; > - fadt->reserved1 = 0; > - int pm_sci_int = pci_config_readb(pci->bdf, PCI_INTERRUPT_LINE); > - fadt->sci_int = cpu_to_le16(pm_sci_int); > - fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD); > - fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE); > - fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04); > - fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08); > - fadt->pm1_evt_len = 4; > - fadt->pm1_cnt_len = 2; > - fadt->pm_tmr_len = 4; > - fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported > - fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported > pci_init_device(fadt_init_tbl, pci, fadt); > - /* WBINVD + PROC_C1 + SLP_BUTTON + RTC_S4 + USE_PLATFORM_CLOCK */ > - fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 7) | > - (1 << 15)); > > build_header((void*)fadt, FACP_SIGNATURE, sizeof(*fadt), 1); > >

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Re: [SeaBIOS] [PATCH v2 2/9] seabios: acpi: add mcfg table.
by Paolo Bonzini Oct. 9, 2012

Oct. 9, 2012

Il 09/10/2012 05:35, Jason Baron ha scritto: > From: Isaku Yamahata <yamahata(a)valinux.co.jp> > > add mcfg table. > mcfg isn't populated at the moment. dev-q35 will use it later. > > [jbaron(a)redhat.com: moved header from post.h -> acpi.h] > Signed-off-by: Isaku Yamahata <yamahata(a)valinux.co.jp> > Signed-off-by: Jason Baron <jbaron(a)redhat.com> Reviewed-by: Paolo Bonzini <pbonzini(a)redhat.com> > --- > src/acpi.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > src/acpi.h | 17 ++++++++++++++ > 2 files changed, 90 insertions(+), 0 deletions(-) > > diff --git a/src/acpi.c b/src/acpi.c > index 6d239fa..780c0ac 100644 > --- a/src/acpi.c > +++ b/src/acpi.c > @@ -13,6 +13,7 @@ > #include "pci_regs.h" // PCI_INTERRUPT_LINE > #include "ioport.h" // inl > #include "paravirt.h" // qemu_cfg_irq0_override > +#include "memmap.h" > > /****************************************************/ > /* ACPI tables init */ > @@ -734,6 +735,77 @@ build_srat(void) > return srat; > } > > +struct acpi_mcfg > +{ > + u32 nr; > + struct acpi_table_mcfg *mcfg; > + struct e820entry *e820; > +}; > + > +static const struct pci_device_id mcfg_find_tbl[] = { > + PCI_DEVICE_END, > +}; > + > +static const struct pci_device_id mcfg_init_tbl[] = { > + PCI_DEVICE_END, > +}; > + > +static void * > +build_mcfg(void) > +{ > + struct pci_device *dev; > + int bdf; > + > + struct acpi_mcfg acpi_mcfg = { > + .nr = 0, > + .mcfg = NULL, > + .e820 = NULL, > + }; > + dev = pci_find_init_device(mcfg_find_tbl, &acpi_mcfg); > + bdf = dev->bdf; > + if (bdf < 0) { > + return NULL; > + } > + if (acpi_mcfg.nr == 0) { > + return NULL; > + } > + > + struct acpi_table_mcfg *mcfg; > + int len = sizeof(*mcfg) + acpi_mcfg.nr * sizeof(mcfg->allocation[0]); > + mcfg = malloc_high(len); > + if (!mcfg) { > + dprintf(1, "Not enough memory for mcfg table!\n"); > + return NULL; > + } > + memset(mcfg, 0, len); > + acpi_mcfg.mcfg = mcfg; > + > + > + struct e820entry *e820; > + int e820_len = acpi_mcfg.nr * sizeof(*e820); > + e820 = malloc_tmphigh(e820_len); > + if (!e820) { > + dprintf(1, "Not enough memory for e820 table!\n"); > + free(mcfg); > + return NULL; > + } > + memset(e820, 0, e820_len); > + acpi_mcfg.e820 = e820; > + > + pci_init_device(mcfg_init_tbl, dev, &acpi_mcfg); > + > + /* Linux checks if e820 covers mcfg area as reserved. > + * If no, Linux thinks bios is buggy and won't use MCFG */ > + int i; > + for (i = 0; i < acpi_mcfg.nr; i++) { > + add_e820(e820[i].start, e820[i].size, E820_RESERVED); > + } > + free(e820); > + > + build_header((void *)mcfg, MCFG_SIGNATURE, len, 1); > + return mcfg; > +} > + > static const struct pci_device_id acpi_find_tbl[] = { > /* PIIX4 Power Management device. */ > PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL), > @@ -774,6 +846,7 @@ acpi_bios_init(void) > ACPI_INIT_TABLE(build_madt()); > ACPI_INIT_TABLE(build_hpet()); > ACPI_INIT_TABLE(build_srat()); > + ACPI_INIT_TABLE(build_mcfg()); > > u16 i, external_tables = qemu_cfg_acpi_additional_tables(); > > diff --git a/src/acpi.h b/src/acpi.h > index cb21561..715d19d 100644 > --- a/src/acpi.h > +++ b/src/acpi.h > @@ -107,4 +107,21 @@ struct bfld { > u64 p1l; /* pci window 1 (above 4g) - length */ > } PACKED; > > +/* PCI fw r3.0 MCFG table. */ > +/* Subtable */ > +struct acpi_mcfg_allocation { > + u64 address; /* Base address, processor-relative */ > + u16 pci_segment; /* PCI segment group number */ > + u8 start_bus_number; /* Starting PCI Bus number */ > + u8 end_bus_number; /* Final PCI Bus number */ > + u32 reserved; > +} PACKED; > + > +#define MCFG_SIGNATURE 0x4746434d // MCFG > +struct acpi_table_mcfg { > + ACPI_TABLE_HEADER_DEF; > + u8 reserved[8]; > + struct acpi_mcfg_allocation allocation[0]; > +} PACKED; > + > #endif // acpi.h >

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Re: [SeaBIOS] [PATCH v2 5/9] seabios: add q35 initialization functions.
by Gerd Hoffmann Oct. 9, 2012

Oct. 9, 2012

Hi, > +void mch_mem_addr_init(struct pci_device *dev, void *arg) > +{ > + u64 *start = (u64 *)arg; > + /* mmconfig space */ > + *start = Q35_HOST_BRIDGE_PCIEXBAR_ADDR + > + Q35_HOST_BRIDGE_PCIEXBAR_SIZE; > + mtrr_base = *start; > +} Ah, I see. mtrr needs to cover mmconfig too, thats why it is separate from pcimem_start. Does that actually work? Can you create mtrr entries for 0xb0000000 -> 0xffffffff? Maybe you need two, one 0xb0000000 -> 0xbfffffff and one 0xc0000000 -> 0xffffffff. cheers, Gerd

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Re: [SeaBIOS] USB Problems geode lx800
by Nils Oct. 8, 2012

Oct. 8, 2012

Hi Christian, 2012/10/8 Christian Gmeiner <christian.gmeiner at gmail.com>: > HI all > > I am running into some usb problems with coreboot & seabios: I have similar problems with Geode GX2. Kevin has helped me doing some debugging. (see archives) It has been a while but i recall having memory corruptions while using SeaBIOS. With coreboot alone i had no memory problems. I used a patched memtest86+ for testing. See attached patch. You have to adapt it to LX. (see memtest86 without the +) Succes, Nils.

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Re: [SeaBIOS] USB Problems geode lx800
by Christian Gmeiner Oct. 8, 2012

Oct. 8, 2012

2012/10/8 Christian Gmeiner <christian.gmeiner(a)gmail.com>: > 2012/10/8 Christian Gmeiner <christian.gmeiner(a)gmail.com>: >> HI all >> >> I am running into some usb problems with coreboot & seabios: >> >> >> init usb >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=72 align=10 >> ret=0x1f7a8860 (detail=0x1f7a88b0) >> EHCI init on dev 00:0f.5 (regs=0xfe038010) >> pmm_malloc zone=0x1f7afe83 handle=ffffffff size=4096 align=1000 >> ret=0x1f7bf000 (detail=0x1f7a8830) >> pmm_malloc zone=0x1f7afe83 handle=ffffffff size=68 align=80 >> ret=0x1f7bef80 (detail=0x1f7a8800) >> pmm_malloc zone=0x1f7afe83 handle=ffffffff size=68 align=80 >> ret=0x1f7bef00 (detail=0x1f7a87d0) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 >> ret=0x1f7a8780 (detail=0x1f7a87a0) >> pmm_free 0x1f7a8780 (detail=0x1f7a87a0) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 >> ret=0x1f7a8780 (detail=0x1f7a87a0) >> set_address 0x1f7a8860 >> ehci_alloc_async_pipe 0x1f7a8860 0 >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=92 align=80 >> ret=0x1f7a8680 (detail=0x1f7a8750) >> ehci_control 0x1f7a86d0 (dir=0 cmd=8 data=0) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 >> ret=0x1f7a85c0 (detail=0x1f7a8720) >> pmm_free 0x1f7a85c0 (detail=0x1f7a8720) >> ehci_alloc_async_pipe 0x1f7a8860 0 >> config_usb: 0x1f7a86d0 >> ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=8) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 >> ret=0x1f7a85c0 (detail=0x1f7a8720) >> pmm_free 0x1f7a85c0 (detail=0x1f7a8720) >> device rev=0200 cls=00 sub=00 proto=00 size=40 >> ehci_alloc_async_pipe 0x1f7a8860 0 >> ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=9) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 >> ret=0x1f7a85c0 (detail=0x1f7a8720) >> pmm_free 0x1f7a85c0 (detail=0x1f7a8720) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=32 align=10 >> ret=0x1f7a8700 (detail=0x1f7a8720) >> ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=32) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 >> ret=0x1f7a8580 (detail=0x1f7a8650) >> pmm_free 0x1f7a8580 (detail=0x1f7a8650) >> ehci_control 0x1f7a86d0 (dir=0 cmd=8 data=0) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 >> ret=0x1f7a8580 (detail=0x1f7a8650) >> pmm_free 0x1f7a8580 (detail=0x1f7a8650) >> ehci_alloc_async_pipe 0x1f7a8860 2 >> pmm_malloc zone=0x1f7afe77 handle=ffffffff size=92 align=80 >> ret=0x000ef700 (detail=0x1f7a8650) >> ehci_alloc_async_pipe 0x1f7a8860 2 >> pmm_malloc zone=0x1f7afe77 handle=ffffffff size=92 align=80 >> ret=0x000ef680 (detail=0x1f7a8620) >> ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=1) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 >> ret=0x1f7a8500 (detail=0x1f7a85f0) >> pmm_free 0x1f7a8500 (detail=0x1f7a85f0) >> pmm_malloc zone=0x1f7afe7b handle=ffffffff size=48 align=10 >> ret=0x000fdb30 (detail=0x1f7a85f0) >> Searching bootorder for: /pci@i0cf8/usb@f,5/storage@2/*@0/*@0,0 >> Searching bootorder for: /pci@i0cf8/usb@f,5/usb-*@2 >> ehci_send_bulk qh=0x000ef680 dir=0 data=0x00006d55 size=31 >> ehci_send_bulk qh=0x000ef700 dir=128 data=0x00006e3c size=36 >> ehci_send_bulk qh=0x000ef700 dir=128 data=0x00006d8f size=13 >> WARNING - Timeout at ehci_wait_td:542! >> ehci pipe=0x000ef700 cur=00000000 tok=00000000 next=6b80 td=0x00006b80 >> status=d0d80 >> USB transmission failed >> Unable to configure USB MSC drive. >> pmm_free 0x000fdb30 (detail=0x1f7a85f0) >> Unable to configure USB MSC device. >> pmm_free 0x1f7a8700 (detail=0x1f7a8720) >> pmm_free 0x1f7a8780 (detail=0x1f7a87a0) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 >> ret=0x1f7a8780 (detail=0x1f7a87a0) >> pmm_free 0x1f7a8780 (detail=0x1f7a87a0) >> pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 >> ret=0x1f7a8780 (detail=0x1f7a87a0) >> pmm_free 0x1f7a8780 (detail=0x1f7a87a0) >> ehci_free_pipes 0x1f7a8860 >> pmm_free 0x1f7a8680 (detail=0x1f7a8750) >> pmm_free 0x000ef680 (detail=0x1f7a8620) >> pmm_free 0x000ef700 (detail=0x1f7a8650) >> pmm_free 0x1f7bf000 (detail=0x1f7a8830) >> pmm_free 0x1f7bef80 (detail=0x1f7a8800) >> pmm_free 0x1f7bef00 (detail=0x1f7a87d0) >> pmm_free 0x1f7a8860 (detail=0x1f7a88b0) >> init serial >> Found 2 serial ports >> init hard drives >> >> Mabye somebody has some hints how to start debugging this and what I >> should look for. >> > added some debug to seabios: > http://dpaste.com/811158/ > > and tired my luck with FILO (using libpayload from coreboot): > http://dpaste.com/811165/ > I can boot with FILO from usb successfully into Linux --- Christian Gmeiner, MSc

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Re: [SeaBIOS] USB Problems geode lx800
by Christian Gmeiner Oct. 8, 2012

Oct. 8, 2012

2012/10/8 Christian Gmeiner <christian.gmeiner(a)gmail.com>: > HI all > > I am running into some usb problems with coreboot & seabios: > > > init usb > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=72 align=10 > ret=0x1f7a8860 (detail=0x1f7a88b0) > EHCI init on dev 00:0f.5 (regs=0xfe038010) > pmm_malloc zone=0x1f7afe83 handle=ffffffff size=4096 align=1000 > ret=0x1f7bf000 (detail=0x1f7a8830) > pmm_malloc zone=0x1f7afe83 handle=ffffffff size=68 align=80 > ret=0x1f7bef80 (detail=0x1f7a8800) > pmm_malloc zone=0x1f7afe83 handle=ffffffff size=68 align=80 > ret=0x1f7bef00 (detail=0x1f7a87d0) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 > ret=0x1f7a8780 (detail=0x1f7a87a0) > pmm_free 0x1f7a8780 (detail=0x1f7a87a0) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 > ret=0x1f7a8780 (detail=0x1f7a87a0) > set_address 0x1f7a8860 > ehci_alloc_async_pipe 0x1f7a8860 0 > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=92 align=80 > ret=0x1f7a8680 (detail=0x1f7a8750) > ehci_control 0x1f7a86d0 (dir=0 cmd=8 data=0) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 > ret=0x1f7a85c0 (detail=0x1f7a8720) > pmm_free 0x1f7a85c0 (detail=0x1f7a8720) > ehci_alloc_async_pipe 0x1f7a8860 0 > config_usb: 0x1f7a86d0 > ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=8) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 > ret=0x1f7a85c0 (detail=0x1f7a8720) > pmm_free 0x1f7a85c0 (detail=0x1f7a8720) > device rev=0200 cls=00 sub=00 proto=00 size=40 > ehci_alloc_async_pipe 0x1f7a8860 0 > ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=9) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 > ret=0x1f7a85c0 (detail=0x1f7a8720) > pmm_free 0x1f7a85c0 (detail=0x1f7a8720) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=32 align=10 > ret=0x1f7a8700 (detail=0x1f7a8720) > ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=32) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 > ret=0x1f7a8580 (detail=0x1f7a8650) > pmm_free 0x1f7a8580 (detail=0x1f7a8650) > ehci_control 0x1f7a86d0 (dir=0 cmd=8 data=0) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 > ret=0x1f7a8580 (detail=0x1f7a8650) > pmm_free 0x1f7a8580 (detail=0x1f7a8650) > ehci_alloc_async_pipe 0x1f7a8860 2 > pmm_malloc zone=0x1f7afe77 handle=ffffffff size=92 align=80 > ret=0x000ef700 (detail=0x1f7a8650) > ehci_alloc_async_pipe 0x1f7a8860 2 > pmm_malloc zone=0x1f7afe77 handle=ffffffff size=92 align=80 > ret=0x000ef680 (detail=0x1f7a8620) > ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=1) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 > ret=0x1f7a8500 (detail=0x1f7a85f0) > pmm_free 0x1f7a8500 (detail=0x1f7a85f0) > pmm_malloc zone=0x1f7afe7b handle=ffffffff size=48 align=10 > ret=0x000fdb30 (detail=0x1f7a85f0) > Searching bootorder for: /pci@i0cf8/usb@f,5/storage@2/*@0/*@0,0 > Searching bootorder for: /pci@i0cf8/usb@f,5/usb-*@2 > ehci_send_bulk qh=0x000ef680 dir=0 data=0x00006d55 size=31 > ehci_send_bulk qh=0x000ef700 dir=128 data=0x00006e3c size=36 > ehci_send_bulk qh=0x000ef700 dir=128 data=0x00006d8f size=13 > WARNING - Timeout at ehci_wait_td:542! > ehci pipe=0x000ef700 cur=00000000 tok=00000000 next=6b80 td=0x00006b80 > status=d0d80 > USB transmission failed > Unable to configure USB MSC drive. > pmm_free 0x000fdb30 (detail=0x1f7a85f0) > Unable to configure USB MSC device. > pmm_free 0x1f7a8700 (detail=0x1f7a8720) > pmm_free 0x1f7a8780 (detail=0x1f7a87a0) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 > ret=0x1f7a8780 (detail=0x1f7a87a0) > pmm_free 0x1f7a8780 (detail=0x1f7a87a0) > pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 > ret=0x1f7a8780 (detail=0x1f7a87a0) > pmm_free 0x1f7a8780 (detail=0x1f7a87a0) > ehci_free_pipes 0x1f7a8860 > pmm_free 0x1f7a8680 (detail=0x1f7a8750) > pmm_free 0x000ef680 (detail=0x1f7a8620) > pmm_free 0x000ef700 (detail=0x1f7a8650) > pmm_free 0x1f7bf000 (detail=0x1f7a8830) > pmm_free 0x1f7bef80 (detail=0x1f7a8800) > pmm_free 0x1f7bef00 (detail=0x1f7a87d0) > pmm_free 0x1f7a8860 (detail=0x1f7a88b0) > init serial > Found 2 serial ports > init hard drives > > Mabye somebody has some hints how to start debugging this and what I > should look for. > added some debug to seabios: http://dpaste.com/811158/ and tired my luck with FILO (using libpayload from coreboot): http://dpaste.com/811165/ --- Christian Gmeiner, MSc

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USB Problems geode lx800
by Christian Gmeiner Oct. 8, 2012

Oct. 8, 2012

HI all I am running into some usb problems with coreboot & seabios: init usb pmm_malloc zone=0x1f7afe7f handle=ffffffff size=72 align=10 ret=0x1f7a8860 (detail=0x1f7a88b0) EHCI init on dev 00:0f.5 (regs=0xfe038010) pmm_malloc zone=0x1f7afe83 handle=ffffffff size=4096 align=1000 ret=0x1f7bf000 (detail=0x1f7a8830) pmm_malloc zone=0x1f7afe83 handle=ffffffff size=68 align=80 ret=0x1f7bef80 (detail=0x1f7a8800) pmm_malloc zone=0x1f7afe83 handle=ffffffff size=68 align=80 ret=0x1f7bef00 (detail=0x1f7a87d0) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 ret=0x1f7a8780 (detail=0x1f7a87a0) pmm_free 0x1f7a8780 (detail=0x1f7a87a0) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 ret=0x1f7a8780 (detail=0x1f7a87a0) set_address 0x1f7a8860 ehci_alloc_async_pipe 0x1f7a8860 0 pmm_malloc zone=0x1f7afe7f handle=ffffffff size=92 align=80 ret=0x1f7a8680 (detail=0x1f7a8750) ehci_control 0x1f7a86d0 (dir=0 cmd=8 data=0) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 ret=0x1f7a85c0 (detail=0x1f7a8720) pmm_free 0x1f7a85c0 (detail=0x1f7a8720) ehci_alloc_async_pipe 0x1f7a8860 0 config_usb: 0x1f7a86d0 ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=8) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 ret=0x1f7a85c0 (detail=0x1f7a8720) pmm_free 0x1f7a85c0 (detail=0x1f7a8720) device rev=0200 cls=00 sub=00 proto=00 size=40 ehci_alloc_async_pipe 0x1f7a8860 0 ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=9) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 ret=0x1f7a85c0 (detail=0x1f7a8720) pmm_free 0x1f7a85c0 (detail=0x1f7a8720) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=32 align=10 ret=0x1f7a8700 (detail=0x1f7a8720) ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=32) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 ret=0x1f7a8580 (detail=0x1f7a8650) pmm_free 0x1f7a8580 (detail=0x1f7a8650) ehci_control 0x1f7a86d0 (dir=0 cmd=8 data=0) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 ret=0x1f7a8580 (detail=0x1f7a8650) pmm_free 0x1f7a8580 (detail=0x1f7a8650) ehci_alloc_async_pipe 0x1f7a8860 2 pmm_malloc zone=0x1f7afe77 handle=ffffffff size=92 align=80 ret=0x000ef700 (detail=0x1f7a8650) ehci_alloc_async_pipe 0x1f7a8860 2 pmm_malloc zone=0x1f7afe77 handle=ffffffff size=92 align=80 ret=0x000ef680 (detail=0x1f7a8620) ehci_control 0x1f7a86d0 (dir=128 cmd=8 data=1) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=192 align=40 ret=0x1f7a8500 (detail=0x1f7a85f0) pmm_free 0x1f7a8500 (detail=0x1f7a85f0) pmm_malloc zone=0x1f7afe7b handle=ffffffff size=48 align=10 ret=0x000fdb30 (detail=0x1f7a85f0) Searching bootorder for: /pci@i0cf8/usb@f,5/storage@2/*@0/*@0,0 Searching bootorder for: /pci@i0cf8/usb@f,5/usb-*@2 ehci_send_bulk qh=0x000ef680 dir=0 data=0x00006d55 size=31 ehci_send_bulk qh=0x000ef700 dir=128 data=0x00006e3c size=36 ehci_send_bulk qh=0x000ef700 dir=128 data=0x00006d8f size=13 WARNING - Timeout at ehci_wait_td:542! ehci pipe=0x000ef700 cur=00000000 tok=00000000 next=6b80 td=0x00006b80 status=d0d80 USB transmission failed Unable to configure USB MSC drive. pmm_free 0x000fdb30 (detail=0x1f7a85f0) Unable to configure USB MSC device. pmm_free 0x1f7a8700 (detail=0x1f7a8720) pmm_free 0x1f7a8780 (detail=0x1f7a87a0) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 ret=0x1f7a8780 (detail=0x1f7a87a0) pmm_free 0x1f7a8780 (detail=0x1f7a87a0) pmm_malloc zone=0x1f7afe7f handle=ffffffff size=28 align=10 ret=0x1f7a8780 (detail=0x1f7a87a0) pmm_free 0x1f7a8780 (detail=0x1f7a87a0) ehci_free_pipes 0x1f7a8860 pmm_free 0x1f7a8680 (detail=0x1f7a8750) pmm_free 0x000ef680 (detail=0x1f7a8620) pmm_free 0x000ef700 (detail=0x1f7a8650) pmm_free 0x1f7bf000 (detail=0x1f7a8830) pmm_free 0x1f7bef80 (detail=0x1f7a8800) pmm_free 0x1f7bef00 (detail=0x1f7a87d0) pmm_free 0x1f7a8860 (detail=0x1f7a88b0) init serial Found 2 serial ports init hard drives Mabye somebody has some hints how to start debugging this and what I should look for. --- Christian Gmeiner, MSc

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