SeaBIOS November 2011

seabios@seabios.org

22 participants
31 discussions

Re: [SeaBIOS] PCI Option ROM debugging with Coreboot+SeaBIOS (detailed steps)
by WangXiao 14 Nov '11

14 Nov '11

That's a good way for debugging, ...I have a question, can SeaBIOS use on real board seperatly without Coreboot? Thanks! > Date: Sat, 12 Nov 2011 15:41:15 +0700 > From: darmawan.salihun(a)gmail.com > To: coreboot(a)coreboot.org > CC: seabios(a)seabios.org > Subject: [SeaBIOS] PCI Option ROM debugging with Coreboot+SeaBIOS (detailed steps) > > I made a blogpost detailing the steps to debug PCI Option ROM with > Coreboot+SeaBIOS and a GDB-server-compatible debugger: > > http://bioshacking.blogspot.com/search/label/PCI%20Option%20ROM > > Hopefully would help those in need because it takes quite a while to > get it right. > Thanks to Kevin O'Connor for the helps :-) > > Regards, > > Darmawan > -- > -------------------------------------------------------------------- > -= Human knowledge belongs to the world =- > > _______________________________________________ > SeaBIOS mailing list > SeaBIOS(a)seabios.org > http://www.seabios.org/mailman/listinfo/seabios

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Re: [SeaBIOS] [PATCH] SeaBIOS/Xen: Compute the low RAM memory size in the BDA according to the e820
by Kevin O'Connor 14 Nov '11

14 Nov '11

On Mon, Nov 14, 2011 at 01:50:05AM +0000, Julian Pidancet wrote: > Some programs or ROMs like iPXE rely on the memory size field present > in the BDA instead of e820 to relocate sections at the end of the low > memory. > Xen's hvmloader places an ACPI info table at 0x9F000 at the end of the > usable RAM in low memory (just before the EBDA). The e820 table gets > altered accordingly to protect the area where the table lives, but a ROM > like iPXE only takes into account the memory size field in the BDA and > consequently corrupts the table when relocating itself. That wont work reliably - SeaBIOS (and option roms) can grow the EBDA. It's not realistic to put a whole in the middle of the first 640k. [...] > diff --git a/src/memmap.c b/src/memmap.c > index 20ccae0..36750f5 100644 > --- a/src/memmap.c > +++ b/src/memmap.c > @@ -7,6 +7,7 @@ > #include "memmap.h" // struct e820entry > #include "util.h" // dprintf.h > #include "biosvar.h" // SET_EBDA > +#include "config.h" // CONFIG_* > > > /**************************************************************** > @@ -133,6 +134,34 @@ add_e820(u64 start, u64 size, u32 type) > //dump_map(); > } > > +// Try to find the size of the usable RAM memory in the > +// first megabyte of RAM. > +u32 > +get_lowram_size(void) > +{ > + u32 lowram_end = 0; > + > + int i; > + for (i=0; i<e820_count; i++) { > + struct e820entry *e = &e820_list[i]; > + u64 e_end = e->start + e->size; > + > + if (e->type != E820_RAM) > + continue; > + > + if (e_end <= 0x100000 && /* 1M */ > + e_end > lowram_end) Shouldn't this read (e_end <= BUILD_LOWRAM_END)? Otherwise, if for some strange reason an e820 entry pointed to ram above 0xa0000 but below 1meg, it would break things. [...] > --- a/src/post.c > +++ b/src/post.c > @@ -82,18 +82,21 @@ init_bda(void) > struct bios_data_area_s *bda = MAKE_FLATPTR(SEG_BDA, 0); > memset(bda, 0, sizeof(*bda)); > > - int esize = EBDA_SIZE_START; > - SET_BDA(mem_size_kb, BUILD_LOWRAM_END/1024 - esize); > u16 ebda_seg = EBDA_SEGMENT_START; > SET_BDA(ebda_seg, ebda_seg); As above, this doesn't look right - SeaBIOS will still locate the EBDA at 9fc00 and nothing will stop it from growing it over the 9f000 area. -Kevin

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[PATCH] SeaBIOS/Xen: Compute the low RAM memory size in the BDA according to the e820
by Julian Pidancet 14 Nov '11

14 Nov '11

Some programs or ROMs like iPXE rely on the memory size field present in the BDA instead of e820 to relocate sections at the end of the low memory. Xen's hvmloader places an ACPI info table at 0x9F000 at the end of the usable RAM in low memory (just before the EBDA). The e820 table gets altered accordingly to protect the area where the table lives, but a ROM like iPXE only takes into account the memory size field in the BDA and consequently corrupts the table when relocating itself. This patch computes the size of the usable RAM in low memory by walking the e820 table and updates the BDA accordingly. It defaults to 640KB if it fails to guess that value. With Xen, the issue can be reproduced by pxe booting a linux kernel through iPXE using the pci=use_crs command line option. Without this patch the last of the following lines doesn't appear: [ 0.326967] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug [ 0.327999] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) [ 0.329028] pci_root PNP0A03:00: host bridge window [io 0x0000-0x0cf7] [ 0.329967] pci_root PNP0A03:00: host bridge window [io 0x0d00-0xffff] [ 0.330966] pci_root PNP0A03:00: host bridge window [mem 0x000a0000-0x000bffff] [ 0.331966] pci_root PNP0A03:00: host bridge window [mem 0xf0000000-0xfbffffff] Signed-off-by: Julian Pidancet <julian.pidancet(a)gmail.com> --- src/memmap.c | 29 +++++++++++++++++++++++++++++ src/memmap.h | 1 + src/post.c | 9 ++++++--- 3 files changed, 36 insertions(+), 3 deletions(-) diff --git a/src/memmap.c b/src/memmap.c index 20ccae0..36750f5 100644 --- a/src/memmap.c +++ b/src/memmap.c @@ -7,6 +7,7 @@ #include "memmap.h" // struct e820entry #include "util.h" // dprintf.h #include "biosvar.h" // SET_EBDA +#include "config.h" // CONFIG_* /**************************************************************** @@ -133,6 +134,34 @@ add_e820(u64 start, u64 size, u32 type) //dump_map(); } +// Try to find the size of the usable RAM memory in the +// first megabyte of RAM. +u32 +get_lowram_size(void) +{ + u32 lowram_end = 0; + + int i; + for (i=0; i<e820_count; i++) { + struct e820entry *e = &e820_list[i]; + u64 e_end = e->start + e->size; + + if (e->type != E820_RAM) + continue; + + if (e_end <= 0x100000 && /* 1M */ + e_end > lowram_end) + lowram_end = (u32)e_end; + } + + // No RAM entry ending before the first megabyte of memory + // found, default to 0xA0000 + if (!lowram_end) + lowram_end = BUILD_LOWRAM_END; + + return lowram_end; +} + // Report on final memory locations. void memmap_finalize(void) diff --git a/src/memmap.h b/src/memmap.h index 01c7ddb..e65d090 100644 --- a/src/memmap.h +++ b/src/memmap.h @@ -18,6 +18,7 @@ struct e820entry { void add_e820(u64 start, u64 size, u32 type); void memmap_finalize(void); +u32 get_lowram_size(void); // A typical OS page size #define PAGE_SIZE 4096 diff --git a/src/post.c b/src/post.c index b4ad1fa..9f0cb63 100644 --- a/src/post.c +++ b/src/post.c @@ -82,18 +82,21 @@ init_bda(void) struct bios_data_area_s *bda = MAKE_FLATPTR(SEG_BDA, 0); memset(bda, 0, sizeof(*bda)); - int esize = EBDA_SIZE_START; - SET_BDA(mem_size_kb, BUILD_LOWRAM_END/1024 - esize); u16 ebda_seg = EBDA_SEGMENT_START; SET_BDA(ebda_seg, ebda_seg); // Init ebda struct extended_bios_data_area_s *ebda = get_ebda_ptr(); memset(ebda, 0, sizeof(*ebda)); - ebda->size = esize; + ebda->size = EBDA_SIZE_START; add_e820((u32)MAKE_FLATPTR(ebda_seg, 0), GET_EBDA2(ebda_seg, size) * 1024 , E820_RESERVED); + + u32 lowram_size = get_lowram_size(); + + dprintf(8, "End of usable low memory RAM: %08x\n", lowram_size); + SET_BDA(mem_size_kb, lowram_size / 1024); } static void -- Julian Pidancet

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PCI Option ROM debugging with Coreboot+SeaBIOS (detailed steps)
by Darmawan Salihun 12 Nov '11

12 Nov '11

I made a blogpost detailing the steps to debug PCI Option ROM with Coreboot+SeaBIOS and a GDB-server-compatible debugger: http://bioshacking.blogspot.com/search/label/PCI%20Option%20ROM Hopefully would help those in need because it takes quite a while to get it right. Thanks to Kevin O'Connor for the helps :-) Regards, Darmawan -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =-

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Re: [SeaBIOS] [PATCH] Set numa topology for max_cpus
by Marcelo Tosatti 10 Nov '11

10 Nov '11

On Wed, Oct 26, 2011 at 02:19:00PM +0200, Vasilis Liaskovitis wrote: > qemu-kvm passes numa/SRAT topology information for smp_cpus to SeaBIOS. However > SeaBIOS always expects to setup max_cpus number of SRAT cpu entries > (MaxCountCPUs variable in build_srat function of Seabios). When qemu-kvm runs > with smp_cpus != max_cpus (e.g. -smp 2,maxcpus=4), Seabios will mistakenly use > memory SRAT info for setting up CPU SRAT entries for the offline CPUs. Wrong > SRAT memory entries are also created. This breaks NUMA in a guest. > Fix by setting up SRAT info for max_cpus in qemu-kvm. > > Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis(a)profitbricks.com> Applied to uq/master, thanks.

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SeaBIOS - Network Problem - LSI53C895A Interrupt problem
by Gerhard Wiesinger 05 Nov '11

05 Nov '11

Hello, I'm having the following problem with Knoppix 6.2 since commit a65f417c8430ce6781cbbfe84381a97d60628d81 of seabios: Linux Call trace and AMD pcnet network interface doesn't work. Looks like that interrupt is disabled. 21.016946] irq 11: nobody cared (try booting with the "irqpoll" option) [ 21.016951] Pid: 2563, comm: NetworkManager Not tainted 2.6.31.6 #4 [ 21.016953] Call Trace: [ 21.016978] [<c0156ce4>] __report_bad_irq+0x2e/0x6f [ 21.016981] [<c0156e12>] note_interrupt+0xed/0x14b [ 21.016985] [<c0157342>] handle_fasteoi_irq+0x8a/0xae [ 21.016989] [<c0104e9a>] handle_irq+0x1a/0x1f [ 21.016991] [<c0104882>] do_IRQ+0x40/0x96 [ 21.016993] [<c01035a9>] common_interrupt+0x29/0x30 [ 21.016998] [<c012be15>] ? __do_softirq+0x47/0xe5 [ 21.017000] [<c012bed9>] do_softirq+0x26/0x2b [ 21.017002] [<c012c02d>] irq_exit+0x29/0x67 [ 21.017004] [<c01048c2>] do_IRQ+0x80/0x96 [ 21.017006] [<c01035a9>] common_interrupt+0x29/0x30 [ 21.017016] [<c04e5cd8>] ? _spin_unlock_irqrestore+0x7/0x26 [ 21.017024] [<d08d8f52>] pcnet32_open+0x4c6/0x50b [pcnet32] [ 21.017029] [<c013b107>] ? notifier_call_chain+0x2b/0x4a [ 21.017036] [<c045d184>] dev_open+0x93/0xd3 [ 21.017038] [<c045c8cd>] dev_change_flags+0xa4/0x157 [ 21.017041] [<c04639cd>] ? rtnl_setlink+0x0/0xe2 [ 21.017043] [<c0463915>] do_setlink+0x26b/0x323 [ 21.017045] [<c046358d>] ? nlmsg_parse+0x37/0x45 [ 21.017047] [<c04639cd>] ? rtnl_setlink+0x0/0xe2 [ 21.017049] [<c0463aa9>] rtnl_setlink+0xdc/0xe2 [ 21.017052] [<c0464781>] rtnetlink_rcv_msg+0x18d/0x1a7 [ 21.017054] [<c04645f4>] ? rtnetlink_rcv_msg+0x0/0x1a7 [ 21.017058] [<c046fa34>] netlink_rcv_skb+0x30/0x78 [ 21.017060] [<c04645ec>] rtnetlink_rcv+0x1c/0x24 [ 21.017062] [<c046f625>] netlink_unicast+0xc6/0x11c [ 21.017064] [<c046f8a9>] netlink_sendmsg+0x22e/0x23b [ 21.017070] [<c044fea9>] sock_sendmsg+0xca/0xe1 [ 21.017074] [<c0137b13>] ? autoremove_wake_function+0x0/0x33 [ 21.017077] [<c0137b13>] ? autoremove_wake_function+0x0/0x33 [ 21.017079] [<c0457020>] ? verify_iovec+0x40/0x70 [ 21.017082] [<c044ffff>] sys_sendmsg+0x13f/0x192 [ 21.017084] [<c04507c8>] ? sys_sendto+0xa1/0xc0 [ 21.017086] [<c04e5d5e>] ? _spin_unlock+0x19/0x24 [ 21.017096] [<c01a0f38>] ? fsnotify_clear_marks_by_inode+0x74/0xa9 [ 21.017099] [<c044efae>] ? sock_destroy_inode+0x10/0x12 [ 21.017103] [<c018df88>] ? generic_drop_inode+0x189/0x18d [ 21.017106] [<c0450f97>] sys_socketcall+0x153/0x183 [ 21.017108] [<c012b7ef>] ? sys_time+0x10/0x39 [ 21.017110] [<c0102fd1>] syscall_call+0x7/0xb [ 21.017111] handlers: [ 21.017112] [<d08a77c6>] (sym53c8xx_intr+0x0/0x5f [sym53c8xx]) [ 21.017119] Disabling IRQ #11 I bisect it down to the following commit: a65f417c8430ce6781cbbfe84381a97d60628d81 is the first bad commit commit a65f417c8430ce6781cbbfe84381a97d60628d81 Author: Kevin O'Connor <kevin(a)koconnor.net> Date: Sun Sep 25 23:08:58 2011 -0400 Consolidate DSDT copy-and-paste PCI IRQ code into method calls. Use method calls in LNK[ABCDS] object methods - this reduces the cut-and-paste code. It also makes it simpler and the object size smaller. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> Any ideas what the problem might be and how to fix it? Thnx. Ciao, Gerhard -- http://www.wiesinger.com/

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[PATCH] Use dedicated HVM debug io port for Xen
by Julian Pidancet 05 Nov '11

05 Nov '11

When running on Xen, use Xen debug io port as debug output instead of Bochs one. Signed-off-by: Julian Pidancet <julian.pidancet(a)gmail.com> --- src/output.c | 9 +++++++-- src/xen.h | 2 ++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/output.c b/src/output.c index 462ffb7..78541a4 100644 --- a/src/output.c +++ b/src/output.c @@ -11,6 +11,7 @@ #include "bregs.h" // struct bregs #include "config.h" // CONFIG_* #include "biosvar.h" // GET_GLOBAL +#include "xen.h" // PORT_XEN_DEBUG struct putcinfo { void (*func)(struct putcinfo *info, char c); @@ -75,9 +76,13 @@ putc_debug(struct putcinfo *action, char c) { if (! CONFIG_DEBUG_LEVEL) return; - if (! CONFIG_COREBOOT) + if (! CONFIG_COREBOOT) { // Send character to debug port. - outb(c, PORT_BIOS_DEBUG); + if (CONFIG_XEN) + outb(c, PORT_XEN_DEBUG); + else + outb(c, PORT_BIOS_DEBUG); + } if (c == '\n') debug_serial('\r'); debug_serial(c); diff --git a/src/xen.h b/src/xen.h index 0ed1e9f..802fee0 100644 --- a/src/xen.h +++ b/src/xen.h @@ -3,6 +3,8 @@ #include "util.h" +#define PORT_XEN_DEBUG 0xe9 + extern u32 xen_cpuid_base; void xen_probe(void); -- Julian Pidancet

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[PATCH RFC] acpi: add ssdt for cpi hotplug
by Michael S. Tsirkin 04 Nov '11

04 Nov '11

So here's the plan: move all hotplug handling out to ssdt, this way it'll keep working even with a user-supplied dsdt. Next step we can patch this ssdt at runtime. There's little point in this change alone, so posting as RFC, will repost with the patching part when it's ready, posting now to present opportunity for early feedback. Compiled only. Signed-off-by: Michael S. Tsirkin <mst(a)redhat.com> --- Makefile | 2 +- src/acpi-dsdt.dsl | 179 ------------------------------------------------- src/acpi.c | 4 + src/ssdt-pcihp.dsl | 188 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 193 insertions(+), 180 deletions(-) create mode 100644 src/ssdt-pcihp.dsl diff --git a/Makefile b/Makefile index 540f1ea..ef8e15d 100644 --- a/Makefile +++ b/Makefile @@ -200,7 +200,7 @@ src/%.hex: src/%.dsl ./tools/acpi_extract_preprocess.py ./tools/acpi_extract.py $(Q)./tools/acpi_extract.py $(OUT)$*.lst > $(OUT)$*.off $(Q)cat $(OUT)$*.off > $@ -$(OUT)ccode32flat.o: src/acpi-dsdt.hex src/ssdt-proc.hex +$(OUT)ccode32flat.o: src/acpi-dsdt.hex src/ssdt-proc.hex src/ssdt-pcihp.hex ####### Kconfig rules export HOSTCC := $(CC) diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl index b9b06f2..32eaeee 100644 --- a/src/acpi-dsdt.dsl +++ b/src/acpi-dsdt.dsl @@ -119,25 +119,6 @@ DefinitionBlock ( prt_slot3(0x001f), }) - OperationRegion(PCST, SystemIO, 0xae00, 0x08) - Field (PCST, DWordAcc, NoLock, WriteAsZeros) - { - PCIU, 32, - PCID, 32, - } - - OperationRegion(SEJ, SystemIO, 0xae08, 0x04) - Field (SEJ, DWordAcc, NoLock, WriteAsZeros) - { - B0EJ, 32, - } - - OperationRegion(RMVC, SystemIO, 0xae0c, 0x04) - Field(RMVC, DWordAcc, NoLock, WriteAsZeros) - { - PCRM, 32, - } - Name (_CRS, ResourceTemplate () { WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, @@ -458,162 +439,6 @@ DefinitionBlock ( } } } - - -/**************************************************************** - * PCI hotplug - ****************************************************************/ - - Scope(\_SB.PCI0) { - /* Methods called by bulk generated PCI devices below */ - Method (PRMV, 1, NotSerialized) { - // _RMV method - check if device can be removed - If (And(\_SB.PCI0.PCRM, ShiftLeft(1, Arg0))) { - Return (0x1) - } - Return (0x0) - } - -#define gen_pci_device(slot) \ - Device(SL##slot) { \ - Name (_ADR, 0x##slot##0000) \ - Method (_RMV) { Return (PRMV(0x##slot)) } \ - Name (_SUN, 0x##slot) \ - } - - /* VGA (slot 1) and ISA bus (slot 2) defined above */ - gen_pci_device(03) - gen_pci_device(04) - gen_pci_device(05) - gen_pci_device(06) - gen_pci_device(07) - gen_pci_device(08) - gen_pci_device(09) - gen_pci_device(0a) - gen_pci_device(0b) - gen_pci_device(0c) - gen_pci_device(0d) - gen_pci_device(0e) - gen_pci_device(0f) - gen_pci_device(10) - gen_pci_device(11) - gen_pci_device(12) - gen_pci_device(13) - gen_pci_device(14) - gen_pci_device(15) - gen_pci_device(16) - gen_pci_device(17) - gen_pci_device(18) - gen_pci_device(19) - gen_pci_device(1a) - gen_pci_device(1b) - gen_pci_device(1c) - gen_pci_device(1d) - gen_pci_device(1e) - gen_pci_device(1f) - - /* Methods called by bulk generated hotplug devices below */ - Method (PCEJ, 1, NotSerialized) { - // _EJ0 method - eject callback - Store(ShiftLeft(1, Arg0), B0EJ) - Return (0x0) - } - - /* Bulk generated PCI hotplug devices */ -#define hotplug_slot(slot) \ - Device (S##slot) { \ - Name (_ADR, 0x##slot##0000) \ - Method (_EJ0, 1) { Return(PCEJ(0x##slot)) } \ - Name (_SUN, 0x##slot) \ - } - - hotplug_slot(01) - hotplug_slot(02) - hotplug_slot(03) - hotplug_slot(04) - hotplug_slot(05) - hotplug_slot(06) - hotplug_slot(07) - hotplug_slot(08) - hotplug_slot(09) - hotplug_slot(0a) - hotplug_slot(0b) - hotplug_slot(0c) - hotplug_slot(0d) - hotplug_slot(0e) - hotplug_slot(0f) - hotplug_slot(10) - hotplug_slot(11) - hotplug_slot(12) - hotplug_slot(13) - hotplug_slot(14) - hotplug_slot(15) - hotplug_slot(16) - hotplug_slot(17) - hotplug_slot(18) - hotplug_slot(19) - hotplug_slot(1a) - hotplug_slot(1b) - hotplug_slot(1c) - hotplug_slot(1d) - hotplug_slot(1e) - hotplug_slot(1f) - - /* PCI hotplug notify method */ - Method(PCNF, 0) { - // Local0 = iterator - Store (Zero, Local0) - While (LLess(Local0, 31)) { - Increment(Local0) - If (And(PCIU, ShiftLeft(1, Local0))) { - PCNT(Local0, 1) - } - If (And(PCID, ShiftLeft(1, Local0))) { - PCNT(Local0, 3) - } - } - Return(One) - } - -#define gen_pci_hotplug(slot) \ - If (LEqual(Arg0, 0x##slot)) { Notify(S##slot, Arg1) } - - Method(PCNT, 2) { - gen_pci_hotplug(01) - gen_pci_hotplug(02) - gen_pci_hotplug(03) - gen_pci_hotplug(04) - gen_pci_hotplug(05) - gen_pci_hotplug(06) - gen_pci_hotplug(07) - gen_pci_hotplug(08) - gen_pci_hotplug(09) - gen_pci_hotplug(0a) - gen_pci_hotplug(0b) - gen_pci_hotplug(0c) - gen_pci_hotplug(0d) - gen_pci_hotplug(0e) - gen_pci_hotplug(0f) - gen_pci_hotplug(10) - gen_pci_hotplug(11) - gen_pci_hotplug(12) - gen_pci_hotplug(13) - gen_pci_hotplug(14) - gen_pci_hotplug(15) - gen_pci_hotplug(16) - gen_pci_hotplug(17) - gen_pci_hotplug(18) - gen_pci_hotplug(19) - gen_pci_hotplug(1a) - gen_pci_hotplug(1b) - gen_pci_hotplug(1c) - gen_pci_hotplug(1d) - gen_pci_hotplug(1e) - gen_pci_hotplug(1f) - } - } - - /**************************************************************** * PCI IRQs ****************************************************************/ @@ -837,10 +662,6 @@ DefinitionBlock ( Method(_L00) { Return(0x01) } - Method(_L01) { - // PCI hotplug event - Return(\_SB.PCI0.PCNF()) - } Method(_L02) { // CPU hotplug event Return(\_SB.PRSC()) diff --git a/src/acpi.c b/src/acpi.c index a3770ae..97cc6dd 100644 --- a/src/acpi.c +++ b/src/acpi.c @@ -406,6 +406,7 @@ encodeLen(u8 *ssdt_ptr, int length, int bytes) #define SD_PROC (ssdp_proc_aml + *ssdt_proc_start) #define SSDT_SIGNATURE 0x54445353 // SSDT + static void* build_ssdt(void) { @@ -633,6 +634,8 @@ static const struct pci_device_id acpi_find_tbl[] = { struct rsdp_descriptor *RsdpAddr; +#include "ssdt-pcihp.hex" + #define MAX_ACPI_TABLES 20 void acpi_bios_init(void) @@ -664,6 +667,7 @@ acpi_bios_init(void) ACPI_INIT_TABLE(build_madt()); ACPI_INIT_TABLE(build_hpet()); ACPI_INIT_TABLE(build_srat()); + ACPI_INIT_TABLE(ssdp_pcihp_aml); u16 i, external_tables = qemu_cfg_acpi_additional_tables(); diff --git a/src/ssdt-pcihp.dsl b/src/ssdt-pcihp.dsl new file mode 100644 index 0000000..7ed7eef --- /dev/null +++ b/src/ssdt-pcihp.dsl @@ -0,0 +1,188 @@ +ACPI_EXTRACT_ALL_CODE ssdp_pcihp_aml + +DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1) +{ + +/**************************************************************** + * PCI hotplug + ****************************************************************/ + + External (\_SB.PCI0, DeviceObj) + + Scope(\_SB.PCI0) { + OperationRegion(PCST, SystemIO, 0xae00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32, + } + + OperationRegion(SEJ, SystemIO, 0xae08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32, + } + + OperationRegion(RMVC, SystemIO, 0xae0c, 0x04) + Field(RMVC, DWordAcc, NoLock, WriteAsZeros) + { + PCRM, 32, + } + + /* Methods called by bulk generated PCI devices below */ + Method (PRMV, 1, NotSerialized) { + // _RMV method - check if device can be removed + If (And(\_SB.PCI0.PCRM, ShiftLeft(1, Arg0))) { + Return (0x1) + } + Return (0x0) + } + +#define gen_pci_device(slot) \ + Device(SL##slot) { \ + Name (_ADR, 0x##slot##0000) \ + Method (_RMV) { Return (PRMV(0x##slot)) } \ + Name (_SUN, 0x##slot) \ + } + + /* VGA (slot 1) and ISA bus (slot 2) defined in DSDT */ + gen_pci_device(03) + gen_pci_device(04) + gen_pci_device(05) + gen_pci_device(06) + gen_pci_device(07) + gen_pci_device(08) + gen_pci_device(09) + gen_pci_device(0a) + gen_pci_device(0b) + gen_pci_device(0c) + gen_pci_device(0d) + gen_pci_device(0e) + gen_pci_device(0f) + gen_pci_device(10) + gen_pci_device(11) + gen_pci_device(12) + gen_pci_device(13) + gen_pci_device(14) + gen_pci_device(15) + gen_pci_device(16) + gen_pci_device(17) + gen_pci_device(18) + gen_pci_device(19) + gen_pci_device(1a) + gen_pci_device(1b) + gen_pci_device(1c) + gen_pci_device(1d) + gen_pci_device(1e) + gen_pci_device(1f) + + /* Methods called by bulk generated hotplug devices below */ + Method (PCEJ, 1, NotSerialized) { + // _EJ0 method - eject callback + Store(ShiftLeft(1, Arg0), B0EJ) + Return (0x0) + } + + /* Bulk generated PCI hotplug devices */ +#define hotplug_slot(slot) \ + Device (S##slot) { \ + Name (_ADR, 0x##slot##0000) \ + Method (_EJ0, 1) { Return(PCEJ(0x##slot)) } \ + Name (_SUN, 0x##slot) \ + } + + hotplug_slot(01) + hotplug_slot(02) + hotplug_slot(03) + hotplug_slot(04) + hotplug_slot(05) + hotplug_slot(06) + hotplug_slot(07) + hotplug_slot(08) + hotplug_slot(09) + hotplug_slot(0a) + hotplug_slot(0b) + hotplug_slot(0c) + hotplug_slot(0d) + hotplug_slot(0e) + hotplug_slot(0f) + hotplug_slot(10) + hotplug_slot(11) + hotplug_slot(12) + hotplug_slot(13) + hotplug_slot(14) + hotplug_slot(15) + hotplug_slot(16) + hotplug_slot(17) + hotplug_slot(18) + hotplug_slot(19) + hotplug_slot(1a) + hotplug_slot(1b) + hotplug_slot(1c) + hotplug_slot(1d) + hotplug_slot(1e) + hotplug_slot(1f) + + /* PCI hotplug notify method */ + Method(PCNF, 0) { + // Local0 = iterator + Store (Zero, Local0) + While (LLess(Local0, 31)) { + Increment(Local0) + If (And(PCIU, ShiftLeft(1, Local0))) { + PCNT(Local0, 1) + } + If (And(PCID, ShiftLeft(1, Local0))) { + PCNT(Local0, 3) + } + } + Return(One) + } + +#define gen_pci_hotplug(slot) \ + If (LEqual(Arg0, 0x##slot)) { Notify(S##slot, Arg1) } + + Method(PCNT, 2) { + gen_pci_hotplug(01) + gen_pci_hotplug(02) + gen_pci_hotplug(03) + gen_pci_hotplug(04) + gen_pci_hotplug(05) + gen_pci_hotplug(06) + gen_pci_hotplug(07) + gen_pci_hotplug(08) + gen_pci_hotplug(09) + gen_pci_hotplug(0a) + gen_pci_hotplug(0b) + gen_pci_hotplug(0c) + gen_pci_hotplug(0d) + gen_pci_hotplug(0e) + gen_pci_hotplug(0f) + gen_pci_hotplug(10) + gen_pci_hotplug(11) + gen_pci_hotplug(12) + gen_pci_hotplug(13) + gen_pci_hotplug(14) + gen_pci_hotplug(15) + gen_pci_hotplug(16) + gen_pci_hotplug(17) + gen_pci_hotplug(18) + gen_pci_hotplug(19) + gen_pci_hotplug(1a) + gen_pci_hotplug(1b) + gen_pci_hotplug(1c) + gen_pci_hotplug(1d) + gen_pci_hotplug(1e) + gen_pci_hotplug(1f) + } + } + + Scope (\_GPE) + { + Method(_L01) { + // PCI hotplug event + Return(\_SB.PCI0.PCNF()) + } + } + +} -- 1.7.5.53.gc233e

4 11

[PATCH] i8042_flush change
by John Baboval 01 Nov '11

01 Nov '11

When using seabios with Xen and qemu, I frequently get the following message: WARNING - Timeout at i8042_flush:69! I do have a slightly unusual configuration compared to the typical Xen configuration. We are running with no hvmloader. However I don't think that's related to this issue.... The flush routine attempts to read the queue depth's worth of data from the port and then checks to see if the queue is empty. There are two issues with this. First is that qemu and seabios disagree about the queue depth. Qemu's ps2 buffer has 256 entries, and I8042_BUFFER_SIZE is 16 for seabios. The second is that a command may arrive between the start of the flush loop and the completion. I believe a more robust way to do this would be to first issue a RESET command, and then flush. That resolves the issue that I am seeing. Signed-off By: John Baboval <john.baboval(a)virtualcomputer.com> --- diff --git a/src/ps2port.c b/src/ps2port.c index 58335af..4ed25bf 100644 --- a/src/ps2port.c +++ b/src/ps2port.c @@ -20,7 +20,7 @@ // Timeout value. #define I8042_CTL_TIMEOUT 10000 -#define I8042_BUFFER_SIZE 16 +#define I8042_BUFFER_SIZE 256 static int i8042_wait_read(void) @@ -391,7 +391,7 @@ handle_09(void) } v = inb(PORT_PS2_DATA); - if (!(GET_EBDA(ps2ctr) & I8042_CTR_KBDINT)) + if (!(GET_EBDA(ps2ctr) & I8042_CTR_KBDINT)) // Interrupts not enabled. goto done; @@ -409,13 +409,17 @@ done: static void keyboard_init(void *data) { + int ret; + u8 param[2]; /* flush incoming keys */ - int ret = i8042_flush(); + ret = ps2_kbd_command(ATKBD_CMD_RESET_BAT, param); + if (ret) + return; + ret = i8042_flush(); if (ret) return; // Controller self-test. - u8 param[2]; ret = i8042_command(I8042_CMD_CTL_TEST, param); if (ret) return;

2 6

Re: [SeaBIOS] Question on block driver operation buffer
by Kevin O'Connor 01 Nov '11

01 Nov '11

On Tue, Nov 01, 2011 at 08:21:11PM +0900, Daniel Castro wrote: > Hello, > > When an int 13 operation is handles (suppose read), you are supposed > to get sector X up until sector Y, where X is lba and count is Y. But > I wonder, the buffer is the size of the operation? or is it a > predefined size that never changes? I tend to incline for the later > one, but how can I determine the size? If the caller requests a read of 16 sectors that are 512 bytes each then the caller must provide an 8K buffer to read into. The SeaBIOS code will pass this buffer to the low-level driver code (op->buf_fl) - the driver should try to fully populate this buffer according to the drive sector size and request size (op->count). -Kevin

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SeaBIOS November 2011