coreboot-gerrit September 2021

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Change in coreboot[master]: mb/google/brya/variants/gimble: Enable SaGv support
by Mark Hsieh (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Marx Wang, YH Lin, Tim Wawrzynczak, Kane Chen, Felix Held. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57357 ) Change subject: mb/google/brya/variants/gimble: Enable SaGv support ...................................................................... Patch Set 1: Code-Review+1 This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/57357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29887418827614afb10558c6958c9c5e9667079e Gerrit-Change-Number: 57357 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: Marx Wang <marx.wang(a)intel.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Sep 2021 06:28:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Add argument for CSE fixed client addr
by Rizwan Qureshi (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Rizwan Qureshi, Tim Wawrzynczak, Sridhar Siricilla, Aseda Aboagye, Andrey Petrov, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Tim Wawrzynczak, Aseda Aboagye, Sridhar Siricilla, Andrey Petrov, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57295 to look at the new patch set (#10). Change subject: soc/intel/common/cse: Add argument for CSE fixed client addr ...................................................................... soc/intel/common/cse: Add argument for CSE fixed client addr There are multiple HECI clients in the CSE. heci_send_receive() is sending HECI messages to only the MKHI client. Add an argument to heci_send_receive() function to provide flexibility to the caller to select the client for which the message is intended. With the above change heci_send() and heci_receive() functions are no longer required to be exposed. In the follow-up patches there will be messages sent to one other client. BUG=None BRANCH=None TEST=Build and boot brya. HECI message send and receive to MKHI client is working. Also, MEI BUS message to disable bus is working. Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c --- M src/soc/intel/apollolake/cse.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_eop.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 5 files changed, 38 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/57295/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/57295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c Gerrit-Change-Number: 57295 Gerrit-PatchSet: 10 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/qualcomm/common: clock: Add support for common clock driver
by Shelley Chen (Code Review) 03 Sep '21

03 Sep '21

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56588 ) Change subject: soc/qualcomm/common: clock: Add support for common clock driver ...................................................................... soc/qualcomm/common: clock: Add support for common clock driver The clock driver supports configuring the general purpose PLLs, configuring the root clock generator (RCG), enable clock branch, enable gdsc and also the block resets. The common clock driver exposes PLL configuration functions and also different Agera PLL enable functions for the CPU PLLs. While at it, the common driver also supports reset of subsystems like AOP and SHRM. SC7180 clock driver is also refactored to use the common clock driver APIs. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Change-Id: I03d1b4a2fb90303c7259ec08f312d78b4e33ec39 Signed-off-by: Taniya Das <tdas(a)codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56588 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shelley Chen <shchen(a)google.com> --- A src/soc/qualcomm/common/clock.c A src/soc/qualcomm/common/include/soc/clock_common.h M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/include/soc/clock.h 5 files changed, 513 insertions(+), 353 deletions(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/soc/qualcomm/common/clock.c b/src/soc/qualcomm/common/clock.c new file mode 100644 index 0000000..e83f979 --- /dev/null +++ b/src/soc/qualcomm/common/clock.c @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <commonlib/helpers.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/clock.h> +#include <timer.h> +#include <types.h> + +/* Clock Branch Operations */ +static bool clock_is_off(u32 *cbcr_addr) +{ + return (read32(cbcr_addr) & CLK_CTL_OFF_BMSK); +} + +enum cb_err clock_enable_vote(void *cbcr_addr, void *vote_addr, + uint32_t vote_bit) +{ + int count = 100; + + setbits32(vote_addr, BIT(vote_bit)); + + /* Ensure clock is enabled */ + while (count-- > 0) { + if (!clock_is_off(cbcr_addr)) + return CB_SUCCESS; + udelay(1); + } + printk(BIOS_ERR, "ERROR: Failed to enable clock, register val: 0x%x\n", + read32(cbcr_addr)); + return CB_ERR; +} + +enum cb_err clock_enable(void *cbcr_addr) +{ + int count = 100; + + /* Set clock enable bit */ + setbits32(cbcr_addr, BIT(CLK_CTL_EN_SHFT)); + + /* Ensure clock is enabled */ + while (count-- > 0) { + if (!clock_is_off(cbcr_addr)) + return CB_SUCCESS; + udelay(1); + } + printk(BIOS_ERR, "ERROR: Failed to enable clock, register val: 0x%x\n", + read32(cbcr_addr)); + return CB_ERR; +} + +/* Clock Block Reset Operations */ +void clock_reset_bcr(void *bcr_addr, bool assert) +{ + if (assert) + setbits32(bcr_addr, BIT(CLK_CTL_BCR_BLK_SHFT)); + else + clrbits32(bcr_addr, BIT(CLK_CTL_BCR_BLK_SHFT)); +} + +/* Clock GDSC Operations */ +enum cb_err enable_and_poll_gdsc_status(void *gdscr_addr) +{ + if (read32(gdscr_addr) & CLK_CTL_OFF_BMSK) + return CB_SUCCESS; + + clrbits32(gdscr_addr, BIT(GDSC_ENABLE_BIT)); + + /* Ensure gdsc is enabled */ + if (!wait_us(100, (read32(gdscr_addr) & CLK_CTL_OFF_BMSK))) + return CB_ERR; + + return CB_SUCCESS; +} + +/* Clock Root clock Generator with MND Operations */ +static void clock_configure_mnd(struct clock_rcg *clk, uint32_t m, uint32_t n, + uint32_t d_2) +{ + struct clock_rcg_mnd *mnd = (struct clock_rcg_mnd *)clk; + + setbits32(&clk->rcg_cfg, + RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); + + write32(&mnd->m, m & CLK_CTL_RCG_MND_BMSK); + write32(&mnd->n, ~(n-m) & CLK_CTL_RCG_MND_BMSK); + write32(&mnd->d_2, ~(d_2) & CLK_CTL_RCG_MND_BMSK); +} + +/* Clock Root clock Generator Operations */ +enum cb_err clock_configure(struct clock_rcg *clk, + struct clock_freq_config *clk_cfg, uint32_t hz, + uint32_t num_perfs) +{ + uint32_t reg_val, idx; + + for (idx = 0; idx < num_perfs; idx++) + if (hz <= clk_cfg[idx].hz) + break; + + reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + /* Set clock config */ + write32(&clk->rcg_cfg, reg_val); + + if (clk_cfg[idx].m != 0) + clock_configure_mnd(clk, clk_cfg[idx].m, clk_cfg[idx].n, + clk_cfg[idx].d_2); + + /* Commit config to RCG */ + setbits32(&clk->rcg_cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + + return CB_SUCCESS; +} + +/* Clock Root clock Generator with DFS Operations */ +void clock_configure_dfsr_table(int qup, struct clock_freq_config *clk_cfg, + uint32_t num_perfs) +{ + struct qupv3_clock *qup_clk; + unsigned int idx, s = qup % QUP_WRAP1_S0; + uint32_t reg_val; + + qup_clk = qup < QUP_WRAP1_S0 ? + &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; + + clrsetbits32(&qup_clk->dfsr_clk.cmd_dfsr, + BIT(CLK_CTL_CMD_RCG_SW_CTL_SHFT), + BIT(CLK_CTL_CMD_DFSR_SHFT)); + + for (idx = 0; idx < num_perfs; idx++) { + reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + write32(&qup_clk->dfsr_clk.perf_dfsr[idx], reg_val); + + if (clk_cfg[idx].m == 0) + continue; + + setbits32(&qup_clk->dfsr_clk.perf_dfsr[idx], + RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); + + reg_val = clk_cfg[idx].m & CLK_CTL_RCG_MND_BMSK; + write32(&qup_clk->dfsr_clk.perf_m_dfsr[idx], reg_val); + + reg_val = ~(clk_cfg[idx].n - clk_cfg[idx].m) + & CLK_CTL_RCG_MND_BMSK; + write32(&qup_clk->dfsr_clk.perf_n_dfsr[idx], reg_val); + + reg_val = ~(clk_cfg[idx].d_2) & CLK_CTL_RCG_MND_BMSK; + write32(&qup_clk->dfsr_clk.perf_d_dfsr[idx], reg_val); + } +} + +/* General Purpose PLL configuration and enable Operations */ +enum cb_err clock_configure_enable_gpll(struct alpha_pll_reg_val_config *cfg, + bool enable, int br_enable) +{ + if (cfg->l_val) + write32(cfg->reg_l, cfg->l_val); + + if (cfg->cal_l_val) + write32(cfg->reg_cal_l, cfg->cal_l_val); + + if (cfg->alpha_val) + write32(cfg->reg_alpha, cfg->alpha_val); + + if (cfg->user_ctl_val) + write32(cfg->reg_user_ctl, cfg->user_ctl_val); + + if (cfg->user_ctl_hi_val) + write32(cfg->reg_user_ctl_hi, cfg->user_ctl_hi_val); + + if (cfg->user_ctl_hi1_val) + write32(cfg->reg_user_ctl_hi1, cfg->user_ctl_hi1_val); + + if (cfg->config_ctl_val) + write32(cfg->reg_config_ctl, cfg->config_ctl_val); + + if (cfg->config_ctl_hi_val) + write32(cfg->reg_config_ctl_hi, cfg->config_ctl_hi_val); + + if (cfg->config_ctl_hi1_val) + write32(cfg->reg_config_ctl_hi1, cfg->config_ctl_hi1_val); + + if (cfg->fsm_enable) + setbits32(cfg->reg_mode, BIT(PLL_FSM_EN_SHFT)); + + if (enable) { + setbits32(cfg->reg_opmode, BIT(PLL_STANDBY_MODE)); + + /* + * H/W requires a 1us delay between placing PLL in STANDBY and + * de-asserting the reset. + */ + udelay(1); + setbits32(cfg->reg_mode, BIT(PLL_RESET_N_SHFT)); + + /* + * H/W requires a 10us delay between de-asserting the reset and + * enabling the PLL branch bit. + */ + udelay(10); + setbits32(cfg->reg_apcs_pll_br_en, BIT(br_enable)); + + /* Wait for Lock Detection */ + if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { + printk(BIOS_ERR, "ERROR: PLL did not lock!\n"); + return CB_ERR; + } + } + + return CB_SUCCESS; +} + +enum cb_err agera_pll_enable(struct alpha_pll_reg_val_config *cfg) +{ + setbits32(cfg->reg_mode, BIT(PLL_BYPASSNL_SHFT)); + + /* + * H/W requires a 5us delay between disabling the bypass and + * de-asserting the reset. + */ + udelay(5); + setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT)); + + if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { + printk(BIOS_ERR, "ERROR: CPU PLL did not lock!\n"); + return CB_ERR; + } + + setbits32(cfg->reg_mode, BIT(PLL_OUTCTRL_SHFT)); + + return CB_SUCCESS; +} + +/* Bring subsystem out of RESET */ +void clock_reset_subsystem(u32 *misc, u32 shft) +{ + clrbits32(misc, BIT(shft)); +} diff --git a/src/soc/qualcomm/common/include/soc/clock_common.h b/src/soc/qualcomm/common/include/soc/clock_common.h new file mode 100644 index 0000000..b924194 --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/clock_common.h @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_QUALCOMM_COMMON_CLOCK_H__ +#define __SOC_QUALCOMM_COMMON_CLOCK_H__ + +#define QCOM_CLOCK_DIV(div) (2 * div - 1) + +/* Root Clock Generator */ +struct clock_rcg { + u32 rcg_cmd; + u32 rcg_cfg; +}; + +/* Root Clock Generator with MND */ +struct clock_rcg_mnd { + struct clock_rcg clock; + u32 m; + u32 n; + u32 d_2; +}; + +/* DFS controlled Root Clock Generator */ +struct clock_rcg_dfsr { + u32 cmd_dfsr; + u8 _res0[0x20 - 0x1c]; + u32 perf_dfsr[8]; + u8 _res1[0x60 - 0x40]; + u32 perf_m_dfsr[8]; + u8 _res2[0xa0 - 0x80]; + u32 perf_n_dfsr[8]; + u8 _res3[0xe0 - 0xc0]; + u32 perf_d_dfsr[8]; + u8 _res4[0x130 - 0x100]; +}; + +/* Clock Frequency Table */ +struct clock_freq_config { + uint32_t hz; + uint8_t src; + uint8_t div; + uint16_t m; + uint16_t n; + uint16_t d_2; +}; + +struct qupv3_clock { + u32 cbcr; + struct clock_rcg_mnd clk; + struct clock_rcg_dfsr dfsr_clk; +}; + +/* PLL Configuration */ +struct alpha_pll_reg_val_config { + void *reg_mode; + u32 mode_val; + void *reg_l; + u32 l_val; + void *reg_cal_l; + u32 cal_l_val; + void *reg_user_ctl; + u32 user_ctl_val; + void *reg_user_ctl_hi; + u32 user_ctl_hi_val; + void *reg_user_ctl_hi1; + u32 user_ctl_hi1_val; + void *reg_config_ctl; + u32 config_ctl_val; + void *reg_config_ctl_hi; + u32 config_ctl_hi_val; + void *reg_config_ctl_hi1; + u32 config_ctl_hi1_val; + void *reg_alpha; + u32 alpha_val; + void *reg_opmode; + void *reg_apcs_pll_br_en; + bool fsm_enable; +}; + +enum clk_ctl_gpll_user_ctl { + PLL_PLLOUT_MAIN_SHFT = 0, + PLL_PLLOUT_EVEN_SHFT = 1, + PLL_PLLOUT_ODD_SHFT = 2, + PLL_POST_DIV_EVEN_SHFT = 8, + PLL_POST_DIV_ODD_SHFT = 12, + PLL_PLLOUT_EVEN_BMSK = 0x2, +}; + +enum gpll_mode { + PLL_LOCK_DET_BMSK = 0x80000000, + PLL_BYPASSNL_BMSK = 0x2, + PLL_OUTCTRL_BMSK = 0x1, + PLL_USERCTL_BMSK = 0xF, + PLL_STANDBY_MODE = 0, + PLL_RUN_MODE = 1, + PLL_OPMODE_SHFT = 0, + PLL_OUTCTRL_SHFT = 0, + PLL_BYPASSNL_SHFT = 1, + PLL_RESET_SHFT = 2, + PLL_RESET_N_SHFT = 2, + PLL_FSM_EN_SHFT = 20, +}; + +enum clk_ctl_cfg_rcgr { + CLK_CTL_CFG_SRC_DIV_SHFT = 0, + CLK_CTL_CFG_SRC_SEL_SHFT = 8, + CLK_CTL_CFG_MODE_SHFT = 12, +}; + +enum clk_ctl_cmd_rcgr { + CLK_CTL_CMD_UPDATE_SHFT = 0, +}; + +enum clk_ctl_cbcr { + CLK_CTL_EN_SHFT = 0, + CLK_CTL_OFF_SHFT = 31, + CLK_CTL_EN_BMSK = 0x1, + CLK_CTL_OFF_BMSK = 0x80000000, +}; + +enum clk_ctl_rcg_mnd { + RCG_MODE_DUAL_EDGE = 2, + CLK_CTL_RCG_MND_SHFT = 0, + CLK_CTL_RCG_MND_BMSK = 0xFFFF, +}; + +enum clk_ctl_bcr { + CLK_CTL_BCR_BLK_SHFT = 0, + CLK_CTL_BCR_BLK_BMSK = 0x1, +}; + +enum clk_ctl_dfsr { + CLK_CTL_CMD_DFSR_SHFT = 0, + CLK_CTL_CMD_RCG_SW_CTL_SHFT = 15, + CLK_CTL_CMD_DFSR_BMSK = 0x1, +}; + +#define GDSC_ENABLE_BIT 0 + +enum cb_err clock_enable_vote(void *cbcr_addr, void *vote_addr, + uint32_t vote_bit); + +enum cb_err clock_enable(void *cbcr_addr); + +enum cb_err enable_and_poll_gdsc_status(void *gdscr_addr); + +void clock_reset_bcr(void *bcr_addr, bool assert); + +enum cb_err clock_configure(struct clock_rcg *clk, struct clock_freq_config *clk_cfg, + uint32_t hz, uint32_t num_perfs); + +void clock_configure_dfsr_table(int qup, struct clock_freq_config *clk_cfg, + uint32_t num_perfs); + +enum cb_err clock_configure_enable_gpll(struct alpha_pll_reg_val_config *cfg, + bool enable, int br_enable); +enum cb_err agera_pll_enable(struct alpha_pll_reg_val_config *cfg); + +struct aoss { + u8 _res0[0x50020]; + u32 aoss_cc_reset_status; + u8 _res1[0x5002c - 0x50024]; + u32 aoss_cc_apcs_misc; +}; +check_member(aoss, aoss_cc_reset_status, 0x50020); +check_member(aoss, aoss_cc_apcs_misc, 0x5002c); + +struct shrm { + u32 shrm_sproc_ctrl; +}; + +void clock_reset_subsystem(u32 *misc, u32 shft); + +#endif diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 5ac1f3f..83f9eb5 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -11,6 +11,7 @@ all-y += qupv3_spi.c all-y += clock.c all-$(CONFIG_SC7180_QSPI) += qspi.c +all-y += ../common/clock.c all-y += qcom_qup_se.c all-y += qupv3_config.c diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 8bf450a..aa289c4 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -2,48 +2,45 @@ #include <assert.h> #include <commonlib/helpers.h> -#include <console/console.h> #include <delay.h> #include <device/mmio.h> #include <soc/clock.h> #include <timer.h> #include <types.h> -#define DIV(div) (2 * div - 1) - -struct clock_config qspi_core_cfg[] = { +static struct clock_freq_config qspi_core_cfg[] = { { .hz = SRC_XO_HZ, /* 19.2KHz */ .src = SRC_XO_19_2MHZ, - .div = DIV(1), + .div = QCOM_CLOCK_DIV(1), }, { .hz = 100 * MHz, .src = SRC_GPLL0_EVEN_300MHZ, - .div = DIV(3), + .div = QCOM_CLOCK_DIV(3), }, { .hz = 150 * MHz, .src = SRC_GPLL0_EVEN_300MHZ, - .div = DIV(2), + .div = QCOM_CLOCK_DIV(2), }, { .hz = GPLL0_EVEN_HZ, /* 300MHz */ .src = SRC_GPLL0_EVEN_300MHZ, - .div = DIV(1), + .div = QCOM_CLOCK_DIV(1), } }; -struct clock_config qupv3_wrap_cfg[] = { +static struct clock_freq_config qupv3_wrap_cfg[] = { { .hz = SRC_XO_HZ, /* 19.2KHz */ .src = SRC_XO_19_2MHZ, - .div = DIV(1), + .div = QCOM_CLOCK_DIV(1), }, { .hz = 32 * MHz, .src = SRC_GPLL0_EVEN_300MHZ, - .div = DIV(1), + .div = QCOM_CLOCK_DIV(1), .m = 8, .n = 75, .d_2 = 75, @@ -51,7 +48,7 @@ { .hz = 48 * MHz, .src = SRC_GPLL0_EVEN_300MHZ, - .div = DIV(1), + .div = QCOM_CLOCK_DIV(1), .m = 4, .n = 25, .d_2 = 25, @@ -59,7 +56,7 @@ { .hz = 64 * MHz, .src = SRC_GPLL0_EVEN_300MHZ, - .div = DIV(1), + .div = QCOM_CLOCK_DIV(1), .m = 16, .n = 75, .d_2 = 75, @@ -67,7 +64,7 @@ { .hz = 96 * MHz, .src = SRC_GPLL0_EVEN_300MHZ, - .div = DIV(1), + .div = QCOM_CLOCK_DIV(1), .m = 8, .n = 25, .d_2 = 25, @@ -75,21 +72,21 @@ { .hz = 100 * MHz, .src = SRC_GPLL0_EVEN_300MHZ, - .div = DIV(3), + .div = QCOM_CLOCK_DIV(3), }, { .hz = SRC_XO_HZ, /* 19.2KHz */ .src = SRC_XO_19_2MHZ, - .div = DIV(1), + .div = QCOM_CLOCK_DIV(1), }, { .hz = SRC_XO_HZ, /* 19.2KHz */ .src = SRC_XO_19_2MHZ, - .div = DIV(1), + .div = QCOM_CLOCK_DIV(1), }, }; -static struct sc7180_mnd_clock *mdss_clock[MDSS_CLK_COUNT] = { +static struct clock_rcg_mnd *mdss_clock[MDSS_CLK_COUNT] = { [MDSS_CLK_ESC0] = &mdss->esc0, [MDSS_CLK_PCLK0] = &mdss->pclk0, [MDSS_CLK_BYTE0] = &mdss->byte0, @@ -105,96 +102,18 @@ static int clock_configure_gpll0(void) { - setbits32(&gcc->gpll0.user_ctl_u, 1 << SCALE_FREQ_SHFT); + struct alpha_pll_reg_val_config gpll0_cfg = {0}; - /* Keep existing GPLL0 configuration, in RUN mode @600Mhz. */ - setbits32(&gcc->gpll0.user_ctl, - 1 << CLK_CTL_GPLL_PLLOUT_EVEN_SHFT | - 1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT | - 1 << CLK_CTL_GPLL_PLLOUT_ODD_SHFT); + gpll0_cfg.reg_user_ctl_hi = &gcc->gpll0.user_ctl_u; + gpll0_cfg.user_ctl_hi_val = 1 << SCALE_FREQ_SHFT; - return 0; -} + gpll0_cfg.reg_user_ctl = &gcc->gpll0.user_ctl; + gpll0_cfg.user_ctl_val = (1 << PLL_POST_DIV_EVEN_SHFT | + 1 << PLL_PLLOUT_EVEN_SHFT | + 1 << PLL_PLLOUT_MAIN_SHFT | + 1 << PLL_PLLOUT_ODD_SHFT); -static void clock_configure_mnd(struct sc7180_clock *clk, uint32_t m, - uint32_t n, uint32_t d_2) -{ - struct sc7180_mnd_clock *mnd = (struct sc7180_mnd_clock *)clk; - setbits32(&clk->rcg_cfg, - RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); - - write32(&mnd->m, m & CLK_CTL_RCG_MND_BMSK); - write32(&mnd->n, ~(n-m) & CLK_CTL_RCG_MND_BMSK); - write32(&mnd->d_2, ~(d_2) & CLK_CTL_RCG_MND_BMSK); -} - -static enum cb_err clock_configure(struct sc7180_clock *clk, - struct clock_config *clk_cfg, - uint32_t hz, uint32_t num_perfs) -{ - uint32_t reg_val; - uint32_t idx; - - for (idx = 0; idx < num_perfs; idx++) - if (hz <= clk_cfg[idx].hz) - break; - - assert(hz == clk_cfg[idx].hz); - - reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | - (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); - - /* Set clock config */ - write32(&clk->rcg_cfg, reg_val); - - if (clk_cfg[idx].m != 0) - clock_configure_mnd(clk, clk_cfg[idx].m, clk_cfg[idx].n, - clk_cfg[idx].d_2); - - /* Commit config to RCG*/ - setbits32(&clk->rcg_cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); - - return CB_SUCCESS; -} - -static bool clock_is_off(u32 *cbcr_addr) -{ - return (read32(cbcr_addr) & CLK_CTL_CBC_CLK_OFF_BMSK); -} - -static enum cb_err clock_enable_vote(void *cbcr_addr, void *vote_addr, - uint32_t vote_bit) -{ - /* Set clock vote bit */ - setbits32(vote_addr, BIT(vote_bit)); - - /* Ensure clock is enabled */ - if (!wait_us(100, clock_is_off(cbcr_addr))) - return CB_ERR; - - return CB_SUCCESS; -} - -static enum cb_err clock_enable(void *cbcr_addr) -{ - /* Set clock enable bit */ - setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); - - if (!wait_us(100, clock_is_off(cbcr_addr))) - return CB_ERR; - - return CB_SUCCESS; -} - -static void clock_reset_subsystem(u32 *misc, u32 shft) -{ - clrbits32(misc, BIT(shft)); -} - -void clock_reset_aop(void) -{ - /* Bring AOP out of RESET */ - clock_reset_subsystem(&aoss->aoss_cc_apcs_misc, AOP_RESET_SHFT); + return clock_configure_enable_gpll(&gpll0_cfg, false, 0); } void clock_configure_qspi(uint32_t hz) @@ -206,57 +125,10 @@ clock_enable(&gcc->qspi_core_cbcr); } -void clock_reset_bcr(void *bcr_addr, bool reset) -{ - struct sc7180_bcr *bcr = bcr_addr; - - if (reset) - setbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); - else - clrbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); -} - -static void clock_configure_dfsr_table(int qup, struct clock_config *clk_cfg, - uint32_t num_perfs) -{ - int idx; - int s = qup % QUP_WRAP1_S0; - uint32_t reg_val; - struct sc7180_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? - &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; - - clrsetbits32(&qup_clk->dfsr_clk.cmd_dfsr, - BIT(CLK_CTL_CMD_RCG_SW_CTL_SHFT), - BIT(CLK_CTL_CMD_DFSR_SHFT)); - - for (idx = 0; idx < num_perfs; idx++) { - reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | - (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); - - write32(&qup_clk->dfsr_clk.perf_dfsr[idx], reg_val); - - if (clk_cfg[idx].m == 0) - continue; - - setbits32(&qup_clk->dfsr_clk.perf_dfsr[idx], - RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); - - reg_val = clk_cfg[idx].m & CLK_CTL_RCG_MND_BMSK; - write32(&qup_clk->dfsr_clk.perf_m_dfsr[idx], reg_val); - - reg_val = ~(clk_cfg[idx].n - clk_cfg[idx].m) - & CLK_CTL_RCG_MND_BMSK; - write32(&qup_clk->dfsr_clk.perf_n_dfsr[idx], reg_val); - - reg_val = ~(clk_cfg[idx].d_2) & CLK_CTL_RCG_MND_BMSK; - write32(&qup_clk->dfsr_clk.perf_d_dfsr[idx], reg_val); - } -} - void clock_configure_dfsr(int qup) { clock_configure_dfsr_table(qup, qupv3_wrap_cfg, - ARRAY_SIZE(qupv3_wrap_cfg)); + ARRAY_SIZE(qupv3_wrap_cfg)); } void clock_enable_qup(int qup) @@ -264,51 +136,40 @@ int s = qup % QUP_WRAP1_S0; int clk_en_off = qup < QUP_WRAP1_S0 ? QUPV3_WRAP0_CLK_ENA_S(s) : QUPV3_WRAP1_CLK_ENA_S(s); - struct sc7180_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? + struct qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; - clock_enable_vote(&qup_clk->mnd_clk, &gcc->apcs_clk_br_en1, - clk_en_off); -} - -static enum cb_err agera_pll_enable(u32 *mode, u32 *opmode) -{ - setbits32(mode, BIT(BYPASSNL_SHFT)); - udelay(5); - setbits32(mode, BIT(RESET_SHFT)); - - setbits32(opmode, RUN_MODE); - - if (!wait_us(100, read32(mode) & LOCK_DET_BMSK)) { - printk(BIOS_ERR, "ERROR: PLL did not lock!\n"); - return CB_ERR; - } - - setbits32(mode, BIT(OUTCTRL_SHFT)); - - return CB_SUCCESS; + clock_enable_vote(&qup_clk->cbcr, &gcc->apcs_clk_br_en1, + clk_en_off); } static enum cb_err pll_init_and_set(struct sc7180_apss_clock *apss, u32 l_val) { + struct alpha_pll_reg_val_config pll_cfg = {0}; int ret; u32 gfmux_val; - /* Configure and Enable PLL */ - write32(&apss->pll.config_ctl_lo, 0x0); - setbits32(&apss->pll.config_ctl_lo, 0x2 << CTUNE_SHFT | - 0x2 << K_I_SHFT | 0x5 << K_P_SHFT | - 0x2 << PFA_MSB_SHFT | 0x2 << REF_CONT_SHFT); + pll_cfg.reg_config_ctl = &apss->pll.config_ctl_lo; + pll_cfg.reg_config_ctl_hi = &apss->pll.config_ctl_hi; + pll_cfg.reg_config_ctl_hi1 = &apss->pll.config_ctl_u1; - write32(&apss->pll.config_ctl_hi, 0x0); - setbits32(&apss->pll.config_ctl_hi, 0x2 << CUR_ADJ_SHFT | - BIT(DMET_SHFT) | 0xF << RES_SHFT); + pll_cfg.config_ctl_val = (0x2 << CTUNE_SHFT | 0x2 << K_I_SHFT | + 0x5 << K_P_SHFT | 0x2 << PFA_MSB_SHFT | + 0x2 << REF_CONT_SHFT); + pll_cfg.config_ctl_hi_val = (0x2 << CUR_ADJ_SHFT | BIT(DMET_SHFT) | + 0xF << RES_SHFT); write32(&apss->pll.config_ctl_u1, 0x0); - write32(&apss->pll.l_val, l_val); + pll_cfg.reg_l = &apss->pll.l; + pll_cfg.l_val = l_val; - ret = agera_pll_enable(&apss->pll.mode, &apss->pll.opmode); - if (ret != CB_SUCCESS) + ret = clock_configure_enable_gpll(&pll_cfg, false, 0); + if (ret < 0) + return CB_ERR; + + pll_cfg.reg_mode = &apss->pll.mode; + ret = agera_pll_enable(&pll_cfg); + if (ret < 0) return CB_ERR; gfmux_val = read32(&apss->cfg_gfmux) & ~GFMUX_SRC_SEL_BMSK; @@ -333,8 +194,7 @@ uint32_t divider, uint32_t m, uint32_t n, uint32_t d_2) { - struct clock_config mdss_clk_cfg; - uint32_t reg_val; + struct clock_freq_config mdss_clk_cfg; if (clk_type >= MDSS_CLK_COUNT) return CB_ERR; @@ -355,33 +215,17 @@ mdss_clk_cfg.n = n; mdss_clk_cfg.d_2 = d_2; - /* configure and set the clock */ - reg_val = (mdss_clk_cfg.src << CLK_CTL_CFG_SRC_SEL_SHFT) | - (mdss_clk_cfg.div << CLK_CTL_CFG_SRC_DIV_SHFT); - - write32(&mdss_clock[clk_type]->clock.rcg_cfg, reg_val); - - /* Set m/n/d values for a specific clock */ - if (mdss_clk_cfg.m != 0) - clock_configure_mnd((struct sc7180_clock *)mdss_clock[clk_type], - mdss_clk_cfg.m, mdss_clk_cfg.n, mdss_clk_cfg.d_2); - - /* Commit config to RCG */ - setbits32(&mdss_clock[clk_type]->clock.rcg_cmd, - BIT(CLK_CTL_CMD_UPDATE_SHFT)); - - return CB_SUCCESS; + return clock_configure((struct clock_rcg *)mdss_clock[clk_type], + &mdss_clk_cfg, 0, 0); } int mdss_clock_enable(enum mdss_clock clk_type) { if (clk_type >= MDSS_CLK_COUNT) - return -1; + return CB_ERR; /* Enable clock*/ - clock_enable(mdss_cbcr[clk_type]); - - return 0; + return clock_enable(mdss_cbcr[clk_type]); } void clock_init(void) diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index bb46062..4e80fe8 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -2,69 +2,46 @@ #include <soc/addressmap.h> #include <types.h> +#include <soc/clock_common.h> #ifndef __SOC_QUALCOMM_SC7180_CLOCK_H__ #define __SOC_QUALCOMM_SC7180_CLOCK_H__ -#define QUPV3_WRAP_0_M_AHB_CLK_ENA 6 -#define QUPV3_WRAP_0_S_AHB_CLK_ENA 7 -#define QUPV3_WRAP0_CORE_2X_CLK_ENA 9 -#define QUPV3_WRAP0_CORE_CLK_ENA 8 -#define QUPV3_WRAP1_CORE_2X_CLK_ENA 18 -#define QUPV3_WRAP1_CORE_CLK_ENA 19 -#define QUPV3_WRAP_1_M_AHB_CLK_ENA 20 -#define QUPV3_WRAP_1_S_AHB_CLK_ENA 21 -#define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx) -#define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx) - #define SRC_XO_HZ (19200 * KHz) #define GPLL0_EVEN_HZ (300 * MHz) #define GPLL0_MAIN_HZ (600 * MHz) -#define SRC_XO_19_2MHZ 0 -#define SRC_GPLL0_MAIN_600MHZ 1 -#define SRC_GPLL0_EVEN_300MHZ 6 +#define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx) +#define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx) -#define AOP_RESET_SHFT 0 -#define RCG_MODE_DUAL_EDGE 2 - -#define SCALE_FREQ_SHFT 11 - -struct sc7180_clock { - u32 rcg_cmd; - u32 rcg_cfg; +enum apcs_branch_en_vote { + QUPV3_WRAP_0_M_AHB_CLK_ENA = 6, + QUPV3_WRAP_0_S_AHB_CLK_ENA = 7, + QUPV3_WRAP0_CORE_CLK_ENA = 8, + QUPV3_WRAP0_CORE_2X_CLK_ENA = 9, + QUPV3_WRAP1_CORE_2X_CLK_ENA = 18, + QUPV3_WRAP1_CORE_CLK_ENA = 19, + QUPV3_WRAP_1_M_AHB_CLK_ENA = 20, + QUPV3_WRAP_1_S_AHB_CLK_ENA = 21, }; -struct sc7180_mnd_clock { - struct sc7180_clock clock; - u32 m; - u32 n; - u32 d_2; +enum clk_pll_src { + SRC_XO_19_2MHZ = 0, + SRC_GPLL0_MAIN_600MHZ = 1, + SRC_GPLL0_EVEN_300MHZ = 6, }; -struct sc7180_dfsr_clock { - u32 cmd_dfsr; - u8 _res0[0x20 - 0x1c]; - u32 perf_dfsr[8]; - u8 _res1[0x60 - 0x40]; - u32 perf_m_dfsr[8]; - u8 _res2[0xa0 - 0x80]; - u32 perf_n_dfsr[8]; - u8 _res3[0xe0 - 0xc0]; - u32 perf_d_dfsr[8]; - u8 _res4[0x130 - 0x100]; -}; +/* CPU PLL */ +#define L_VAL_1516P8MHz 0x4F +#define L_VAL_1209P6MHz 0x3F -struct sc7180_qupv3_clock { - u32 cbcr; - struct sc7180_mnd_clock mnd_clk; - struct sc7180_dfsr_clock dfsr_clk; -}; +#define AOP_RESET_SHFT 0 +#define SCALE_FREQ_SHFT 11 struct sc7180_gpll { u32 mode; - u32 l_val; - u32 cal_l_val; + u32 l; + u32 cal_l; u32 user_ctl; u32 user_ctl_u; u32 config_ctl; @@ -85,16 +62,16 @@ u32 qup_wrap0_core_cbcr; u32 qup_wrap0_core_cdivr; u32 qup_wrap0_core_2x_cbcr; - struct sc7180_clock qup_wrap0_core_2x; + struct clock_rcg qup_wrap0_core_2x; u8 _res2[0x17030 - 0x17020]; - struct sc7180_qupv3_clock qup_wrap0_s[6]; + struct qupv3_clock qup_wrap0_s[6]; u8 _res3[0x18000 - 0x17750]; u32 qup_wrap1_bcr; u32 qup_wrap1_core_2x_cbcr; u32 qup_wrap1_core_cbcr; u32 qup_wrap1_m_ahb_cbcr; u32 qup_wrap1_s_ahb_cbcr; - struct sc7180_qupv3_clock qup_wrap1_s[6]; + struct qupv3_clock qup_wrap1_s[6]; u8 _res4[0x18994 - 0x18734]; u32 qup_wrap1_core_cdivr; u8 _res5[0x26000 - 0x18998]; @@ -103,7 +80,7 @@ u32 qspi_bcr; u32 qspi_cnoc_ahb_cbcr; u32 qspi_core_cbcr; - struct sc7180_clock qspi_core; + struct clock_rcg qspi_core; u8 _res7[0x50000 - 0x4b014]; u32 usb3_phy_prim_bcr; u32 usb3phy_phy_prim_bcr; @@ -124,15 +101,6 @@ check_member(sc7180_gcc, usb3_phy_prim_bcr, 0x50000); check_member(sc7180_gcc, apcs_clk_br_en1, 0x52008); -struct sc7180_aoss { - u8 _res0[0x50020]; - u32 aoss_cc_reset_status; - u8 _res1[0x5002C - 0x50024]; - u32 aoss_cc_apcs_misc; -}; -check_member(sc7180_aoss, aoss_cc_reset_status, 0x50020); -check_member(sc7180_aoss, aoss_cc_apcs_misc, 0x5002C); - struct sc7180_disp_cc { u8 _res0[0x2004]; u32 pclk0_cbcr; @@ -142,11 +110,11 @@ u8 _res2[0x2038 - 0x2030]; u32 esc0_cbcr; u8 _res3[0x2098 - 0x203C]; - struct sc7180_mnd_clock pclk0; + struct clock_rcg_mnd pclk0; u8 _res4[0x2110 - 0x20AC]; - struct sc7180_mnd_clock byte0; + struct clock_rcg_mnd byte0; u8 _res5[0x2148 - 0x2124]; - struct sc7180_mnd_clock esc0; + struct clock_rcg_mnd esc0; u8 _res6[0x10000 - 0x215C]; }; check_member(sc7180_disp_cc, byte0_cbcr, 0x2028); @@ -160,56 +128,6 @@ MDSS_CLK_COUNT }; -enum clk_ctl_gpll_user_ctl { - CLK_CTL_GPLL_PLLOUT_EVEN_BMSK = 0x2, - CLK_CTL_GPLL_PLLOUT_MAIN_SHFT = 0, - CLK_CTL_GPLL_PLLOUT_EVEN_SHFT = 1, - CLK_CTL_GPLL_PLLOUT_ODD_SHFT = 2 -}; - -enum clk_ctl_cfg_rcgr { - CLK_CTL_CFG_HW_CTL_BMSK = 0x100000, - CLK_CTL_CFG_HW_CTL_SHFT = 20, - CLK_CTL_CFG_MODE_BMSK = 0x3000, - CLK_CTL_CFG_MODE_SHFT = 12, - CLK_CTL_CFG_SRC_SEL_BMSK = 0x700, - CLK_CTL_CFG_SRC_SEL_SHFT = 8, - CLK_CTL_CFG_SRC_DIV_BMSK = 0x1F, - CLK_CTL_CFG_SRC_DIV_SHFT = 0 -}; - -enum clk_ctl_cmd_rcgr { - CLK_CTL_CMD_ROOT_OFF_BMSK = 0x80000000, - CLK_CTL_CMD_ROOT_OFF_SHFT = 31, - CLK_CTL_CMD_ROOT_EN_BMSK = 0x2, - CLK_CTL_CMD_ROOT_EN_SHFT = 1, - CLK_CTL_CMD_UPDATE_BMSK = 0x1, - CLK_CTL_CMD_UPDATE_SHFT = 0 -}; - -enum clk_ctl_cbcr { - CLK_CTL_CBC_CLK_OFF_BMSK = 0x80000000, - CLK_CTL_CBC_CLK_OFF_SHFT = 31, - CLK_CTL_CBC_CLK_EN_BMSK = 0x1, - CLK_CTL_CBC_CLK_EN_SHFT = 0 -}; - -enum clk_ctl_rcg_mnd { - CLK_CTL_RCG_MND_BMSK = 0xFFFF, - CLK_CTL_RCG_MND_SHFT = 0, -}; - -enum clk_ctl_bcr { - CLK_CTL_BCR_BLK_ARES_BMSK = 0x1, - CLK_CTL_BCR_BLK_ARES_SHFT = 0, -}; - -enum clk_ctl_dfsr { - CLK_CTL_CMD_DFSR_BMSK = 0x1, - CLK_CTL_CMD_DFSR_SHFT = 0, - CLK_CTL_CMD_RCG_SW_CTL_SHFT = 15, -}; - enum clk_qup { QUP_WRAP0_S0, QUP_WRAP0_S1, @@ -225,23 +143,10 @@ QUP_WRAP1_S5, }; -struct clock_config { - uint32_t hz; - uint8_t src; - uint8_t div; - uint16_t m; - uint16_t n; - uint16_t d_2; -}; - -/* CPU PLL */ -#define L_VAL_1516P8MHz 0x4F -#define L_VAL_1209P6MHz 0x3F - struct sc7180_apss_pll { u32 mode; - u32 l_val; - u32 alpha_val; + u32 l; + u32 alpha; u32 user_ctl; u32 config_ctl_lo; u32 config_ctl_hi; @@ -261,34 +166,25 @@ }; enum pll_config_ctl_lo { - CTUNE_SHFT = 2, - K_I_SHFT = 4, - K_P_SHFT = 7, - PFA_MSB_SHFT = 10, - REF_CONT_SHFT = 28, + CTUNE_SHFT = 2, + K_I_SHFT = 4, + K_P_SHFT = 7, + PFA_MSB_SHFT = 10, + REF_CONT_SHFT = 28, }; enum pll_config_ctl_hi { - CUR_ADJ_SHFT = 0, - DMET_SHFT = 4, - RES_SHFT = 6, -}; - -enum pll_mode { - LOCK_DET_BMSK = 0x80000000, - RUN_MODE = 1, - OUTCTRL_SHFT = 0, - BYPASSNL_SHFT = 1, - RESET_SHFT = 2, + CUR_ADJ_SHFT = 0, + DMET_SHFT = 4, + RES_SHFT = 6, }; enum apss_gfmux { GFMUX_SRC_SEL_BMSK = 0x3, - APCS_SRC_EARLY = 0x2, + APCS_SRC_EARLY = 0x2, }; static struct sc7180_gcc *const gcc = (void *)GCC_BASE; -static struct sc7180_aoss *const aoss = (void *)AOSS_CC_BASE; static struct sc7180_apss_clock *const apss_silver = (void *)SILVER_PLL_BASE; static struct sc7180_apss_clock *const apss_l3 = (void *)L3_PLL_BASE; static struct sc7180_disp_cc *const mdss = (void *)DISP_CC_BASE; @@ -296,7 +192,6 @@ void clock_init(void); void clock_reset_aop(void); void clock_configure_qspi(uint32_t hz); -void clock_reset_bcr(void *bcr_addr, bool reset); void clock_configure_qup(int qup, uint32_t hz); void clock_enable_qup(int qup); void clock_configure_dfsr(int qup); @@ -304,4 +199,8 @@ uint32_t divider, uint32_t m, uint32_t n, uint32_t d); int mdss_clock_enable(enum mdss_clock clk_type); +static struct aoss *const aoss = (void *)AOSS_CC_BASE; +#define clock_reset_aop() \ + clock_reset_subsystem(&aoss->aoss_cc_apcs_misc, AOP_RESET_SHFT) + #endif // __SOC_QUALCOMM_SC7180_CLOCK_H__ -- To view, visit https://review.coreboot.org/c/coreboot/+/56588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03d1b4a2fb90303c7259ec08f312d78b4e33ec39 Gerrit-Change-Number: 56588 Gerrit-PatchSet: 8 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/qualcomm/common: clock: Add support for common clock driver
by Shelley Chen (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Ravi kumar, Taniya Das, Paul Menzel, mturney mturney, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56588 ) Change subject: soc/qualcomm/common: clock: Add support for common clock driver ...................................................................... Patch Set 7: (1 comment) File src/soc/qualcomm/common/clock.c: https://review.coreboot.org/c/coreboot/+/56588/comment/f3425ae2_33e53e28 PS2, Line 188: printk(BIOS_ERR, "ERROR: PLL did not lock!\n"); > Yes the CPU would be on a default general purpose PLL which would be at a very low frequency. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03d1b4a2fb90303c7259ec08f312d78b4e33ec39 Gerrit-Change-Number: 56588 Gerrit-PatchSet: 7 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 03 Sep 2021 06:04:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Taniya Das <tdas(a)codeaurora.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: qualcomm/sc7180: Clean up drivers with common clock
by Shelley Chen (Code Review) 03 Sep '21

03 Sep '21

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56587 ) Change subject: qualcomm/sc7180: Clean up drivers with common clock ...................................................................... qualcomm/sc7180: Clean up drivers with common clock As we move to use the common clock driver, the sc7180 clock driver, watchdog and display drivers requires few cleanups, thus update the impacted drivers. Earlier the display client is expected to provide 2n divider value, as the divider value in register is in form "2n-1". mdss_clk_cfg.div = half_divider ? (half_divider - 1) : 0; The older convention in the upcoming patches would be replaced with the common macro of QCOM_CLOCK_DIV, thus need the divider needs to be updated. mdss_clk_cfg.div = half_divider ? QCOM_CLOCK_DIV(half_divider) : 0; To accommodate impacting the functionality, the half_divider is taken care in the clock driver. BUG=b:182963902 TEST=Validated on qualcomm sc7180 development board Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66 Signed-off-by: Taniya Das <tdas(a)codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56587 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shelley Chen <shchen(a)google.com> --- M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/display/dsi_phy.c M src/soc/qualcomm/sc7180/include/soc/clock.h M src/soc/qualcomm/sc7180/watchdog.c 4 files changed, 70 insertions(+), 68 deletions(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 8763a9d..8bf450a 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -11,14 +11,6 @@ #define DIV(div) (2 * div - 1) -struct clock_config qup_cfg[] = { - { - .hz = SRC_XO_HZ, /* 19.2KHz */ - .src = SRC_XO_19_2MHZ, - .div = DIV(1), - } -}; - struct clock_config qspi_core_cfg[] = { { .hz = SRC_XO_HZ, /* 19.2KHz */ @@ -42,7 +34,7 @@ } }; -struct clock_config qup_wrap_cfg[] = { +struct clock_config qupv3_wrap_cfg[] = { { .hz = SRC_XO_HZ, /* 19.2KHz */ .src = SRC_XO_19_2MHZ, @@ -124,8 +116,8 @@ return 0; } -static int clock_configure_mnd(struct sc7180_clock *clk, uint32_t m, uint32_t n, - uint32_t d_2) +static void clock_configure_mnd(struct sc7180_clock *clk, uint32_t m, + uint32_t n, uint32_t d_2) { struct sc7180_mnd_clock *mnd = (struct sc7180_mnd_clock *)clk; setbits32(&clk->rcg_cfg, @@ -134,11 +126,9 @@ write32(&mnd->m, m & CLK_CTL_RCG_MND_BMSK); write32(&mnd->n, ~(n-m) & CLK_CTL_RCG_MND_BMSK); write32(&mnd->d_2, ~(d_2) & CLK_CTL_RCG_MND_BMSK); - - return 0; } -static int clock_configure(struct sc7180_clock *clk, +static enum cb_err clock_configure(struct sc7180_clock *clk, struct clock_config *clk_cfg, uint32_t hz, uint32_t num_perfs) { @@ -164,7 +154,7 @@ /* Commit config to RCG*/ setbits32(&clk->rcg_cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); - return 0; + return CB_SUCCESS; } static bool clock_is_off(u32 *cbcr_addr) @@ -172,35 +162,39 @@ return (read32(cbcr_addr) & CLK_CTL_CBC_CLK_OFF_BMSK); } -static int clock_enable_vote(void *cbcr_addr, void *vote_addr, +static enum cb_err clock_enable_vote(void *cbcr_addr, void *vote_addr, uint32_t vote_bit) { /* Set clock vote bit */ setbits32(vote_addr, BIT(vote_bit)); /* Ensure clock is enabled */ - while (clock_is_off(cbcr_addr)) - ; + if (!wait_us(100, clock_is_off(cbcr_addr))) + return CB_ERR; - return 0; + return CB_SUCCESS; } -static int clock_enable(void *cbcr_addr) +static enum cb_err clock_enable(void *cbcr_addr) { /* Set clock enable bit */ setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); - /* Ensure clock is enabled */ - while (clock_is_off(cbcr_addr)) - ; + if (!wait_us(100, clock_is_off(cbcr_addr))) + return CB_ERR; - return 0; + return CB_SUCCESS; +} + +static void clock_reset_subsystem(u32 *misc, u32 shft) +{ + clrbits32(misc, BIT(shft)); } void clock_reset_aop(void) { /* Bring AOP out of RESET */ - clrbits32(&aoss->aoss_cc_apcs_misc, BIT(AOP_RESET_SHFT)); + clock_reset_subsystem(&aoss->aoss_cc_apcs_misc, AOP_RESET_SHFT); } void clock_configure_qspi(uint32_t hz) @@ -212,7 +206,7 @@ clock_enable(&gcc->qspi_core_cbcr); } -int clock_reset_bcr(void *bcr_addr, bool reset) +void clock_reset_bcr(void *bcr_addr, bool reset) { struct sc7180_bcr *bcr = bcr_addr; @@ -220,11 +214,10 @@ setbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); else clrbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); - - return 0; } -void clock_configure_dfsr(int qup) +static void clock_configure_dfsr_table(int qup, struct clock_config *clk_cfg, + uint32_t num_perfs) { int idx; int s = qup % QUP_WRAP1_S0; @@ -236,38 +229,34 @@ BIT(CLK_CTL_CMD_RCG_SW_CTL_SHFT), BIT(CLK_CTL_CMD_DFSR_SHFT)); - for (idx = 0; idx < ARRAY_SIZE(qup_wrap_cfg); idx++) { - reg_val = (qup_wrap_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | - (qup_wrap_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + for (idx = 0; idx < num_perfs; idx++) { + reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); write32(&qup_clk->dfsr_clk.perf_dfsr[idx], reg_val); - if (qup_wrap_cfg[idx].m == 0) + if (clk_cfg[idx].m == 0) continue; setbits32(&qup_clk->dfsr_clk.perf_dfsr[idx], RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); - reg_val = qup_wrap_cfg[idx].m & CLK_CTL_RCG_MND_BMSK; + reg_val = clk_cfg[idx].m & CLK_CTL_RCG_MND_BMSK; write32(&qup_clk->dfsr_clk.perf_m_dfsr[idx], reg_val); - reg_val = ~(qup_wrap_cfg[idx].n - qup_wrap_cfg[idx].m) + reg_val = ~(clk_cfg[idx].n - clk_cfg[idx].m) & CLK_CTL_RCG_MND_BMSK; write32(&qup_clk->dfsr_clk.perf_n_dfsr[idx], reg_val); - reg_val = ~(qup_wrap_cfg[idx].d_2) & CLK_CTL_RCG_MND_BMSK; + reg_val = ~(clk_cfg[idx].d_2) & CLK_CTL_RCG_MND_BMSK; write32(&qup_clk->dfsr_clk.perf_d_dfsr[idx], reg_val); } } -void clock_configure_qup(int qup, uint32_t hz) +void clock_configure_dfsr(int qup) { - int s = qup % QUP_WRAP1_S0; - struct sc7180_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? - &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; - - clock_configure(&qup_clk->mnd_clk.clock, qup_cfg, hz, - ARRAY_SIZE(qup_cfg)); + clock_configure_dfsr_table(qup, qupv3_wrap_cfg, + ARRAY_SIZE(qupv3_wrap_cfg)); } void clock_enable_qup(int qup) @@ -282,8 +271,27 @@ clk_en_off); } -static int pll_init_and_set(struct sc7180_apss_clock *apss, u32 l_val) +static enum cb_err agera_pll_enable(u32 *mode, u32 *opmode) { + setbits32(mode, BIT(BYPASSNL_SHFT)); + udelay(5); + setbits32(mode, BIT(RESET_SHFT)); + + setbits32(opmode, RUN_MODE); + + if (!wait_us(100, read32(mode) & LOCK_DET_BMSK)) { + printk(BIOS_ERR, "ERROR: PLL did not lock!\n"); + return CB_ERR; + } + + setbits32(mode, BIT(OUTCTRL_SHFT)); + + return CB_SUCCESS; +} + +static enum cb_err pll_init_and_set(struct sc7180_apss_clock *apss, u32 l_val) +{ + int ret; u32 gfmux_val; /* Configure and Enable PLL */ @@ -299,24 +307,15 @@ write32(&apss->pll.config_ctl_u1, 0x0); write32(&apss->pll.l_val, l_val); - setbits32(&apss->pll.mode, BIT(BYPASSNL_SHFT)); - udelay(5); - setbits32(&apss->pll.mode, BIT(RESET_SHFT)); - - setbits32(&apss->pll.opmode, RUN_MODE); - - if (!wait_us(100, read32(&apss->pll.mode) & LOCK_DET_BMSK)) { - printk(BIOS_ERR, "ERROR: PLL did not lock!\n"); - return -1; - } - - setbits32(&apss->pll.mode, BIT(OUTCTRL_SHFT)); + ret = agera_pll_enable(&apss->pll.mode, &apss->pll.opmode); + if (ret != CB_SUCCESS) + return CB_ERR; gfmux_val = read32(&apss->cfg_gfmux) & ~GFMUX_SRC_SEL_BMSK; gfmux_val |= APCS_SRC_EARLY; write32(&apss->cfg_gfmux, gfmux_val); - return 0; + return CB_SUCCESS; } static void speed_up_boot_cpu(void) @@ -330,25 +329,28 @@ printk(BIOS_DEBUG, "L3 Frequency bumped to 1.2096(GHz)\n"); } -int mdss_clock_configure(enum mdss_clock clk_type, uint32_t source, - uint32_t half_divider, uint32_t m, +enum cb_err mdss_clock_configure(enum mdss_clock clk_type, uint32_t source, + uint32_t divider, uint32_t m, uint32_t n, uint32_t d_2) { struct clock_config mdss_clk_cfg; uint32_t reg_val; if (clk_type >= MDSS_CLK_COUNT) - return -1; + return CB_ERR; /* Initialize it with received arguments */ mdss_clk_cfg.hz = 0; mdss_clk_cfg.src = source; /* + * Update half_divider passed from display, this is to accommodate + * the transition to common clock driver. + * * client is expected to provide 2n divider value, * as the divider value in register is in form "2n-1" */ - mdss_clk_cfg.div = half_divider ? (half_divider - 1) : 0; + mdss_clk_cfg.div = divider ? ((divider * 2) - 1) : 0; mdss_clk_cfg.m = m; mdss_clk_cfg.n = n; mdss_clk_cfg.d_2 = d_2; @@ -368,7 +370,7 @@ setbits32(&mdss_clock[clk_type]->clock.rcg_cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); - return 0; + return CB_SUCCESS; } int mdss_clock_enable(enum mdss_clock clk_type) diff --git a/src/soc/qualcomm/sc7180/display/dsi_phy.c b/src/soc/qualcomm/sc7180/display/dsi_phy.c index db4b67c..a7b04a8 100644 --- a/src/soc/qualcomm/sc7180/display/dsi_phy.c +++ b/src/soc/qualcomm/sc7180/display/dsi_phy.c @@ -722,7 +722,7 @@ {.clk_type = MDSS_CLK_PCLK0, .clk_source = 1}, {.clk_type = MDSS_CLK_BYTE0, .clk_source = 1}, {.clk_type = MDSS_CLK_BYTE0_INTF, .clk_source = 1, - .clk_div = 2, .source_div = 2}, + .clk_div = 1, .source_div = 2}, }; for (i = 0; i < ARRAY_SIZE(clks); i++) { diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index b303efe..bb46062 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -28,8 +28,6 @@ #define AOP_RESET_SHFT 0 #define RCG_MODE_DUAL_EDGE 2 -#define WDOG_RESET_BIT_MASK 1 - #define SCALE_FREQ_SHFT 11 struct sc7180_clock { @@ -298,12 +296,12 @@ void clock_init(void); void clock_reset_aop(void); void clock_configure_qspi(uint32_t hz); -int clock_reset_bcr(void *bcr_addr, bool reset); +void clock_reset_bcr(void *bcr_addr, bool reset); void clock_configure_qup(int qup, uint32_t hz); void clock_enable_qup(int qup); void clock_configure_dfsr(int qup); int mdss_clock_configure(enum mdss_clock clk_type, uint32_t source, - uint32_t half_divider, uint32_t m, uint32_t n, uint32_t d); + uint32_t divider, uint32_t m, uint32_t n, uint32_t d); int mdss_clock_enable(enum mdss_clock clk_type); #endif // __SOC_QUALCOMM_SC7180_CLOCK_H__ diff --git a/src/soc/qualcomm/sc7180/watchdog.c b/src/soc/qualcomm/sc7180/watchdog.c index 0b7dd6d..680d70b 100644 --- a/src/soc/qualcomm/sc7180/watchdog.c +++ b/src/soc/qualcomm/sc7180/watchdog.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/watchdog.h> #include <soc/clock.h> +#include <soc/watchdog.h> #include <device/mmio.h> #include <vendorcode/google/chromeos/chromeos.h> +#define WDOG_RESET_BIT_MASK 1 + void check_wdog(void) { uint32_t wdog_sta = read32(&aoss->aoss_cc_reset_status); -- To view, visit https://review.coreboot.org/c/coreboot/+/56587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66 Gerrit-Change-Number: 56587 Gerrit-PatchSet: 9 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: qualcomm/sc7180: Clean up drivers with common clock
by Shelley Chen (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Ravi kumar, Paul Menzel, mturney mturney, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56587 ) Change subject: qualcomm/sc7180: Clean up drivers with common clock ...................................................................... Patch Set 8: (1 comment) File src/soc/qualcomm/sc7180/clock.c: https://review.coreboot.org/c/coreboot/+/56587/comment/cf21f44f_04c8e1b4 PS5, Line 171: ; > nit: can you fix the extra semicolon while you're making other changes? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66 Gerrit-Change-Number: 56587 Gerrit-PatchSet: 8 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 03 Sep 2021 06:02:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: preserve WDT reset reason for debugging
by Hung-Te Lin (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Rex-BC Chen, Paul Menzel, Felix Held. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57270 ) Change subject: soc/mediatek: preserve WDT reset reason for debugging ...................................................................... Patch Set 5: (1 comment) File src/soc/mediatek/common/wdt.c: https://review.coreboot.org/c/coreboot/+/57270/comment/a1304c17_b428b21d PS2, Line 22: write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); > (This GPIO is not controlled by sw driver.) But we're already doing that in kukui/asurada/cherry boards? (`gpio_output(GPIO_RESET, 1)) -- To view, visit https://review.coreboot.org/c/coreboot/+/57270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5887a8312f4daab3cbd0a30fea0195670a932e52 Gerrit-Change-Number: 57270 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Sep 2021 05:57:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: preserve WDT reset reason for debugging
by Rex-BC Chen (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Felix Held. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57270 ) Change subject: soc/mediatek: preserve WDT reset reason for debugging ...................................................................... Patch Set 5: (1 comment) File src/soc/mediatek/common/wdt.c: https://review.coreboot.org/c/coreboot/+/57270/comment/9c50034f_8adb7c8f PS2, Line 22: write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); > then isn't it GPIO_RESET (e.g. […] WDT signal is controlled by wdt hardware. If we need to send signal, wdt hardware will send signal to this GPIO. (This GPIO is not controlled by sw driver.) -- To view, visit https://review.coreboot.org/c/coreboot/+/57270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5887a8312f4daab3cbd0a30fea0195670a932e52 Gerrit-Change-Number: 57270 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Sep 2021 05:54:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: preserve WDT reset reason for debugging
by Hung-Te Lin (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Rex-BC Chen, Paul Menzel, Felix Held. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57270 ) Change subject: soc/mediatek: preserve WDT reset reason for debugging ...................................................................... Patch Set 5: (1 comment) File src/soc/mediatek/common/wdt.c: https://review.coreboot.org/c/coreboot/+/57270/comment/429ce1a1_bd9039b9 PS2, Line 22: write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); > for 2nd reset, we need to tell EC to reset. then isn't it GPIO_RESET (e.g., do_board_reset)? -- To view, visit https://review.coreboot.org/c/coreboot/+/57270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5887a8312f4daab3cbd0a30fea0195670a932e52 Gerrit-Change-Number: 57270 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Sep 2021 05:42:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard/herobrine: Initialize SPI FW for EC and TPM
by Ravi Kumar Bokka (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney, Julius Werner, Rajesh Patil. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50581 ) Change subject: src/mainboard/herobrine: Initialize SPI FW for EC and TPM ...................................................................... Patch Set 65: (1 comment) File src/mainboard/google/herobrine/Kconfig: https://review.coreboot.org/c/coreboot/+/50581/comment/97b461df_4d151ce1 PS58, Line 49: config DRIVER_TPM_SPI_BUS : hex : default 0xE : > Just found out that we're going to use the i2c communication lines for TPM, so this should be DRIVER […] HI Shelly, We have differentiated TPM GPIO configuration in below gerrit: https://review.coreboot.org/c/coreboot/+/57186/2 now we squash both changes in single gerrit. -Ravi -- To view, visit https://review.coreboot.org/c/coreboot/+/50581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c Gerrit-Change-Number: 50581 Gerrit-PatchSet: 65 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 05:41:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit September 2021