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Change subject: soc/qualcomm/common: clock: Add support for common clock driver
......................................................................
Patch Set 7:
(1 comment)
File src/soc/qualcomm/common/clock.c:
https://review.coreboot.org/c/coreboot/+/56588/comment/f3425ae2_33e53e28
PS2, Line 188: printk(BIOS_ERR, "ERROR: PLL did not lock!\n");
> Yes the CPU would be on a default general purpose PLL which would be at a very low frequency.
Done
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Change subject: qualcomm/sc7180: Clean up drivers with common clock
......................................................................
Patch Set 8:
(1 comment)
File src/soc/qualcomm/sc7180/clock.c:
https://review.coreboot.org/c/coreboot/+/56587/comment/cf21f44f_04c8e1b4
PS5, Line 171: ;
> nit: can you fix the extra semicolon while you're making other changes?
Done
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Change subject: soc/mediatek: preserve WDT reset reason for debugging
......................................................................
Patch Set 5:
(1 comment)
File src/soc/mediatek/common/wdt.c:
https://review.coreboot.org/c/coreboot/+/57270/comment/a1304c17_b428b21d
PS2, Line 22: write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
> (This GPIO is not controlled by sw driver.)
But we're already doing that in kukui/asurada/cherry boards? (`gpio_output(GPIO_RESET, 1))
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Change subject: soc/mediatek: preserve WDT reset reason for debugging
......................................................................
Patch Set 5:
(1 comment)
File src/soc/mediatek/common/wdt.c:
https://review.coreboot.org/c/coreboot/+/57270/comment/9c50034f_8adb7c8f
PS2, Line 22: write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
> then isn't it GPIO_RESET (e.g. […]
WDT signal is controlled by wdt hardware.
If we need to send signal, wdt hardware will send signal to this GPIO.
(This GPIO is not controlled by sw driver.)
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Change subject: soc/mediatek: preserve WDT reset reason for debugging
......................................................................
Patch Set 5:
(1 comment)
File src/soc/mediatek/common/wdt.c:
https://review.coreboot.org/c/coreboot/+/57270/comment/429ce1a1_bd9039b9
PS2, Line 22: write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
> for 2nd reset, we need to tell EC to reset.
then isn't it GPIO_RESET (e.g., do_board_reset)?
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Change subject: src/mainboard/herobrine: Initialize SPI FW for EC and TPM
......................................................................
Patch Set 65:
(1 comment)
File src/mainboard/google/herobrine/Kconfig:
https://review.coreboot.org/c/coreboot/+/50581/comment/97b461df_4d151ce1
PS58, Line 49: config DRIVER_TPM_SPI_BUS
: hex
: default 0xE
:
> Just found out that we're going to use the i2c communication lines for TPM, so this should be DRIVER […]
HI Shelly,
We have differentiated TPM GPIO configuration in below gerrit:
https://review.coreboot.org/c/coreboot/+/57186/2
now we squash both changes in single gerrit.
-Ravi
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Change subject: src/mainboard/herobrine: Initialize SPI FW for EC and TPM
......................................................................
Patch Set 65:
(1 comment)
File src/mainboard/google/herobrine/Kconfig:
https://review.coreboot.org/c/coreboot/+/50581/comment/df389c16_47736f2c
PS58, Line 55: 0xA
> i will check with hardware team and update to you
Done
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Change subject: src/mainboard/trogdor: Initialize SPI FW for EC and TPM
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS8:
> unresolving
Hi Shelly,
In trogdor, we are maintaining separate commits for SOC and Mainboard changes.
Due to this reason, we have split this changes separately.
-Ravi
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Paul Menzel, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56628
to look at the new patch set (#11).
Change subject: arch/x86: Refactor the SMBIOS type 17 write function
......................................................................
arch/x86: Refactor the SMBIOS type 17 write function
List of changes:
1. Create Module Type macros as per Memory Type
(i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation
issue due to renaming of existing macros due to scoping the Memory
Type.
2. Skip fixed module type to form factor conversion using DDR2 SPD4
specification (inside dimm_info_fill()).
3. Use dedicated Memory Type and Module type for `Form Factor`
conversion using `get_spd_info()` function.
4. Use dedicated Memory Type and Module type for `TypeDetail`
conversion using `get_spd_info()` function.
5. Create a new API (convert_form_factor_to_module_type()) for
`Form Factor` to 'Module type' conversion as per `Memory Type`.
6. Add DDR5 and LPDDR5 memory technology into the SMBIOS Memory Type
table.
7. Add new argument as `Memory Type`
smbios_form_factor_to_spd_mod_type().
8. smbios_form_factor_to_spd_mod_type() internally calls
convert_form_factor_to_module_type() for `Module Type` conversion.
Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx.
BUG=b:194659789
TEST=Refer to dmidecode -t 17 output as below:
Without this code change:
Handle 0x0012, DMI type 17, 40 bytes
Memory Device
    Array Handle: 0x000A
    Error Information Handle: Not Provided
    Total Width: 16 bits
    Data Width: 16 bits
    Size: 2048 MB
    Form Factor: Unknown
    ....
With this code change:
Handle 0x0012, DMI type 17, 40 bytes
Memory Device
    Array Handle: 0x000A
    Error Information Handle: Not Provided
    Total Width: 16 bits
    Data Width: 16 bits
    Size: 2048 MB
    Form Factor: Row Of Chips
    ....
Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/arch/x86/smbios.c
M src/device/dram/ddr3.c
M src/device/dram/ddr4.c
M src/device/dram/spd.c
M src/include/device/dram/spd.h
M src/include/dimm_info_util.h
M src/include/smbios.h
M src/include/spd.h
M src/lib/dimm_info_util.c
M src/mainboard/scaleway/tagada/ramstage.c
M src/northbridge/intel/haswell/haswell_mrc/raminit.c
M src/soc/amd/common/block/pi/amd_late_init.c
M src/soc/amd/common/fsp/dmi.c
M src/soc/intel/common/smbios.c
14 files changed, 326 insertions(+), 94 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/56628/11
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