coreboot-gerrit September 2021

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Change in coreboot[master]: mb/google/dedede: Create beetley variant
by Paul Menzel (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Zhi7 Li. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57358 ) Change subject: mb/google/dedede: Create beetley variant ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57358/comment/bdd85042_30a9fa04 PS1, Line 12: (Auto-Generated by create_coreboot_variant.sh version 4.5.0). Please move the dot/period before the ). -- To view, visit https://review.coreboot.org/c/coreboot/+/57358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d52be55270361406a67f91707b71dff5c725f35 Gerrit-Change-Number: 57358 Gerrit-PatchSet: 1 Gerrit-Owner: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystal Han <hanlijing(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 08:27:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/gimble: Enable SaGv support
by Paul Menzel (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: YH Lin, Tim Wawrzynczak, Kane Chen, Mark Hsieh, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57357 ) Change subject: mb/google/brya/variants/gimble: Enable SaGv support ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57357/comment/bcb440e9_0a7ea40c PS2, Line 9: This patch enables SaGv support for gimble. Why can it be enabled? -- To view, visit https://review.coreboot.org/c/coreboot/+/57357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29887418827614afb10558c6958c9c5e9667079e Gerrit-Change-Number: 57357 Gerrit-PatchSet: 2 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Sep 2021 08:27:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard/trogdor: Initialize SPI FW for EC and TPM
by Paul Menzel (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Shelley Chen, Ravi kumar. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56398 ) Change subject: src/mainboard/trogdor: Initialize SPI FW for EC and TPM ...................................................................... Patch Set 10: (1 comment) File src/mainboard/google/trogdor/bootblock.c: https://review.coreboot.org/c/coreboot/+/56398/comment/d36ab722_a945a0b4 PS10, Line 10: 1010 * KHz Please mention where the frequency is documented in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/56398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb89e36517f6a32b8b5881b89112dac4a3f292b0 Gerrit-Change-Number: 56398 Gerrit-PatchSet: 10 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Fri, 03 Sep 2021 08:26:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/gooey: Add MT53E512M32D1NP-046 as supported mem ...
by Paul Menzel (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Henry Sun, Stanley Wu, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57310 ) Change subject: mb/google/dedede/var/gooey: Add MT53E512M32D1NP-046 as supported mem module ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57310/comment/ca8da12c_a02974f4 PS1, Line 11: MT53E512M32D1NP-046 WT:B > From Micron AE feedback as below: […] Could you add that to the commit message please? -- To view, visit https://review.coreboot.org/c/coreboot/+/57310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b83126a2bf98bb9d0ca05d397c288e0d99ed781 Gerrit-Change-Number: 57310 Gerrit-PatchSet: 2 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 08:25:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Rename MMCONF Kconfigs to ECAM_MMCONF
by Furquan Shaikh (Code Review) 03 Sep '21

03 Sep '21

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Change in coreboot[master]: Rename MMCONF Kconfigs to ECAM_MMCONF
by Furquan Shaikh (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Stefan Reinauer, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Suresh Bellampalli, Morgan Jang, Michal Motyl, Alexander Couzens, Felix Held, Shelley Chen, Angel Pons, Lance Zhao, Jason Glenesk, Martin Roth, Damien Zammit, Lee Leahy, Marshall Dawson, Tim Wawrzynczak, Vanessa Eusebio, Huang Jin. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57333 ) Change subject: Rename MMCONF Kconfigs to ECAM_MMCONF ...................................................................... Patch Set 5: (13 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/57333/comment/e3dc103b_c5612532 PS3, Line 11: which applies only to x86 platforms Actually, this applies to platforms that support ACPI. https://review.coreboot.org/c/coreboot/+/57333/comment/652b14d9_31b0d602 PS3, Line 11: This can be confusing as : other platforms, such as ARM, use a different way of mapping the pci : config space to memory. > My understanding so far (for QC IIUC) is that there is a single 4K window in MMIO space, and some ot […] That sounds right for QC platform. Other platforms could implement this in other ways too. https://review.coreboot.org/c/coreboot/+/57333/comment/3fb8efc2_9dc97bca PS3, Line 16: NO_ECAM_MMCONF_SUPPORT Reading the PCI firmware specification again, ECAM and MMCONF actually go hand in hand. So, Commit Message: https://review.coreboot.org/c/coreboot/+/57333/comment/ceb292de_5a3d19da PS4, Line 9: the MMCONF Kconfigs only use the Enhanced Configuration : Access mechanism (ECAM) method Reading following two docs again: * PCI base express specification * PCI firmware specification This is what I understand: ECAM and MMCONFIG go hand in hand. PCI base express specification mentions that platforms that support ACPI must implement Enhanced configuration access mechanism (ECAM). This allows PCI configuration space access using memory primitives instead of I/O-based primitives (CF8/CFC). In order to report the memory mapped configuration (MMCONFIG) space base address, MCFG table is used in ACPI. Given that, I think we need to set up things such that: There are two types of PCI ops supported: * PCI_IO_OPS * PCI_MMIO_OPS For PCI_MMIO_OPS, there will be PCI_ECAM which will be selected by default if PCI and ACPI are both selected for a platform. If ACPI is not selected, then the platform can either choose to select PCI_ECAM or it can provide its own access mechanisms. I think the current MMCONF Kconfigs are really a mix of MMIO ops and ECAM. So, we will have to inspect and create two different Kconfigs i.e. PCI_MMIO_OPS and PCI_ECAM and accordingly update the current configs. PCI_MMIO_OPS must be selected by default if PCI is selected unless a platform selects PCI_NO_MMIO_OPS. https://review.coreboot.org/c/coreboot/+/57333/comment/a6cb1a94_48b06689 PS4, Line 11: which applies only to x86 platforms Actually, this applies to platforms that support ACPI. So, if there are non-x86 platforms that support ACPI, they will support ECAM. https://review.coreboot.org/c/coreboot/+/57333/comment/fae77218_acefbd93 PS4, Line 16: NO_ECAM_MMCONF_SUPPORT I think this will have to be renamed to `PCI_NO_MMIO_OPS` https://review.coreboot.org/c/coreboot/+/57333/comment/be0532ce_e5c93a8b PS4, Line 17: ECAM_MMCONF_SUPPORT This will really be either `PCI_ECAM` or `PCI_MMIO_OPS` depending upon how it is used. https://review.coreboot.org/c/coreboot/+/57333/comment/41e121a3_ffd3a241 PS4, Line 18: ECAM_MMCONF_BASE_ADDRESS I think `MMCONF_BASE_ADDRESS` is fine here because that is how the PCI spec uses it. Probably this can be renamed to PCI_MMCONF_BASE_ADDRESS and add dependency on `PCI_ECAM`. https://review.coreboot.org/c/coreboot/+/57333/comment/a74c46cc_cb899b24 PS4, Line 19: MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER : MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Same for these two Kconfigs as `MMCONF_BASE_ADDRESS`. File src/arch/x86/include/arch/pci_io_cfg.h: https://review.coreboot.org/c/coreboot/+/57333/comment/e50876be_5806b636 PS4, Line 72: ECAM_MMCONF_SUPPORT This should be `!CONFIG(PCI_MMIO_OPS)` File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/57333/comment/8eda7e1c_0a70d7ce PS4, Line 502: NO_ECAM_MMCONF_SUPPORT Posted a comment on the commit message about the Kconfigs. File src/northbridge/intel/e7505/Kconfig: https://review.coreboot.org/c/coreboot/+/57333/comment/711d9d6d_ab3d04c9 PS4, Line 10: NO_ECAM_MMCONF_SUPPORT This will have to be changed to PCI_NO_MMIO_OPS File src/soc/intel/quark/Kconfig: https://review.coreboot.org/c/coreboot/+/57333/comment/63335c3b_310ce292 PS4, Line 13: NO_ECAM_MMCONF_SUPPORT This should be PCI_NO_MMIO_OPS -- To view, visit https://review.coreboot.org/c/coreboot/+/57333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Gerrit-Change-Number: 57333 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 08:22:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Rename MMCONF Kconfigs to ECAM_MMCONF
by Shelley Chen (Code Review) 03 Sep '21

03 Sep '21

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Change in coreboot[master]: Rename MMCONF Kconfigs to ECAM_MMCONF
by Shelley Chen (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Stefan Reinauer, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Suresh Bellampalli, Morgan Jang, Michal Motyl, Alexander Couzens, Felix Held, Shelley Chen, Furquan Shaikh, Angel Pons, Lance Zhao, Jason Glenesk, Martin Roth, Damien Zammit, Lee Leahy, Marshall Dawson, Tim Wawrzynczak, Vanessa Eusebio, Huang Jin. Hello build bot (Jenkins), Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Stefan Reinauer, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Suresh Bellampalli, Michal Motyl, Morgan Jang, Alexander Couzens, Felix Held, Furquan Shaikh, Angel Pons, Lance Zhao, Jason Glenesk, Damien Zammit, Martin Roth, Lee Leahy, Marshall Dawson, Tim Wawrzynczak, Vanessa Eusebio, Huang Jin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57333 to look at the new patch set (#5). Change subject: Rename MMCONF Kconfigs to ECAM_MMCONF ...................................................................... Rename MMCONF Kconfigs to ECAM_MMCONF Currently, the MMCONF Kconfigs only use the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space, which applies only to x86 platforms. This can be confusing as other platforms, such as ARM, use a different way of mapping the PCI config space to memory. Renaming the following configs to make it clear that these configs only apply to ECAM: NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER MMCONF_LENGTH --> ECAM_MMCONF_LENGTH BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M payloads/external/Makefile.inc M payloads/external/tianocore/Makefile M src/acpi/dsdt_top.asl M src/arch/x86/include/arch/pci_io_cfg.h M src/device/Kconfig M src/device/device_util.c M src/device/pci_ops.c M src/drivers/intel/fsp1_1/romstage.c M src/include/device/pci_mmio_cfg.h M src/lib/Kconfig M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/acpi_tables.c M src/mainboard/emulation/qemu-q35/bootblock.c M src/mainboard/emulation/qemu-q35/memmap.c M src/mainboard/google/butterfly/early_init.c M src/mainboard/google/link/early_init.c M src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/early_init.c M src/mainboard/intel/dcp847ske/romstage.c M src/mainboard/intel/emeraldlake2/early_init.c M src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/lenovo/x220/early_init.c M src/mainboard/roda/rv11/variants/rv11/early_init.c M src/mainboard/roda/rv11/variants/rw11/early_init.c M src/mainboard/samsung/lumpy/early_init.c M src/mainboard/samsung/stumpy/early_init.c M src/northbridge/amd/agesa/family14/Kconfig M src/northbridge/amd/agesa/family15tn/Kconfig M src/northbridge/amd/agesa/family16kb/Kconfig M src/northbridge/amd/pi/00730F01/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/gm45/acpi/gm45.asl M src/northbridge/intel/gm45/bootblock.c M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/haswell/haswell_mrc/raminit.c M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/i945/acpi/i945.asl M src/northbridge/intel/i945/bootblock.c M src/northbridge/intel/ironlake/Kconfig M src/northbridge/intel/ironlake/acpi.c M src/northbridge/intel/ironlake/acpi/ironlake.asl M src/northbridge/intel/ironlake/bootblock.c M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/acpi.c M src/northbridge/intel/pineview/acpi/pineview.asl M src/northbridge/intel/pineview/bootblock.c M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/acpi.c M src/northbridge/intel/sandybridge/acpi/hostbridge.asl M src/northbridge/intel/sandybridge/bootblock.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/x4x/Kconfig M src/northbridge/intel/x4x/acpi.c M src/northbridge/intel/x4x/acpi/x4x.asl M src/northbridge/intel/x4x/bootblock.c M src/security/intel/stm/StmPlatformResource.c M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/acpi/pci0.asl M src/soc/amd/cezanne/fsp_m_params.c M src/soc/amd/common/block/acpi/tables.c M src/soc/amd/common/block/pci/amd_pci_mmconf.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/fsp_m_params.c M src/soc/amd/stoneyridge/Kconfig M src/soc/cavium/cn81xx/Kconfig M src/soc/example/min86/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/systemagent.c M src/soc/intel/apollolake/systemagent.c M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/acpi/southcluster.asl M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/bootblock.c M src/soc/intel/broadwell/pei_data.c M src/soc/intel/cannonlake/systemagent.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/acpi/northcluster.asl M src/soc/intel/denverton_ns/bootblock/bootblock.c M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/systemagent.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/systemagent.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/systemagent.c M src/soc/intel/quark/Kconfig M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/systemagent.c M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/uncore.c M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/pi/hudson/lpc.c M src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h M src/vendorcode/amd/cimx/sb800/OEM.h 120 files changed, 232 insertions(+), 216 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/57333/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/57333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Gerrit-Change-Number: 57333 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Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki 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Change in coreboot[master]: sc7280: Refactor QUP driver
by Ravi Kumar Bokka (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney, Julius Werner. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55960 ) Change subject: sc7280: Refactor QUP driver ...................................................................... Patch Set 17: (9 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55960/comment/1b53853f_43b9b457 PS15, Line 9: Refactor QUP driver by separating : common and SoC specific driver code : > This should probably say something like "Enable common qup driver in sc7280" instead. Ack File src/soc/qualcomm/sc7280/Makefile.inc: https://review.coreboot.org/c/coreboot/+/55960/comment/d75fd996_d09d0062 PS8, Line 94: GSI_FW_FILE := $(SC7280_BLOB)/qup_fw/gsi_fw.bin : GSI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/gsi_fw : $(GSI_FW_CBFS)-file := $(GSI_FW_FILE) : $(GSI_FW_CBFS)-type := raw : $(GSI_FW_CBFS)-compression := none : cbfs-files-y += $(GSI_FW_CBFS) > I don't see this in 3rdparty/qc_blobs. […] Ack File src/soc/qualcomm/sc7280/Makefile.inc: https://review.coreboot.org/c/coreboot/+/55960/comment/5ac6480e_8d7acfe8 PS15, Line 93: ################################################################################ > Actually, just found this CL (for AOP): https://review.coreboot. […] Ack https://review.coreboot.org/c/coreboot/+/55960/comment/eac2120e_944eb626 PS15, Line 102: CPUCP_FILE := $(SC7280_BLOB)/cpucp/cpucp.elf > And this CL: https://review.coreboot. […] Ack https://review.coreboot.org/c/coreboot/+/55960/comment/2074967f_c1f9ed7f PS15, Line 110: SHRM_FILE := $(SC7280_BLOB)/shrm/shrm.elf > And the appropriate place for loading of shrm.elf seems to be in this CL: https://review.coreboot. […] Ack https://review.coreboot.org/c/coreboot/+/55960/comment/f03f1ce7_5325c260 PS15, Line 93: ################################################################################ : AOP_FILE := $(SC7280_BLOB)/aop/aop.mbn : AOP_CBFS := $(CONFIG_CBFS_PREFIX)/aop : $(AOP_CBFS)-file := $(AOP_FILE) : $(AOP_CBFS)-type := payload : $(AOP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) : cbfs-files-y += $(AOP_CBFS) : : ################################################################################ : CPUCP_FILE := $(SC7280_BLOB)/cpucp/cpucp.elf : CPUCP_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp : $(CPUCP_CBFS)-file := $(CPUCP_FILE) : $(CPUCP_CBFS)-type := payload : $(CPUCP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) : cbfs-files-y += $(CPUCP_CBFS) : : ################################################################################ : SHRM_FILE := $(SC7280_BLOB)/shrm/shrm.elf : SHRM_CBFS := $(CONFIG_CBFS_PREFIX)/shrm : $(SHRM_CBFS)-file := $(SHRM_FILE) : $(SHRM_CBFS)-type := payload : $(SHRM_CBFS)-compression := none : cbfs-files-y += $(SHRM_CBFS) > Please ignore this comment and move the loading of the different blobs to the CLs referenced. Ack File src/soc/qualcomm/sc7280/include/soc/addressmap.h: https://review.coreboot.org/c/coreboot/+/55960/comment/aca54394_2aad98e3 PS15, Line 31: define QUP_SERIAL0_BASE 0x00980000 : #define QUP_SERIAL1_BASE 0x00984000 : #define QUP_SERIAL2_BASE 0x00988000 : #define QUP_SERIAL3_BASE 0x0098C000 : #define QUP_SERIAL4_BASE 0x00990000 : #define QUP_SERIAL5_BASE 0x00994000 : #define QUP_SERIAL6_BASE 0x00998000 : #define QUP_SERIAL7_BASE 0x0099C000 : #define QUP_WRAP0_BASE 0x009C0000 : #define QUP_0_GSI_BASE 0x00904000 : : /* QUPV3_1 */ : #define QUP_SERIAL8_BASE 0x00A80000 : #define QUP_SERIAL9_BASE 0x00A84000 : #define QUP_SERIAL10_BASE 0x00A88000 : #define QUP_SERIAL11_BASE 0x00A8C000 : #define QUP_SERIAL12_BASE 0x00A90000 : #define QUP_SERIAL13_BASE 0x00A94000 : #define QUP_SERIAL14_BASE 0x00A98000 : #define QUP_SERIAL15_BASE 0x00A9C000 : #define QUP_WRAP1_BASE 0x00AC0000 : #define QUP_1_GSI_BASE 0x00A04000 : > Please change these to tabs so we're consistent with the rest of the #defines. Ack https://review.coreboot.org/c/coreboot/+/55960/comment/76b44e0f_ff9ceae7 PS15, Line 31: define QUP_SERIAL0_BASE 0x00980000 : #define QUP_SERIAL1_BASE 0x00984000 : #define QUP_SERIAL2_BASE 0x00988000 : #define QUP_SERIAL3_BASE 0x0098C000 : #define QUP_SERIAL4_BASE 0x00990000 : #define QUP_SERIAL5_BASE 0x00994000 : #define QUP_SERIAL6_BASE 0x00998000 : #define QUP_SERIAL7_BASE 0x0099C000 : #define QUP_WRAP0_BASE 0x009C0000 : #define QUP_0_GSI_BASE 0x00904000 : : /* QUPV3_1 */ : #define QUP_SERIAL8_BASE 0x00A80000 : #define QUP_SERIAL9_BASE 0x00A84000 : #define QUP_SERIAL10_BASE 0x00A88000 : #define QUP_SERIAL11_BASE 0x00A8C000 : #define QUP_SERIAL12_BASE 0x00A90000 : #define QUP_SERIAL13_BASE 0x00A94000 : #define QUP_SERIAL14_BASE 0x00A98000 : #define QUP_SERIAL15_BASE 0x00A9C000 : #define QUP_WRAP1_BASE 0x00AC0000 : #define QUP_1_GSI_BASE 0x00A04000 : > Please change these to tabs so we're consistent with the rest of the #defines. Ack File src/soc/qualcomm/sc7280/qcom_qup_se.c: https://review.coreboot.org/c/coreboot/+/55960/comment/32f5de19_f2ade482 PS15, Line 6: 0 > Can we use the enums that you defined (ie: QUPV3_0_SE0, QUPV3_0_SE1, etc. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/55960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e9049557ff63898037210e72333e1739ab62413 Gerrit-Change-Number: 55960 Gerrit-PatchSet: 17 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 03 Sep 2021 08:02:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/qualcomm: move aop firmware loading changes to common
by Ravi Kumar Bokka (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Shelley Chen, Ravi kumar, Julius Werner. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49767 ) Change subject: soc/qualcomm: move aop firmware loading changes to common ...................................................................... Patch Set 66: (1 comment) File src/soc/qualcomm/common/include/soc/aop_common.h: https://review.coreboot.org/c/coreboot/+/49767/comment/10606307_c6438080 PS64, Line 9: > Looks like these newlines are causing Jenkins to mark this as verfied-1: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/49767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90b0f48e15df390970e027bff2065b7a89b14cec Gerrit-Change-Number: 49767 Gerrit-PatchSet: 66 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 03 Sep 2021 08:02:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit September 2021