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Change subject: arch/x86: Refactor the SMBIOS type 17 write function
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
> Any suggestion on the failure, unable to see any such reason.
got it, its test framework
tests/lib/dimm_info_util-test.c: In function 'test_smbios_form_factor_to_spd_mod_type':
tests/lib/dimm_info_util-test.c:70:3: error: 'SPD_UDIMM' undeclared (first use in this function); did you mean 'DDR5_SPD_UDIMM'?
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Zhi7 Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57358 )
Change subject: mb/google/dedede: Create beetley variant
......................................................................
mb/google/dedede: Create beetley variant
Create the beetley variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:198713668
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BEETLEY
Signed-off-by: Zhi Li <lizhi7(a)huaqin.corp-partner.google.com>
Change-Id: I3d52be55270361406a67f91707b71dff5c725f35
---
M src/mainboard/google/dedede/Kconfig
M src/mainboard/google/dedede/Kconfig.name
A src/mainboard/google/dedede/variants/beetley/include/variant/ec.h
A src/mainboard/google/dedede/variants/beetley/include/variant/gpio.h
A src/mainboard/google/dedede/variants/beetley/memory/Makefile.inc
A src/mainboard/google/dedede/variants/beetley/memory/dram_id.generated.txt
A src/mainboard/google/dedede/variants/beetley/memory/mem_parts_used.txt
A src/mainboard/google/dedede/variants/beetley/overridetree.cb
8 files changed, 82 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/57358/1
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index 980fe70..1de1b5c 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -115,6 +115,7 @@
default "Corori" if BOARD_GOOGLE_CORORI
default "Driblee" if BOARD_GOOGLE_DRIBLEE
default "Gooey" if BOARD_GOOGLE_GOOEY
+ default "Beetley" if BOARD_GOOGLE_BEETLEY
config MAX_CPUS
int
@@ -156,6 +157,7 @@
default "corori" if BOARD_GOOGLE_CORORI
default "driblee" if BOARD_GOOGLE_DRIBLEE
default "gooey" if BOARD_GOOGLE_GOOEY
+ default "beetley" if BOARD_GOOGLE_BEETLEY
endif #BOARD_GOOGLE_BASEBOARD_DEDEDE
diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name
index a55f189..545cd87 100644
--- a/src/mainboard/google/dedede/Kconfig.name
+++ b/src/mainboard/google/dedede/Kconfig.name
@@ -184,3 +184,8 @@
select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2
select BASEBOARD_DEDEDE_LAPTOP
select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
+
+config BOARD_GOOGLE_BEETLEY
+ bool "-> Beetley"
+ select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
+ select BASEBOARD_DEDEDE_LAPTOP
diff --git a/src/mainboard/google/dedede/variants/beetley/include/variant/ec.h b/src/mainboard/google/dedede/variants/beetley/include/variant/ec.h
new file mode 100644
index 0000000..08870e0
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/beetley/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/dedede/variants/beetley/include/variant/gpio.h b/src/mainboard/google/dedede/variants/beetley/include/variant/gpio.h
new file mode 100644
index 0000000..9078664
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/beetley/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/dedede/variants/beetley/memory/Makefile.inc b/src/mainboard/google/dedede/variants/beetley/memory/Makefile.inc
new file mode 100644
index 0000000..b0ca222
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/beetley/memory/Makefile.inc
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+## This is an auto-generated file. Do not edit!!
+## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+
+SPD_SOURCES = placeholder.spd.hex
diff --git a/src/mainboard/google/dedede/variants/beetley/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/beetley/memory/dram_id.generated.txt
new file mode 100644
index 0000000..fa24790
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/beetley/memory/dram_id.generated.txt
@@ -0,0 +1 @@
+DRAM Part Name ID to assign
diff --git a/src/mainboard/google/dedede/variants/beetley/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/beetley/memory/mem_parts_used.txt
new file mode 100644
index 0000000..e4258b5
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/beetley/memory/mem_parts_used.txt
@@ -0,0 +1,11 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.inc and dram_id.generated.txt by running the
+# gen_part_id tool from util/spd_tools/{ddr4,lp4x}.
+# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions.
+
+# Part Name
diff --git a/src/mainboard/google/dedede/variants/beetley/overridetree.cb b/src/mainboard/google/dedede/variants/beetley/overridetree.cb
new file mode 100644
index 0000000..404024b
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/beetley/overridetree.cb
@@ -0,0 +1,42 @@
+chip soc/intel/jasperlake
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| I2C0 | Trackpad |
+ #| I2C1 | Digitizer |
+ #| I2C2 | Touchscreen |
+ #| I2C3 | Camera |
+ #| I2C4 | Audio |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[4] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ }"
+
+ device domain 0 on
+ device pci 15.0 on end
+ end
+end
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Change subject: soc/mediatek: preserve WDT reset reason for debugging
......................................................................
Patch Set 6:
(1 comment)
File src/soc/mediatek/common/wdt.c:
https://review.coreboot.org/c/coreboot/+/57270/comment/1427eaa4_720aa092
PS2, Line 22: write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
> > (This GPIO is not controlled by sw driver.) […]
We trigger secondary reset by triggering WDT hardware to send signal to EC.
We do not use do_board_reset() to send signal to EC which is controlled by software driver.
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57270
to look at the new patch set (#6).
Change subject: soc/mediatek: preserve WDT reset reason for debugging
......................................................................
soc/mediatek: preserve WDT reset reason for debugging
1. Disable external output reset signal in first WDT reset
to preserve WDT original reset reason for WDT issue in kernel stage.
2. After preserved WDT reset reason, do fully reset again by sending
external output reset signal.
BUG=b:194025005
TEST=boot to kernel ok and function test pass
Signed-off-by: Fengquan Chen <fengquan.chen(a)mediatek.corp-partner.google.com>
Change-Id: I5887a8312f4daab3cbd0a30fea0195670a932e52
---
M src/soc/mediatek/common/wdt.c
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/57270/6
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Marx Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57357 )
Change subject: mb/google/brya/variants/gimble: Enable SaGv support
......................................................................
Patch Set 1: Code-Review+1
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Change subject: arch/x86: Refactor the SMBIOS type 17 write function
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
Any suggestion on the failure, unable to see any such reason.
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Change subject: mb/google/brya/variants/gimble: Enable SaGv support
......................................................................
Patch Set 1: Code-Review+1
This change is ready for review.
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Hello build bot (Jenkins), Tim Wawrzynczak, Aseda Aboagye, Sridhar Siricilla, Andrey Petrov, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common/cse: Add argument for CSE fixed client addr
......................................................................
soc/intel/common/cse: Add argument for CSE fixed client addr
There are multiple HECI clients in the CSE. heci_send_receive() is
sending HECI messages to only the MKHI client. Add an argument to
heci_send_receive() function to provide flexibility to the caller to
select the client for which the message is intended.
With the above change heci_send() and heci_receive() functions are
no longer required to be exposed.
In the follow-up patches there will be messages sent to one other
client.
BUG=None
BRANCH=None
TEST=Build and boot brya. HECI message send and receive to MKHI client
is working. Also, MEI BUS message to disable bus is working.
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c
---
M src/soc/intel/apollolake/cse.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/cse/cse_eop.c
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
5 files changed, 38 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/57295/10
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Gerrit-Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c
Gerrit-Change-Number: 57295
Gerrit-PatchSet: 10
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