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Change subject: mb/google/brya/variants/gimble: add GPP_B4 and GPP_D11 to early_gpio_table
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57359/comment/83d34b62_d265fee2
PS2, Line 9: needs extra time to run boot process
How much is the total required time? Did you check the datasheet?
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Change subject: mb/google/brya/variants/gimble: add GPP_B4 and GPP_D11 to early_gpio_table
......................................................................
Patch Set 2: Code-Review+1
This change is ready for review.
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Change subject: soc/mediatek: preserve WDT reset reason for debugging
......................................................................
Patch Set 6:
(2 comments)
File src/soc/mediatek/common/wdt.c:
https://review.coreboot.org/c/coreboot/+/57270/comment/9d267e09_17d59e76
PS2, Line 22: write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
> We trigger secondary reset by triggering WDT hardware to send signal to EC. […]
Ack
File src/soc/mediatek/common/wdt.c:
https://review.coreboot.org/c/coreboot/+/57270/comment/f9bb16d7_2c798c9a
PS6, Line 23: /*
: * We trigger secondary reset by triggering WDT hardware to send signal to EC.
: * We do not use do_board_reset() to send signal to EC
: * which is controlled by software driver.
: */
> enable first(MTK_WDT_MODE_EXTEN) and set reset trigger. […]
Ack
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Change subject: soc/mediatek: preserve WDT reset reason for debugging
......................................................................
Patch Set 6: Code-Review+1
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Change subject: soc/mediatek: preserve WDT reset reason for debugging
......................................................................
Patch Set 6:
(1 comment)
File src/soc/mediatek/common/wdt.c:
https://review.coreboot.org/c/coreboot/+/57270/comment/7c20a961_26ea5847
PS6, Line 23: /*
: * We trigger secondary reset by triggering WDT hardware to send signal to EC.
: * We do not use do_board_reset() to send signal to EC
: * which is controlled by software driver.
: */
> this comment should be only for MTK_WDT_SWRST_KEY right? or to both wdt_mode and wdt_swrst? […]
enable first(MTK_WDT_MODE_EXTEN) and set reset trigger.
So I think these two register are including what we need.
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Change subject: soc/mediatek: preserve WDT reset reason for debugging
......................................................................
Patch Set 6:
(1 comment)
File src/soc/mediatek/common/wdt.c:
https://review.coreboot.org/c/coreboot/+/57270/comment/68ecc6c8_fef6bd3f
PS6, Line 23: /*
: * We trigger secondary reset by triggering WDT hardware to send signal to EC.
: * We do not use do_board_reset() to send signal to EC
: * which is controlled by software driver.
: */
this comment should be only for MTK_WDT_SWRST_KEY right? or to both wdt_mode and wdt_swrst?
If only for MTK_WDT_SWRST_KEY then please move it to before that.
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Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57333 )
Change subject: Rename MMCONF Kconfigs to ECAM_MMCONF
......................................................................
Patch Set 4:
(8 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57333/comment/e0b27b24_12c9b8ac
PS3, Line 10: pci
> nit: […]
Done
https://review.coreboot.org/c/coreboot/+/57333/comment/d1672181_cd6f1053
PS3, Line 11: This can be confusing as
: other platforms, such as ARM, use a different way of mapping the pci
: config space to memory.
> My understanding so far (for QC IIUC) is that there is a single 4K window in MMIO space, and some ot […]
Thanks, Tim. That's probably much better than I can explain it :).
File payloads/external/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/57333/comment/e717aa2a_a6f2a2b6
PS3, Line 149: CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
> This change and the one in payloads/external/tianocore/Makefile. […]
This was not intentional, but what I wanted to do was maintain functionality at this point. As ECAM is the only access method implemented right now, I wanted to stick all existing MMIO functionality under that umbrella. The intention is to create another config for the ARM MMIO access mechanism. We should be able to add support for both if needed in the future.
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/57333/comment/e9ff90ce_92c7e827
PS3, Line 502: NO_ECAM_MMCONF_SUPPORT
> Maybe add some help text to this and the config below explaining what ECAM_MMCONF is? Basically jus […]
Done
https://review.coreboot.org/c/coreboot/+/57333/comment/39fcd6a7_261b0771
PS3, Line 504: default n
> default y if !x86 ?
Done
https://review.coreboot.org/c/coreboot/+/57333/comment/cab25a6e_4bdf345a
PS3, Line 506: ECAM_MMCONF_SUPPORT
> Make this depend on X86?
Done
https://review.coreboot.org/c/coreboot/+/57333/comment/7192a7b4_984cc922
PS3, Line 622: depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT)
> Does this specifically depend on ECAM, or just MMCONF?
No, but all the current MMCONF support only covers ECAM and is only used by x86, so we thought that it would be cleaner to just move everything to under the ECAM config and create a new config for the ARM side of things.
https://review.coreboot.org/c/coreboot/+/57333/comment/e8e61883_53f63b3c
PS3, Line 639: default 16 if ECAM_MMCONF_SUPPORT && ECAM_MMCONF_BUS_NUMBER <= 128
> Same as above.
See response above.
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Hello build bot (Jenkins), Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Stefan Reinauer, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Suresh Bellampalli, Michal Motyl, Morgan Jang, Alexander Couzens, Felix Held, Furquan Shaikh, Angel Pons, Lance Zhao, Jason Glenesk, Damien Zammit, Martin Roth, Lee Leahy, Marshall Dawson, Tim Wawrzynczak, Vanessa Eusebio, Huang Jin,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: Rename MMCONF Kconfigs to ECAM_MMCONF
......................................................................
Rename MMCONF Kconfigs to ECAM_MMCONF
Currently, the MMCONF Kconfigs only use the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space, which applies only to x86 platforms. This can be confusing as
other platforms, such as ARM, use a different way of mapping the PCI
config space to memory. Renaming the following configs to make it
clear that these configs only apply to ECAM:
NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M payloads/external/Makefile.inc
M payloads/external/tianocore/Makefile
M src/acpi/dsdt_top.asl
M src/arch/x86/include/arch/pci_io_cfg.h
M src/device/Kconfig
M src/device/device_util.c
M src/device/pci_ops.c
M src/drivers/intel/fsp1_1/romstage.c
M src/include/device/pci_mmio_cfg.h
M src/lib/Kconfig
M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
M src/mainboard/emulation/qemu-i440fx/Kconfig
M src/mainboard/emulation/qemu-q35/Kconfig
M src/mainboard/emulation/qemu-q35/acpi_tables.c
M src/mainboard/emulation/qemu-q35/bootblock.c
M src/mainboard/emulation/qemu-q35/memmap.c
M src/mainboard/google/butterfly/early_init.c
M src/mainboard/google/link/early_init.c
M src/mainboard/google/parrot/early_init.c
M src/mainboard/google/stout/early_init.c
M src/mainboard/intel/dcp847ske/romstage.c
M src/mainboard/intel/emeraldlake2/early_init.c
M src/mainboard/kontron/ktqm77/early_init.c
M src/mainboard/lenovo/x220/early_init.c
M src/mainboard/roda/rv11/variants/rv11/early_init.c
M src/mainboard/roda/rv11/variants/rw11/early_init.c
M src/mainboard/samsung/lumpy/early_init.c
M src/mainboard/samsung/stumpy/early_init.c
M src/northbridge/amd/agesa/family14/Kconfig
M src/northbridge/amd/agesa/family15tn/Kconfig
M src/northbridge/amd/agesa/family16kb/Kconfig
M src/northbridge/amd/pi/00730F01/Kconfig
M src/northbridge/intel/e7505/Kconfig
M src/northbridge/intel/gm45/Kconfig
M src/northbridge/intel/gm45/acpi.c
M src/northbridge/intel/gm45/acpi/gm45.asl
M src/northbridge/intel/gm45/bootblock.c
M src/northbridge/intel/haswell/Kconfig
M src/northbridge/intel/haswell/acpi.c
M src/northbridge/intel/haswell/acpi/hostbridge.asl
M src/northbridge/intel/haswell/bootblock.c
M src/northbridge/intel/haswell/haswell_mrc/raminit.c
M src/northbridge/intel/i440bx/Kconfig
M src/northbridge/intel/i945/Kconfig
M src/northbridge/intel/i945/acpi.c
M src/northbridge/intel/i945/acpi/i945.asl
M src/northbridge/intel/i945/bootblock.c
M src/northbridge/intel/ironlake/Kconfig
M src/northbridge/intel/ironlake/acpi.c
M src/northbridge/intel/ironlake/acpi/ironlake.asl
M src/northbridge/intel/ironlake/bootblock.c
M src/northbridge/intel/ironlake/ironlake.h
M src/northbridge/intel/pineview/Kconfig
M src/northbridge/intel/pineview/acpi.c
M src/northbridge/intel/pineview/acpi/pineview.asl
M src/northbridge/intel/pineview/bootblock.c
M src/northbridge/intel/sandybridge/Kconfig
M src/northbridge/intel/sandybridge/acpi.c
M src/northbridge/intel/sandybridge/acpi/hostbridge.asl
M src/northbridge/intel/sandybridge/bootblock.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/northbridge/intel/x4x/Kconfig
M src/northbridge/intel/x4x/acpi.c
M src/northbridge/intel/x4x/acpi/x4x.asl
M src/northbridge/intel/x4x/bootblock.c
M src/security/intel/stm/StmPlatformResource.c
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/acpi/pci0.asl
M src/soc/amd/cezanne/fsp_m_params.c
M src/soc/amd/common/block/acpi/tables.c
M src/soc/amd/common/block/pci/amd_pci_mmconf.c
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/acpi/sb_pci0_fch.asl
M src/soc/amd/picasso/fsp_m_params.c
M src/soc/amd/stoneyridge/Kconfig
M src/soc/cavium/cn81xx/Kconfig
M src/soc/example/min86/Kconfig
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/systemagent.c
M src/soc/intel/apollolake/systemagent.c
M src/soc/intel/baytrail/Kconfig
M src/soc/intel/baytrail/acpi.c
M src/soc/intel/baytrail/acpi/southcluster.asl
M src/soc/intel/baytrail/bootblock/bootblock.c
M src/soc/intel/braswell/Kconfig
M src/soc/intel/braswell/acpi.c
M src/soc/intel/braswell/acpi/southcluster.asl
M src/soc/intel/braswell/bootblock/bootblock.c
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/acpi.c
M src/soc/intel/broadwell/bootblock.c
M src/soc/intel/broadwell/pei_data.c
M src/soc/intel/cannonlake/systemagent.c
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/block/systemagent/Kconfig
M src/soc/intel/common/block/systemagent/systemagent_early.c
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/acpi.c
M src/soc/intel/denverton_ns/acpi/northcluster.asl
M src/soc/intel/denverton_ns/bootblock/bootblock.c
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/elkhartlake/systemagent.c
M src/soc/intel/icelake/Kconfig
M src/soc/intel/icelake/systemagent.c
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/jasperlake/systemagent.c
M src/soc/intel/quark/Kconfig
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/systemagent.c
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/systemagent.c
M src/soc/intel/xeon_sp/Kconfig
M src/soc/intel/xeon_sp/uncore.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
M src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h
M src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h
M src/vendorcode/amd/cimx/sb800/OEM.h
120 files changed, 234 insertions(+), 217 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/57333/4
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