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Change subject: soc/mediatek: preserve WDT reset reason for debugging
......................................................................
Patch Set 5:
(1 comment)
File src/soc/mediatek/common/wdt.c:
https://review.coreboot.org/c/coreboot/+/57270/comment/33143935_6f0ace35
PS2, Line 22: write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
> So I think we still remain the modification of this patch instead of using do_board_reset()?
Just want to make sure, so for the 2nd reset, we don't tell EC (GPIO_RESET) to reset, and has to reset from AP?
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Peter Marheine has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/57354 )
Change subject: documentation: add a section on devicetree refs
......................................................................
documentation: add a section on devicetree refs
There is no existing documentation on how `device ref` and aliases work
in the devicetree, and the behavior around devices not being in the same
location is difficult to discern as well as somewhat unexpected.
This should help prevent confusion leading to bugs such as the one fixed
by https://review.coreboot.org/c/coreboot/+/57298
Change-Id: I4b30f7d531cfc3453d6523a76084f1969125b4bf
Signed-off-by: Peter Marheine <pmarheine(a)chromium.org>
---
M Documentation/acpi/devicetree.md
1 file changed, 56 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/57354/2
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Peter Marheine has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57354 )
Change subject: documentation: add a section on devicetree refs
......................................................................
documentation: add a section on devicetree refs
There is no existing documentation on how `device ref` and aliases work
in the devicetree, and the behavior around devices not being in the same
location is difficult to discern as well as somewhat unexpected.
Change-Id: I4b30f7d531cfc3453d6523a76084f1969125b4bf
Signed-off-by: Peter Marheine <pmarheine(a)chromium.org>
---
M Documentation/acpi/devicetree.md
1 file changed, 56 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/57354/1
diff --git a/Documentation/acpi/devicetree.md b/Documentation/acpi/devicetree.md
index c184fa0..738de26 100644
--- a/Documentation/acpi/devicetree.md
+++ b/Documentation/acpi/devicetree.md
@@ -20,6 +20,62 @@
distinction, and may only have a devicetree.cb file. Or you can always just
write the ASL (ACPI Source Language) code yourself.
+### Naming & referencing devices
+
+When declaring a device, it can optionally be given an alias that can be
+referred to elsewhere. This is particularly useful to declare a device in one
+device tree while allowing its configuration to be more easily changed in an
+overlay. For instance, the AMD Picasso SoC definition
+(`soc/amd/picasso/chipset.cb`) declares an IOMMU on a PCI bus that is disabled
+by default:
+
+```
+chip soc/amd/picasso
+ device domain 0 on
+ ...
+ device pci 00.2 alias iommu off end
+ ...
+ end
+end
+```
+
+A device based on this SoC can override the configuration for the IOMMU without
+duplicating addresses, as in
+`mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb`:
+
+```
+chip soc/amd/picasso
+ device domain 0
+ ...
+ device ref iommu on end
+ ...
+ end
+end
+```
+
+In this example the override simply enables the IOMMU, but it could also
+set additional properties (or even add child devices) inside the IOMMU `device`
+block.
+
+---
+
+It is important to note that devices that use `device ref` syntax to override
+previous definitions of a device by alias must be placed at **exactly the same
+location in the device tree** as the original declaration. If not, this will
+actually create another device rather than overriding the properties of the
+existing one. For instance, if the above snippet from `devicetree_trembyle.cb`
+were written as follows:
+
+```
+chip soc/amd/picasso
+ # NOTE: not inside domain 0!
+ device ref iommu on end
+end
+```
+
+Then this would leave the SoC's IOMMU disabled, and instead create a new device
+with no properties as a direct child of the SoC.
+
## Device drivers
Let's take a look at an example entry from
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Change subject: soc/mediatek: preserve WDT reset reason for debugging
......................................................................
Patch Set 5: Code-Review+2
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Change subject: soc/mediatek: preserve WDT reset reason for debugging
......................................................................
Patch Set 5:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57270/comment/24431c52_4fae207e
PS4, Line 10: reserve
> preserve
Done
https://review.coreboot.org/c/coreboot/+/57270/comment/71ed084f_fa0651f9
PS4, Line 11: reserve
> preserved
Done
File src/soc/mediatek/common/wdt.c:
https://review.coreboot.org/c/coreboot/+/57270/comment/420ef4b6_fbe11338
PS2, Line 22: write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
> ah, didn't see that only mt8173 adds that file to the build. […]
So I think we still remain the modification of this patch instead of using do_board_reset()?
File src/soc/mediatek/common/wdt.c:
https://review.coreboot.org/c/coreboot/+/57270/comment/a3c37265_d00bbf65
PS4, Line 23: write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
> add a comment before this: […]
Done
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57270
to look at the new patch set (#5).
Change subject: soc/mediatek: preserve WDT reset reason for debugging
......................................................................
soc/mediatek: preserve WDT reset reason for debugging
1. Disable external output reset signal in first WDT reset
to preserve WDT original reset reason for WDT issue in kernel stage.
2. After preserved WDT reset reason, do fully reset again by sending
external output reset signal.
BUG=b:194025005
TEST=boot to kernel ok and function test pass
Signed-off-by: Fengquan Chen <fengquan.chen(a)mediatek.corp-partner.google.com>
Change-Id: I5887a8312f4daab3cbd0a30fea0195670a932e52
---
M src/soc/mediatek/common/wdt.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/57270/5
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57219 )
Change subject: drivers/intel/fsp/Makefile: error out when FSP files aren't specified
......................................................................
Patch Set 5:
(1 comment)
File src/drivers/intel/fsp2_0/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/57219/comment/85d98327_5f8943aa
PS5, Line 114: $(warning ADD_FSP_BINARIES isn't selected even though this SoC uses the FSP.)
: $(warning The resulting image likely won't boot successfully.)
There are a number of boards that do not select ADD_FSP_BINARIES in coreboot. Not sure if we really want to print out a warning in this case.
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Change subject: mb/google/dedede/var/gooey: Configure I2C times for I2C devices
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Differ to Karthik to Review and approve. LGTM. Thanks.
CR+2 approved.
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Change subject: mb/google/dedede/var/gooey: Add MT53E512M32D1NP-046 as supported mem module
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57310/comment/af5cf66d_49c546d2
PS1, Line 2: stanley.wu
> Please use *Stanley Wu*. […]
Done
https://review.coreboot.org/c/coreboot/+/57310/comment/771540a2_9e1ce543
PS1, Line 7: Generate SPD ID for supported part
> Maybe: […]
Done
https://review.coreboot.org/c/coreboot/+/57310/comment/b7c1e00c_da8f4626
PS1, Line 11: MT53E512M32D1NP-046 WT:B
> 1. What is the difference to MT53E512M32D2NP-046? […]
From Micron AE feedback as below:
1. MT53E512M32D1NP-046 WT:B is 1anm Tech, MT53E512M32D2NP-046 is 1xnm Tech
2. Manufacturer is Micron
https://review.coreboot.org/c/coreboot/+/57310/comment/cccb5e5a_db00d375
PS1, Line 17: Signed-off-by: stanley.wu <stanley1.wu(a)lcfc.corp-partner.google.com>
> Ditto.
Done
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Change subject: mb/google/dedede/var/bugzzy: Configure DDI port A as MIPI DSI
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Ping for review.
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