coreboot-gerrit September 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/guybrush: If not using PCIe WWAN, disable the port
by Martin Roth (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Raul Rangel, Karthik Ramasubramanian, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57316 ) Change subject: mb/google/guybrush: If not using PCIe WWAN, disable the port ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57316/comment/83cc64dd_3b3aeaa8 PS1, Line 10: and not do : the PCIe training. > In the next CL, it is mentioned that PCIE Training is not done at all for the WWAN port whereas here […] PCIE training is no longer being run for the USB WWAN card, I updated the commit message of the next patch to fix that. -- To view, visit https://review.coreboot.org/c/coreboot/+/57316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79c32e4814672c03ee0821786d5be1c77fd1b410 Gerrit-Change-Number: 57316 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Sep 2021 23:38:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Initialize WWAN GPIOs the same for PCI vs USB
by Martin Roth (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Raul Rangel, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Raul Rangel, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57317 to look at the new patch set (#3). Change subject: mb/google/guybrush: Initialize WWAN GPIOs the same for PCI vs USB ...................................................................... mb/google/guybrush: Initialize WWAN GPIOs the same for PCI vs USB Since the PCIE training for the USB WWAN card is no longer being run, we can initialize the GPIOs the same for all WWAN cards. BUG=b:193036827 TEST=Boot and reboot with fibocom FM350-GL & L850GL modules Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Idc9a7cb883fc8dd6bbc6077b8ea99182f17f888b --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/guybrush/gpio.c 2 files changed, 24 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/57317/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/57317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc9a7cb883fc8dd6bbc6077b8ea99182f17f888b Gerrit-Change-Number: 57317 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation: add Intel Broadwell
by Felix Held (Code Review) 03 Sep '21

03 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54744 ) Change subject: Documentation: add Intel Broadwell ...................................................................... Documentation: add Intel Broadwell Change-Id: I0b1c29162a64030b5c100368f2471702e22b8311 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54744 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- A Documentation/soc/intel/broadwell/blobs.md A Documentation/soc/intel/broadwell/index.md M Documentation/soc/intel/index.md 3 files changed, 49 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/Documentation/soc/intel/broadwell/blobs.md b/Documentation/soc/intel/broadwell/blobs.md new file mode 100644 index 0000000..b9f99af --- /dev/null +++ b/Documentation/soc/intel/broadwell/blobs.md @@ -0,0 +1,41 @@ +# Blobs used in Intel Broadwell boards + +All Broadwell boards supported by coreboot require two proprietary blobs. +In a coreboot image of a Broadwell board, the blobs are named `mrc.bin` and +`refcode` in CBFS. + +`mrc.bin` is run in romstage to initialize the memory. It is placed at a fixed +address in CBFS and is loaded at a fixed address in memory. + +`refcode` is run in ramstage to initialize the system agent and the PCH. It is +a relocatable ELF object. + +## Obtaining the blobs + +Both `mrc.bin` and `refcode` can be obtained from a coreboot image of a Broadwell +board, for example a Purism Librem 13 v1 coreboot image from [MrChromebox]. + + cbfstool coreboot_*.rom extract -f broadwell-mrc.bin -n mrc.bin + cbfstool coreboot_*.rom extract -m x86 -f broadwell-refcode.elf -n fallback/refcode + +## SPD Addresses + +The SPD addresses in Broadwell `pei_data` struct are similar to [Haswell]. + +## Intel GbE support + +Unlike Haswell boards, the `pei_data` struct of Broadwell doesn't have `gbe_enable` +field. For boards with an Intel GbE device, a modification of `refcode` is needed, +otherwise `refcode` will disable the Intel GbE device and the OS cannot find it +in the list of PCI devices. + +## Use Broadwell SoC code for Haswell ULT boards + +Haswell ULT boards can use Broadwell SoC code. To use Broadwell code for Haswell ULT +boards, `devicetree.cb` file and `pei_data` code need to be ported to Broadwell, and +build the code with Broadwell `mrc.bin` and `refcode` instead of using Haswell `mrc.bin`. + +Broadwell SoC code doesn't support non-ULT Haswell or non-ULT Broadwell boards. + +[MrChromebox]: https://mrchromebox.tech/ +[Haswell]: ../../../northbridge/intel/haswell/mrc.bin.md diff --git a/Documentation/soc/intel/broadwell/index.md b/Documentation/soc/intel/broadwell/index.md new file mode 100644 index 0000000..11a3ce1 --- /dev/null +++ b/Documentation/soc/intel/broadwell/index.md @@ -0,0 +1,7 @@ +# Intel Broadwell documentation + +This section describes the Intel Broadwell SoC. + +## Proprietary blobs + +- [mrc.bin and refcode](blobs.md) diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md index 71e427e..8da9cac 100644 --- a/Documentation/soc/intel/index.md +++ b/Documentation/soc/intel/index.md @@ -6,6 +6,7 @@ - [Common code development strategy](code_development_model/code_development_model.md) - [FSP](fsp/index.md) +- [Broadwell](broadwell/index.md) - [Ice Lake/9th Gen Core-i series](icelake/index.md) - [MP Initialization](mp_init/mp_init.md) - [Microcode Updates](microcode.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/54744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b1c29162a64030b5c100368f2471702e22b8311 Gerrit-Change-Number: 54744 Gerrit-PatchSet: 7 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: reduce RW_MRC_CACHE size to 64K
by Felix Held (Code Review) 03 Sep '21

03 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56989 ) Change subject: mb/google/brya: reduce RW_MRC_CACHE size to 64K ...................................................................... mb/google/brya: reduce RW_MRC_CACHE size to 64K The RW_MRC_CACHE only needs to be 64K for Brya. BUG=none TEST="emerge-brya coreboot chromeos-bootimage", flash and boot brya0 to kernel. Change-Id: I74365b795e184b92f483ae2bf862791e235c5362 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56989 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/chromeos.fmd 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/chromeos.fmd b/src/mainboard/google/brya/chromeos.fmd index ad62060..c1a4147 100644 --- a/src/mainboard/google/brya/chromeos.fmd +++ b/src/mainboard/google/brya/chromeos.fmd @@ -12,9 +12,9 @@ } RW_LEGACY(CBFS) 2M RW_MISC 1M { - UNIFIED_MRC_CACHE(PRESERVE) 192K { + UNIFIED_MRC_CACHE(PRESERVE) 128K { RECOVERY_MRC_CACHE 64K - RW_MRC_CACHE 128K + RW_MRC_CACHE 64K } RW_ELOG(PRESERVE) 16K RW_SHARED 16K { -- To view, visit https://review.coreboot.org/c/coreboot/+/56989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74365b795e184b92f483ae2bf862791e235c5362 Gerrit-Change-Number: 56989 Gerrit-PatchSet: 3 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/trogdor: Add LCM_ID to SKU_ID
by Bob Moragues (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: zanxi chen, Julius Werner, Bob Moragues. Bob Moragues has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57329 ) Change subject: mb/google/trogdor: Add LCM_ID to SKU_ID ...................................................................... Patch Set 4: Code-Review-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/57329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I018b3f460f9d084d1a3f0dac026f1cd9dde284e2 Gerrit-Change-Number: 57329 Gerrit-PatchSet: 4 Gerrit-Owner: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: Wenli Xu <xuwenli(a)huaqin.corp-partner.google.com> Gerrit-CC: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Bob Moragues <moragues(a)chromium.org> Gerrit-Comment-Date: Thu, 02 Sep 2021 23:29:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: wifi: Add support for new revisions of SAR table entries
by 9elements QA (Code Review) 03 Sep '21

03 Sep '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56750 ) Change subject: wifi: Add support for new revisions of SAR table entries ...................................................................... Patch Set 27: Automatic boot test returned (PASS/FAIL/TOTAL): 12 / 1 / 13 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/75493 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/75492 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/75491 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/75490 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/75489 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/75488 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/75487 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/75486 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/75485 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/75484 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/75483 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/75482 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/75481 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/56750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08c3f321938eba04e8bcff4d87cb215422715bb2 Gerrit-Change-Number: 56750 Gerrit-PatchSet: 27 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie.chen(a)intel.com> Gerrit-CC: Janiex Tu <janiex.tu(a)intel.corp-partner.google.com> Gerrit-CC: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Comment-Date: Thu, 02 Sep 2021 23:15:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/trogdor: Add LCM_ID to SKU_ID
by Philip Chen (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: zanxi chen, Julius Werner, Bob Moragues. Philip Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57329 ) Change subject: mb/google/trogdor: Add LCM_ID to SKU_ID ...................................................................... Patch Set 4: Code-Review-1 (1 comment) Patchset: PS4: We probably don't need extra strapping pins to identify panels. -- To view, visit https://review.coreboot.org/c/coreboot/+/57329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I018b3f460f9d084d1a3f0dac026f1cd9dde284e2 Gerrit-Change-Number: 57329 Gerrit-PatchSet: 4 Gerrit-Owner: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bob Moragues <moragues(a)google.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: Wenli Xu <xuwenli(a)huaqin.corp-partner.google.com> Gerrit-CC: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Bob Moragues <moragues(a)chromium.org> Gerrit-Comment-Date: Thu, 02 Sep 2021 22:57:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: wifi: Add support for DSM methods for intel wifi card
by Tim Wawrzynczak (Code Review) 03 Sep '21

03 Sep '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56751 ) Change subject: wifi: Add support for DSM methods for intel wifi card ...................................................................... wifi: Add support for DSM methods for intel wifi card Add support for DSM methods as per the connectivity document 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:191720858 TEST=Check the generated SSDT tables for DSM methods Change-Id: Ie154edf188531fe6c260274edaa694cf3b3605d3 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56751 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/wifi/generic/acpi.c M src/include/sar.h M src/vendorcode/google/chromeos/sar.c 3 files changed, 164 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 5636abc..e829185 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -23,11 +23,151 @@ */ #define WIFI_ACPI_NAME_MAX_LEN 5 +/* Unique ID for the WIFI _DSM */ +#define ACPI_DSM_OEM_WIFI_UUID "F21202BF-8F78-4DC6-A5B3-1F738E285ADE" + __weak int get_wifi_sar_limits(union wifi_sar_limits *sar_limits) { return -1; } +/* + * Generate ACPI AML code for _DSM method. + * This function takes as input uuid for the device, set of callbacks and + * argument to pass into the callbacks. Callbacks should ensure that Local0 and + * Local1 are left untouched. Use of Local2-Local7 is permitted in callbacks. + */ +void wifi_emit_dsm(struct dsm_profile *dsm); + +/* + * Function 1: Allow PC OEMs to set ETSI 5.8GHz SRD in Passive/Disabled ESTI SRD + * Channels: 149, 153, 157, 161, 165 + * 0 - ETSI 5.8GHz SRD active scan + * 1 - ETSI 5.8GHz SRD passive scan + * 2 - ETSI 5.8GHz SRD disabled + */ +static void wifi_dsm_srd_active_channels(void *args) +{ + struct dsm_profile *dsm_config = (struct dsm_profile *)args; + + acpigen_write_return_integer(dsm_config->disable_active_sdr_channels); +} + +/* + * Function 2 : Supported Indonesia 5.15-5.35 GHz Band + * 0 - Set 5.115-5.35GHz to Disable in Indonesia + * 1 - Set 5.115-5.35GHz to Enable (Passive) in Indonesia + * 2 - Reserved + */ +static void wifi_dsm_indonasia_5Ghz_band_enable(void *args) +{ + struct dsm_profile *dsm_config = (struct dsm_profile *)args; + + acpigen_write_return_integer(dsm_config->support_indonesia_5g_band); +} + +/* + * Function 3: Support Wi-Fi 6 11ax Rev 2 new channels on 6-7 GHz. + * Bit 0: + * 0 - No override; use device settings 0 + * 1 - Force disable all countries that are not defined in the following bits + * + * Bit 1: + * 0 No override; USA 6GHz disable 0 + * 1 6GHz allowed in the USA (enabled only if the device is certified to the USA) + */ +static void wifi_dsm_supported_ultra_high_band(void *args) +{ + struct dsm_profile *dsm_config = (struct dsm_profile *)args; + + acpigen_write_return_integer(dsm_config->support_ultra_high_band); +} + +/* + * Function 4: Regulatory Special Configurations Enablements + */ +static void wifi_dsm_regulatory_configurations(void *args) +{ + struct dsm_profile *dsm_config = (struct dsm_profile *)args; + + acpigen_write_return_integer(dsm_config->regulatory_configurations); +} + +/* + * Function 5: M.2 UART Interface Configuration + */ +static void wifi_dsm_uart_configurations(void *args) +{ + struct dsm_profile *dsm_config = (struct dsm_profile *)args; + + acpigen_write_return_integer(dsm_config->uart_configurations); +} + +/* + * Function 6: Control Enablement 11ax on certificated modules + * Bit 0 - Apply changes to country Ukraine. 11Ax Setting within module certification + * 0 - None. Work with Wi-Fi FW/OTP definitions [Default] + * 1 - Apply changes. + * + * Bit 1 - 11Ax Mode. Effective only if Bit 0 set to 1 + * 0 - Disable 11Ax on country Ukraine [Default] + * 1 - Enable 11Ax on country Ukraine + * + * Bit 2 - Apply changes to country Russia. 11Ax Setting within module certification + * 0 - None. Work with Wi-Fi FW/OTP definitions [Default] + * 1 - Apply changes. + * + * Bit 3 - 11Ax Mode. Effective only if Bit 2 set to 1 + * 0 - Disable 11Ax on country Russia [Default] + * 1 - Enable 11Ax on country Russia + * + * Bit 31:04 - Reserved + * + * Note: Assumed Russia Work with Wi-Fi FW/OTP definitions + */ +static void wifi_dsm_ukrane_russia_11ax_enable(void *args) +{ + struct dsm_profile *dsm_config = (struct dsm_profile *)args; + + acpigen_write_return_integer(dsm_config->enablement_11ax); +} + +/* + * Function 7: Control Enablement UNII-4 over certificate modules + */ +static void wifi_dsm_unii4_control_enable(void *args) +{ + struct dsm_profile *dsm_config = (struct dsm_profile *)args; + + acpigen_write_return_integer(dsm_config->unii_4); +} + +static void (*wifi_dsm_callbacks[])(void *) = { + NULL, /* Function 0 */ + wifi_dsm_srd_active_channels, /* Function 1 */ + wifi_dsm_indonasia_5Ghz_band_enable, /* Function 2 */ + wifi_dsm_supported_ultra_high_band, /* Function 3 */ + wifi_dsm_regulatory_configurations, /* Function 4 */ + wifi_dsm_uart_configurations, /* Function 5 */ + wifi_dsm_ukrane_russia_11ax_enable, /* Function 6 */ + wifi_dsm_unii4_control_enable, /* Function 7 */ +}; + +void wifi_emit_dsm(struct dsm_profile *dsm) +{ + int i; + size_t count = ARRAY_SIZE(wifi_dsm_callbacks); + + if (dsm == NULL) + return; + + for (i = 1; i < count; i++) + if (!(dsm->supported_functions & (1 << i))) + wifi_dsm_callbacks[i] = NULL; + + acpigen_write_dsm(ACPI_DSM_OEM_WIFI_UUID, wifi_dsm_callbacks, count, dsm); +} + static const uint8_t *sar_fetch_set(const struct sar_profile *sar, size_t set_num) { const uint8_t *sar_table = &sar->sar_table[0]; @@ -341,6 +481,7 @@ sar_emit_wgds(sar_limits.wgds); sar_emit_ppag(sar_limits.ppag); sar_emit_wtas(sar_limits.wtas); + wifi_emit_dsm(sar_limits.dsm); free(sar_limits.sar); } diff --git a/src/include/sar.h b/src/include/sar.h index f4ee0c5..5a4f7ae 100644 --- a/src/include/sar.h +++ b/src/include/sar.h @@ -8,7 +8,7 @@ #define MAX_DENYLIST_ENTRY 16 #define MAX_DSAR_SET_COUNT 3 #define MAX_GEO_OFFSET_REVISION 3 -#define MAX_PROFILE_COUNT 4 +#define MAX_PROFILE_COUNT 5 #define MAX_SAR_REVISION 2 #define REVISION_SIZE 1 #define SAR_REV0_CHAINS_COUNT 2 @@ -47,6 +47,17 @@ uint8_t deny_list_entry[MAX_DENYLIST_ENTRY]; } __packed; +struct dsm_profile { + uint32_t supported_functions; + uint32_t disable_active_sdr_channels; + uint32_t support_indonesia_5g_band; + uint32_t support_ultra_high_band; + uint32_t regulatory_configurations; + uint32_t uart_configurations; + uint32_t enablement_11ax; + uint32_t unii_4; +}; + struct sar_header { char marker[SAR_STR_PREFIX_SIZE]; uint8_t version; @@ -60,6 +71,7 @@ struct geo_profile *wgds; struct gain_profile *ppag; struct avg_profile *wtas; + struct dsm_profile *dsm; }; void *profile[MAX_PROFILE_COUNT]; }; diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index 7b84d1a..8959588 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -84,6 +84,14 @@ return sizeof(struct avg_profile); } +static int dsm_table_size(const struct dsm_profile *dsm) +{ + if (dsm == NULL) + return 0; + + return sizeof(struct dsm_profile); +} + static bool valid_legacy_length(size_t bin_len) { if (bin_len == LEGACY_SAR_WGDS_BIN_SIZE) @@ -134,6 +142,7 @@ expected_sar_bin_size += wgds_table_size(sar_limits->wgds); expected_sar_bin_size += gain_table_size(sar_limits->ppag); expected_sar_bin_size += sar_avg_table_size(sar_limits->wtas); + expected_sar_bin_size += dsm_table_size(sar_limits->dsm); if (sar_bin_size != expected_sar_bin_size) { printk(BIOS_ERR, "ERROR: Invalid SAR size, expected: %ld, obtained: %ld\n", @@ -198,6 +207,7 @@ * [WGDS_REVISION,CHAINS_COUNT,SUBBANDS_COUNT<WGDS_DATA>] * [PPAG_REVISION,MODE,CHAINS_COUNT,SUBBANDS_COUNT<PPAG_DATA>] * [WTAS_REVISION, WTAS_DATA] + * [DSM_RETURN_VALUES] * * The configuration data will always have the revision added in the file for each of the * block, based on the revision number and validity, size of the specific block will be -- To view, visit https://review.coreboot.org/c/coreboot/+/56751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie154edf188531fe6c260274edaa694cf3b3605d3 Gerrit-Change-Number: 56751 Gerrit-PatchSet: 22 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie.chen(a)intel.com> Gerrit-CC: Janiex Tu <janiex.tu(a)intel.corp-partner.google.com> Gerrit-CC: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sherry An <sherry.an(a)intel.com> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: wifi: Add support for wifi time average SAR config
by Tim Wawrzynczak (Code Review) 03 Sep '21

03 Sep '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57061 ) Change subject: wifi: Add support for wifi time average SAR config ...................................................................... wifi: Add support for wifi time average SAR config Add support for the WTAS ACPI BIOS configuration table as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:193665559 TEST=Generated SAR file with the WTAS related configuration values and verified that the SSDT has the WTAS ACPI table. Change-Id: I42cf3cba7974e6db0e05de30846ef103a15fd584 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57061 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/wifi/generic/acpi.c M src/include/sar.h M src/vendorcode/google/chromeos/sar.c 3 files changed, 78 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index ed5b632..5636abc 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -267,6 +267,58 @@ acpigen_write_package_end(); } +static void sar_emit_wtas(struct avg_profile *wtas) +{ + int i; + size_t package_size; + + if (wtas == NULL) + return; + + /* + * Name (WTAS, Package() { + * { + * Revision, + * Package() + * { + * DomainType, // 0x7:WiFi + * WifiTASSelection, // Enable/Disable the TAS feature + * WifiTASListEntries, // No. of blocked countries not approved by OEM to + * BlockedListEntry1, support this feature + * BlockedListEntry2, + * BlockedListEntry3, + * BlockedListEntry4, + * BlockedListEntry5, + * BlockedListEntry6, + * BlockedListEntry7, + * BlockedListEntry8, + * BlockedListEntry9, + * BlockedListEntry10, + * BlockedListEntry11, + * BlockedListEntry12, + * BlockedListEntry13, + * BlockedListEntry14, + * BlockedListEntry15, + * BlockedListEntry16, + * } + * }) + */ + package_size = 1 + 1 + 1 + MAX_DENYLIST_ENTRY; + + acpigen_write_name("WTAS"); + acpigen_write_package(2); + acpigen_write_dword(wtas->revision); + acpigen_write_package(package_size); + acpigen_write_dword(DOMAIN_TYPE_WIFI); + acpigen_write_dword(wtas->tas_selection); + acpigen_write_dword(wtas->tas_list_size); + for (i = 0; i < MAX_DENYLIST_ENTRY; i++) + acpigen_write_byte(wtas->deny_list_entry[i]); + + acpigen_write_package_end(); + acpigen_write_package_end(); +} + static void emit_sar_acpi_structures(const struct device *dev) { union wifi_sar_limits sar_limits; @@ -288,6 +340,7 @@ sar_emit_ewrd(sar_limits.sar); sar_emit_wgds(sar_limits.wgds); sar_emit_ppag(sar_limits.ppag); + sar_emit_wtas(sar_limits.wtas); free(sar_limits.sar); } diff --git a/src/include/sar.h b/src/include/sar.h index e8a1b28..f4ee0c5 100644 --- a/src/include/sar.h +++ b/src/include/sar.h @@ -5,9 +5,10 @@ #include <stdint.h> #define MAX_ANT_GAINS_REVISION 2 +#define MAX_DENYLIST_ENTRY 16 #define MAX_DSAR_SET_COUNT 3 #define MAX_GEO_OFFSET_REVISION 3 -#define MAX_PROFILE_COUNT 3 +#define MAX_PROFILE_COUNT 4 #define MAX_SAR_REVISION 2 #define REVISION_SIZE 1 #define SAR_REV0_CHAINS_COUNT 2 @@ -39,6 +40,13 @@ uint8_t ppag_table[0]; } __packed; +struct avg_profile { + uint8_t revision; + uint8_t tas_selection; + uint8_t tas_list_size; + uint8_t deny_list_entry[MAX_DENYLIST_ENTRY]; +} __packed; + struct sar_header { char marker[SAR_STR_PREFIX_SIZE]; uint8_t version; @@ -51,6 +59,7 @@ struct sar_profile *sar; struct geo_profile *wgds; struct gain_profile *ppag; + struct avg_profile *wtas; }; void *profile[MAX_PROFILE_COUNT]; }; diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index 5c16f76..7b84d1a 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -76,6 +76,14 @@ return sizeof(struct gain_profile) + (gain->chains_count * gain->bands_count); } +static int sar_avg_table_size(const struct avg_profile *sar_avg) +{ + if (sar_avg == NULL) + return 0; + + return sizeof(struct avg_profile); +} + static bool valid_legacy_length(size_t bin_len) { if (bin_len == LEGACY_SAR_WGDS_BIN_SIZE) @@ -125,6 +133,7 @@ expected_sar_bin_size += sar_table_size(sar_limits->sar); expected_sar_bin_size += wgds_table_size(sar_limits->wgds); expected_sar_bin_size += gain_table_size(sar_limits->ppag); + expected_sar_bin_size += sar_avg_table_size(sar_limits->wtas); if (sar_bin_size != expected_sar_bin_size) { printk(BIOS_ERR, "ERROR: Invalid SAR size, expected: %ld, obtained: %ld\n", @@ -188,6 +197,7 @@ * [SAR_REVISION,DSAR_SET_COUNT,CHAINS_COUNT,SUBBANDS_COUNT <WRDD>[EWRD]] * [WGDS_REVISION,CHAINS_COUNT,SUBBANDS_COUNT<WGDS_DATA>] * [PPAG_REVISION,MODE,CHAINS_COUNT,SUBBANDS_COUNT<PPAG_DATA>] + * [WTAS_REVISION, WTAS_DATA] * * The configuration data will always have the revision added in the file for each of the * block, based on the revision number and validity, size of the specific block will be @@ -222,6 +232,11 @@ * [Antenna gain used for 6525-6705MHz frequency] * [Antenna gain used for 6705-6865MHz frequency] * [Antenna gain used for 6865-7105MHz frequency] + * + * [WTAS_DATA] = + * [Enable/disable the TAS feature] + * [Number of blocked countries that are not approved by the OEM to support this feature] + * [deny_list_entry_<1-16>: ISO country code to block] */ int get_wifi_sar_limits(union wifi_sar_limits *sar_limits) { -- To view, visit https://review.coreboot.org/c/coreboot/+/57061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42cf3cba7974e6db0e05de30846ef103a15fd584 Gerrit-Change-Number: 57061 Gerrit-PatchSet: 10 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: wifi: Add support for per-platform antenna gain
by Tim Wawrzynczak (Code Review) 03 Sep '21

03 Sep '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57060 ) Change subject: wifi: Add support for per-platform antenna gain ...................................................................... wifi: Add support for per-platform antenna gain Add support for the PPAG ACPI BIOS configuration table as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:193665559 TEST=Generated SAR file with the PPAG related configuration values and verified that the SSDT has the PPAG ACPI table. Change-Id: Ie8d25113feeeb4a4242cfd7d72a5091d2d5fb389 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57060 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/wifi/generic/acpi.c M src/include/sar.h M src/vendorcode/google/chromeos/sar.c 3 files changed, 90 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index aa49be3..ed5b632 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -42,6 +42,13 @@ return wgds_table + (wgds->bands_count * set_num); } +static const uint8_t *ppag_fetch_set(struct gain_profile *ppag, size_t set_num) +{ + const uint8_t *ppag_table = &ppag->ppag_table[0]; + + return ppag_table + (ppag->bands_count * set_num); +} + static void sar_emit_wrds(const struct sar_profile *sar) { int i; @@ -216,6 +223,50 @@ acpigen_write_package_end(); } +static void sar_emit_ppag(struct gain_profile *ppag) +{ + int i; + size_t package_size, set_num; + const uint8_t *set; + + if (ppag == NULL) + return; + + /* + * Name ("PPAG", Package () { + * Revision, + * Package () { + * Domain Type, // 0x7:WiFi + * PPAG Mode, // Defines the mode of ANT_gain control to be used + * ANT_gain Table Chain A // Defines the ANT_gain in dBi for chain A + * ANT_gain Table Chain B // Defines the ANT_gain in dBi for chain B + * } + * }) + */ + if (ppag->revision > MAX_ANT_GAINS_REVISION) { + printk(BIOS_ERR, "Invalid PPAG revision: %d\n", ppag->revision); + return; + } + + package_size = 1 + 1 + ppag->chains_count * ppag->bands_count; + + acpigen_write_name("PPAG"); + acpigen_write_package(2); + acpigen_write_dword(ppag->revision); + acpigen_write_package(package_size); + acpigen_write_dword(DOMAIN_TYPE_WIFI); + acpigen_write_dword(ppag->mode); + + for (set_num = 0; set_num < ppag->chains_count; set_num++) { + set = ppag_fetch_set(ppag, set_num); + for (i = 0; i < ppag->bands_count; i++) + acpigen_write_byte(set[i]); + } + + acpigen_write_package_end(); + acpigen_write_package_end(); +} + static void emit_sar_acpi_structures(const struct device *dev) { union wifi_sar_limits sar_limits; @@ -236,6 +287,7 @@ sar_emit_wrds(sar_limits.sar); sar_emit_ewrd(sar_limits.sar); sar_emit_wgds(sar_limits.wgds); + sar_emit_ppag(sar_limits.ppag); free(sar_limits.sar); } diff --git a/src/include/sar.h b/src/include/sar.h index 625fd51..e8a1b28 100644 --- a/src/include/sar.h +++ b/src/include/sar.h @@ -4,9 +4,10 @@ #include <stdint.h> +#define MAX_ANT_GAINS_REVISION 2 #define MAX_DSAR_SET_COUNT 3 #define MAX_GEO_OFFSET_REVISION 3 -#define MAX_PROFILE_COUNT 2 +#define MAX_PROFILE_COUNT 3 #define MAX_SAR_REVISION 2 #define REVISION_SIZE 1 #define SAR_REV0_CHAINS_COUNT 2 @@ -30,6 +31,14 @@ uint8_t sar_table[0]; } __packed; +struct gain_profile { + uint8_t revision; + uint8_t mode; + uint8_t chains_count; + uint8_t bands_count; + uint8_t ppag_table[0]; +} __packed; + struct sar_header { char marker[SAR_STR_PREFIX_SIZE]; uint8_t version; @@ -41,6 +50,7 @@ struct { struct sar_profile *sar; struct geo_profile *wgds; + struct gain_profile *ppag; }; void *profile[MAX_PROFILE_COUNT]; }; diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index d6cb021..5c16f76 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -68,6 +68,14 @@ return sizeof(struct geo_profile) + (geo->chains_count * geo->bands_count); } +static int gain_table_size(const struct gain_profile *gain) +{ + if (gain == NULL) + return 0; + + return sizeof(struct gain_profile) + (gain->chains_count * gain->bands_count); +} + static bool valid_legacy_length(size_t bin_len) { if (bin_len == LEGACY_SAR_WGDS_BIN_SIZE) @@ -116,6 +124,7 @@ expected_sar_bin_size = header_size; expected_sar_bin_size += sar_table_size(sar_limits->sar); expected_sar_bin_size += wgds_table_size(sar_limits->wgds); + expected_sar_bin_size += gain_table_size(sar_limits->ppag); if (sar_bin_size != expected_sar_bin_size) { printk(BIOS_ERR, "ERROR: Invalid SAR size, expected: %ld, obtained: %ld\n", @@ -178,6 +187,7 @@ * Offsets * [SAR_REVISION,DSAR_SET_COUNT,CHAINS_COUNT,SUBBANDS_COUNT <WRDD>[EWRD]] * [WGDS_REVISION,CHAINS_COUNT,SUBBANDS_COUNT<WGDS_DATA>] + * [PPAG_REVISION,MODE,CHAINS_COUNT,SUBBANDS_COUNT<PPAG_DATA>] * * The configuration data will always have the revision added in the file for each of the * block, based on the revision number and validity, size of the specific block will be @@ -195,6 +205,23 @@ * [GROUP#0] is for FCC * [GROUP#1] is for Europe/Japan * [GROUP#2] is for ROW + * + * [PPAG_DATA] = [ANT_gain Table Chain A] [ANT_gain Table Chain A] + * + * [ANT_gain Table] = + * Supported by Revision 0, 1 and 2 + * [Antenna gain used for 2400MHz frequency] + * [Antenna gain used for 5150-5350MHz frequency] + * [Antenna gain used for 5350-5470MHz frequency] + * [Antenna gain used for 5470-5725MHz frequency] + * [Antenna gain used for 5725-5945MHz frequency] + * Supported by Revision 1 and 2 + * [Antenna gain used for 5945-6165MHz frequency] + * [Antenna gain used for 6165-6405MHz frequency] + * [Antenna gain used for 6405-6525MHz frequency] + * [Antenna gain used for 6525-6705MHz frequency] + * [Antenna gain used for 6705-6865MHz frequency] + * [Antenna gain used for 6865-7105MHz frequency] */ int get_wifi_sar_limits(union wifi_sar_limits *sar_limits) { -- To view, visit https://review.coreboot.org/c/coreboot/+/57060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8d25113feeeb4a4242cfd7d72a5091d2d5fb389 Gerrit-Change-Number: 57060 Gerrit-PatchSet: 9 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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