coreboot-gerrit September 2021

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Change in coreboot[master]: configs/config.google_meep_cros: don't select ADD_FSP_BINARIES
by Felix Held (Code Review) 02 Sep '21

02 Sep '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57351 ) Change subject: configs/config.google_meep_cros: don't select ADD_FSP_BINARIES ...................................................................... configs/config.google_meep_cros: don't select ADD_FSP_BINARIES This config selected ADD_FSP_BINARIES even though HAVE_INTEL_FSP_REPO is only defined for Apollolake and not Geminilake that resides in the same SoC directory and uses the same Kconfig file. This results in the paths to the FSP binaries not being defined, in which case the ADD_FSP_BINARIES option shouldn't be selected. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I95123c4930b44a3b76c87768e130eb7359bbf625 --- M configs/config.google_meep_cros 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/57351/1 diff --git a/configs/config.google_meep_cros b/configs/config.google_meep_cros index 9911614..acb0e4c 100644 --- a/configs/config.google_meep_cros +++ b/configs/config.google_meep_cros @@ -22,7 +22,6 @@ CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144 # Firmware Support Package -CONFIG_ADD_FSP_BINARIES=y # CONFIG_RUN_FSP_GOP is not set # Management Engine -- To view, visit https://review.coreboot.org/c/coreboot/+/57351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95123c4930b44a3b76c87768e130eb7359bbf625 Gerrit-Change-Number: 57351 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp/Makefile: error out when FSP files aren't specified
by Felix Held (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Andrey Petrov, Patrick Rudolph, Felix Held. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57219 to look at the new patch set (#5). Change subject: drivers/intel/fsp/Makefile: error out when FSP files aren't specified ...................................................................... drivers/intel/fsp/Makefile: error out when FSP files aren't specified Error out when the FSP binaries that are supposed to be added aren't specified. Also print a warning that the resulting image likely won't boot successfully if the SoC used the corresponding FSP for the hardware initialization, but ADD_FSP_BINARIES isn't selected, so no FSP binaries will be added to the image. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Nico Huber <nico.h(a)gmx.de> Change-Id: Ie5f2d75d066f0b4e491e9c8420b7a0cbd4ba9e28 --- M src/drivers/intel/fsp2_0/Makefile.inc 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/57219/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/57219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5f2d75d066f0b4e491e9c8420b7a0cbd4ba9e28 Gerrit-Change-Number: 57219 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/device/Kconfig: introduce the AMD_DGPU_WITHOUT_EEPROM symbols
by Name of user not set (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Mike Banon. awokd(a)danwin1210.me has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57319 ) Change subject: src/device/Kconfig: introduce the AMD_DGPU_WITHOUT_EEPROM symbols ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Are there any cases where MAINBOARD_HAS_AMD_DGPU_WITHOUT_EEPROM != AMD_DGPU_WITHOUT_EEPROM ? If not, could it be simplified to only MAINBOARD_HAS_AMD_DGPU_WITHOUT_EEPROM ? -- To view, visit https://review.coreboot.org/c/coreboot/+/57319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I424f93961c9d4a856dd6f5285417597cb117084d Gerrit-Change-Number: 57319 Gerrit-PatchSet: 2 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: awokd(a)danwin1210.me Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Sep 2021 21:15:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Add type-c port info to coreboot table
by Nick Vaccaro (Code Review) 02 Sep '21

02 Sep '21

Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57299 to look at the new patch set (#10). Change subject: mb/google/volteer: Add type-c port info to coreboot table ...................................................................... mb/google/volteer: Add type-c port info to coreboot table This change adds type-c port information for USB type-c ports to the coreboot table. This allows depthcharge to know the usb2 and usb3 port number assignments for each available port, as well as the SBU and data line orientation for the board. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c Passing conn0 type-c info to payload: usb2:9 usb3:1 sbu:0 data:0 Passing conn1 type-c info to payload: usb2:4 usb3:2 sbu:1 data:0 Change-Id: Id5686e5b3dfc6f12aa3f8938f371c14d0b2e490d Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/mainboard.c 1 file changed, 34 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/57299/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/57299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5686e5b3dfc6f12aa3f8938f371c14d0b2e490d Gerrit-Change-Number: 57299 Gerrit-PatchSet: 10 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: coreboot tables: Add type-c port info to coreboot table
by Nick Vaccaro (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Zhuohao Lee, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57069 to look at the new patch set (#16). Change subject: coreboot tables: Add type-c port info to coreboot table ...................................................................... coreboot tables: Add type-c port info to coreboot table This change adds type-c port information for USB Type-C ports to the coreboot table. This allows depthcharge to know the usb2 and usb3 port number assignments for each available port, as well as the SBU and data line orientation for the board. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds successfully. Cherry-pick CL to enable this feature for volteer, flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c Passing conn0 type-c info to payload: usb2:9 usb3:1 sbu:0 data:0 Passing conn1 type-c info to payload: usb2:4 usb3:2 sbu:1 data:0 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/coreboot_tables.h M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c 6 files changed, 138 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/57069/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/57069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Gerrit-Change-Number: 57069 Gerrit-PatchSet: 16 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: utils/abuild: select FSP_USE_REPO instead of ADD_FSP_BINARIES
by Felix Held (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Martin Roth. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57349 to look at the new patch set (#2). Change subject: utils/abuild: select FSP_USE_REPO instead of ADD_FSP_BINARIES ...................................................................... utils/abuild: select FSP_USE_REPO instead of ADD_FSP_BINARIES Like USE_AMD_BLOBS and USE_QC_BLOBS in the case of the AMD and Qualcomm repos, FSP_USE_REPO controls if the Intel FSP repo will get checked out and will be available during the Jenkins runs. ADD_FSP_BINARIES will get selected in drivers/intel/fsp2_0/Kconfig when FSP_USE_REPO is selected. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I72faa6f9e5f2b06ab7cd43595ae0b49bf4d39630 --- M util/abuild/abuild 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/57349/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72faa6f9e5f2b06ab7cd43595ae0b49bf4d39630 Gerrit-Change-Number: 57349 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/leafhill,minnow3: remove FSP_M_CBFS and FSP_S_CBFS override
by Felix Held (Code Review) 02 Sep '21

02 Sep '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57350 ) Change subject: mb/intel/leafhill,minnow3: remove FSP_M_CBFS and FSP_S_CBFS override ...................................................................... mb/intel/leafhill,minnow3: remove FSP_M_CBFS and FSP_S_CBFS override The overrides set the options to the same value as drivers/intel/fsp2_0/ Kconfig does, so drop the overrides. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I53922786382a2e7d29b3df560a1998f41e1d2ea8 --- M src/mainboard/intel/leafhill/Kconfig M src/mainboard/intel/minnow3/Kconfig 2 files changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/57350/1 diff --git a/src/mainboard/intel/leafhill/Kconfig b/src/mainboard/intel/leafhill/Kconfig index bf59d00..8e81a2e 100644 --- a/src/mainboard/intel/leafhill/Kconfig +++ b/src/mainboard/intel/leafhill/Kconfig @@ -44,12 +44,4 @@ depends on NEED_IFWI default y -config FSP_S_CBFS - string - default "fsps.bin" - -config FSP_M_CBFS - string - default "fspm.bin" - endif # BOARD_INTEL_LEAFHILL diff --git a/src/mainboard/intel/minnow3/Kconfig b/src/mainboard/intel/minnow3/Kconfig index 13a8591..018281f 100644 --- a/src/mainboard/intel/minnow3/Kconfig +++ b/src/mainboard/intel/minnow3/Kconfig @@ -44,12 +44,4 @@ depends on NEED_IFWI default y -config FSP_S_CBFS - string - default "fsps.bin" - -config FSP_M_CBFS - string - default "fspm.bin" - endif # BOARD_INTEL_MINNOW3 -- To view, visit https://review.coreboot.org/c/coreboot/+/57350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53922786382a2e7d29b3df560a1998f41e1d2ea8 Gerrit-Change-Number: 57350 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/bugzzy: Adjust framebuffer orientation
by Karthik Ramasubramanian (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: shkim, SH Kim. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57328 ) Change subject: mb/google/dedede/var/bugzzy: Adjust framebuffer orientation ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/dedede/Kconfig: https://review.coreboot.org/c/coreboot/+/57328/comment/0773bd9f_eb0d2a7a PS1, Line 84: BOARD_GOOGLE_SASUKE Isn't it for Buggzy? -- To view, visit https://review.coreboot.org/c/coreboot/+/57328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3477255bab4d99bad5948fd5a4828aa61d8cfa0 Gerrit-Change-Number: 57328 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: shkim <sh_.kim(a)samsung.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 Sep 2021 20:29:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Refactor the SMBIOS type 17 write function
by Subrata Banik (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, Felix Held. Hello Jason Glenesk, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Marshall Dawson, Paul Menzel, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56628 to look at the new patch set (#9). Change subject: arch/x86: Refactor the SMBIOS type 17 write function ...................................................................... arch/x86: Refactor the SMBIOS type 17 write function List of changes: 1. Create Module Type macros as per Memory Type (i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation issue due to renaming of existing macros due to scoping the Memory Type. 2. Skip fixed module type to form factor conversion using DDR2 SPD4 specification (inside dimm_info_fill()). 3. Use dedicated Memory Type and Module type for `Form Factor` conversion using `get_spd_info()` function. 4. Use dedicated Memory Type and Module type for `TypeDetail` conversion using `get_spd_info()` function. 5. Create a new API (convert_form_factor_to_module_type()) for `Form Factor` to 'Module type' conversion as per `Memory Type`. 6. Add DDR5 and LPDDR5 memory technology into the SMBIOS Memory Type table. 7. Add new argument as `Memory Type` smbios_form_factor_to_spd_mod_type(). 8. smbios_form_factor_to_spd_mod_type() internally calls convert_form_factor_to_module_type() for `Module Type` conversion. Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx. BUG=b:194659789 TEST=Refer to dmidecode -t 17 output as below: Without this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Unknown .... With this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Row Of Chips .... Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/smbios.c M src/device/dram/ddr3.c M src/device/dram/ddr4.c M src/device/dram/spd.c M src/include/device/dram/spd.h M src/include/dimm_info_util.h M src/include/smbios.h M src/include/spd.h M src/lib/dimm_info_util.c M src/soc/amd/common/block/pi/amd_late_init.c M src/soc/amd/common/fsp/dmi.c M src/soc/intel/common/smbios.c 12 files changed, 324 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/56628/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/56628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Gerrit-Change-Number: 56628 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Refactor the SMBIOS type 17 write function
by Subrata Banik (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, Felix Held. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56628 ) Change subject: arch/x86: Refactor the SMBIOS type 17 write function ...................................................................... Patch Set 8: (1 comment) File src/include/spd.h: https://review.coreboot.org/c/coreboot/+/56628/comment/29e65f4b_e402994d PS3, Line 209: #define SPD_MEM_DOWN 0x0e > @angel, can I mark this as resolved ? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/56628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Gerrit-Change-Number: 56628 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Sep 2021 20:24:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit September 2021