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Change subject: soc/intel/common/cse: Add argument for CSE fixed client addr
......................................................................
soc/intel/common/cse: Add argument for CSE fixed client addr
There are multiple HECI clients in the CSE. heci_send_receive() is
sending HECI messages to only the MKHI client. Add an argument to
heci_send_receive() funtion to provide flexibility to the caller to
select the client for which the message is intended.
In the follow-up patches there will be messages sent to one other
client.
BUG=None
BRANCH=None
TEST=Build and boot brya. HECI message send and receive to MKHI client
is working. Also, MEI BUS message to disable bus is working.
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c
---
M src/soc/intel/apollolake/cse.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/cse/cse_eop.c
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
5 files changed, 37 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/57295/7
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Change subject: drivers/intel/dptf: Introduce new thermal control mechanism for pch device
......................................................................
Patch Set 5:
(5 comments)
Patchset:
PS5:
Any plans to support GFC0, GFC1, GEMI, SEMI, GFCS, GFCS ?
File src/drivers/intel/dptf/dptf.c:
https://review.coreboot.org/c/coreboot/+/57096/comment/e011ef39_7f95e597
PS5, Line 7: #include <soc/intel/common/block/include/intelblocks/pmc_ipc.h>
`#include <intelblocks/pmc_ipc.h>`
https://review.coreboot.org/c/coreboot/+/57096/comment/2751b7e3_1845009e
PS5, Line 200: int
nit:
`unsigned int`
https://review.coreboot.org/c/coreboot/+/57096/comment/f69c4674_878009d5
PS5, Line 211: acpigen_emit_byte(RETURN_OP);
: acpigen_write_package(0);
: acpigen_write_package_end();
Why does this return a value? I don't see the kernel driver expecting any return value from these methods.
https://review.coreboot.org/c/coreboot/+/57096/comment/75ec90e7_763ef794
PS5, Line 237: acpigen_pop_len
acpigen_write_device_end()
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57096
to look at the new patch set (#5).
Change subject: drivers/intel/dptf: Introduce new thermal control mechanism for pch device
......................................................................
drivers/intel/dptf: Introduce new thermal control mechanism for pch device
Introduce new thermal control mechanism for pch device under dptf.
Change-Id: I035d2844b9ba6a9532ae006fc1c43e34cb94328a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/drivers/intel/dptf/Kconfig
M src/drivers/intel/dptf/dptf.c
M src/drivers/intel/dptf/dptf.h
3 files changed, 57 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/57096/5
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Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50580 )
Change subject: qualcomm/sc7280: Move to use common clock driver for sc7280
......................................................................
Patch Set 62: Code-Review+2
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Change subject: qualcomm/sc7280: Move to use common clock driver for sc7280
......................................................................
Patch Set 62:
(5 comments)
File src/soc/qualcomm/common/clock.c:
https://review.coreboot.org/c/coreboot/+/50580/comment/ddeb1b9e_af4110b0
PS61, Line 239: int
> enum cb_err
Done
File src/soc/qualcomm/common/include/soc/clock_common.h:
https://review.coreboot.org/c/coreboot/+/50580/comment/01244690_8584265f
PS61, Line 157: int
> enum cb_err
Done
File src/soc/qualcomm/sc7280/clock.c:
https://review.coreboot.org/c/coreboot/+/50580/comment/2c2a9e40_c0c09c45
PS61, Line 235: int
> enum cb_err
Done
https://review.coreboot.org/c/coreboot/+/50580/comment/46f1016d_84237950
PS61, Line 352: if (ret < 0)
> if (ret != CB_SUCCESS)
Done
https://review.coreboot.org/c/coreboot/+/50580/comment/2560c599_9cd3bb77
PS61, Line 360: if (ret < 0)
> if (ret != CB_SUCCESS)
Done
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Change subject: coreboot tables: Add type-c port info to coreboot table
......................................................................
Patch Set 12:
(1 comment)
This change is ready for review.
Patchset:
PS11:
> looking pretty nice ! 😊 I would just split out the drivers/intel/pmc_mux changes into a separate CL
Will do.
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Change subject: soc/intel/common/cse: Add argument for CSE fixed client addr
......................................................................
Patch Set 6:
(2 comments)
File src/soc/intel/common/block/cse/cse_eop.c:
https://review.coreboot.org/c/coreboot/+/57295/comment/b613163b_6a6f52ee
PS6, Line 38: if (!heci_send_receive(&msg, sizeof(msg), &reply, &reply_sz, HECI_MEI_ADDR)) {
Similar thing can be done inside APL cse_eop.c. I think that is the last direct use-case of heci_send/heci_receive
With that update, we dont have to export heci_send/heci_receive as public functions. All use-cases can be dealt with using heci_send_receive() function itself.
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/57295/comment/eea5b7db_45510b04
PS6, Line 152: * rcv_msg of size rcv_sz
Nit: Add "from BIOS_HOST_ADDR to cse_addr"
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Hello build bot (Jenkins), Tim Wawrzynczak, Aseda Aboagye, Sridhar Siricilla, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57295
to look at the new patch set (#6).
Change subject: soc/intel/common/cse: Add argument for CSE fixed client addr
......................................................................
soc/intel/common/cse: Add argument for CSE fixed client addr
There are multiple HECI clients in the CSE. heci_send_receive() is
sending HECI messages to only the MKHI client. Add an argument to
heci_send_receive() funtion to provide flexibility to the caller to
select the client for which the message is intended.
In the follow-up patches there will be messages sent to one other
client.
BUG=None
BRANCH=None
TEST=Build and boot brya. HECI message send and receive to MKHI client
is working. Also, MEI BUS message to disable bus is working.
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/cse/cse_eop.c
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
4 files changed, 20 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/57295/6
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