coreboot-gerrit September 2021

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Change in coreboot[master]: mb/google/guybrush: Set eSPI alert as dedicated open drain
by Rob Barnes (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Raul Rangel, Paul Menzel, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57313 ) Change subject: mb/google/guybrush: Set eSPI alert as dedicated open drain ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/57313/comment/67bf09d7_d181e949 PS1, Line 7: nipperkin > mb/google/guybrush/var/nippekin: Done File src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb: https://review.coreboot.org/c/coreboot/+/57313/comment/84c1a1ae_f3fb9596 PS1, Line 37: alert_pin = ESPI_ALERT_PIN_OPEN_DRAIN, > This makes sense. I will update the CL. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b23bfc6a1167aebfde5acd524fda043b63163dc Gerrit-Change-Number: 57313 Gerrit-PatchSet: 2 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 02 Sep 2021 15:50:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Rob Barnes <robbarnes(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Move EC_HOST_EVENT_USB_MUX wake event to S0ix only
by Zhuohao Lee (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57341 ) Change subject: mb/google/volteer: Move EC_HOST_EVENT_USB_MUX wake event to S0ix only ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91e5e0ab8301377817875b6fa9e3c0e1f96c1465 Gerrit-Change-Number: 57341 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 02 Sep 2021 15:48:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Set eSPI alert as dedicated open drain
by Rob Barnes (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Raul Rangel, Karthik Ramasubramanian. Hello build bot (Jenkins), Raul Rangel, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57313 to look at the new patch set (#2). Change subject: mb/google/guybrush: Set eSPI alert as dedicated open drain ...................................................................... mb/google/guybrush: Set eSPI alert as dedicated open drain Guybrush based boards must usa a dedicated eSPI alert#. Must be open drain to prevent power leaks. Keep guybrush reference board in-band since alert# may not be connected. BUG=b:198409370 TEST=Build guybrush and nipperkin, boot guybrush BRANCH=None Change-Id: I4b23bfc6a1167aebfde5acd524fda043b63163dc Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/mainboard/google/guybrush/variants/guybrush/overridetree.cb 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/57313/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b23bfc6a1167aebfde5acd524fda043b63163dc Gerrit-Change-Number: 57313 Gerrit-PatchSet: 2 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp/Makefile: error out when FSP files aren't specified
by Felix Held (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Andrey Petrov, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57219 ) Change subject: drivers/intel/fsp/Makefile: error out when FSP files aren't specified ...................................................................... Patch Set 2: (1 comment) File src/drivers/intel/fsp2_0/Makefile.inc: https://review.coreboot.org/c/coreboot/+/57219/comment/8471f992_baea2dd0 PS1, Line 102: warning > changed this to an error ok, that didn't work. seems that there is some other issue in the kconfig that selects ADD_FSP_BINARIES when it's not supposed to do so; will look into that -- To view, visit https://review.coreboot.org/c/coreboot/+/57219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5f2d75d066f0b4e491e9c8420b7a0cbd4ba9e28 Gerrit-Change-Number: 57219 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 02 Sep 2021 15:41:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially
by Subrata Banik (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Ronak Kanabar, Andrey Petrov, Patrick Rudolph. Hello Ronak Kanabar, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/57343 to review the following change. Change subject: drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially ...................................................................... drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially As per MP service specification, EDK2 is allowed to specify the mode in which a 'func' routine would execute on APs as `SingleThread` sets to 'true' meaning execute the function one by one (serially) or sets to 'false' meaning execute the function simultaneously. MP service API `StartupAllAPs` has designed to pass such options as part of function argument. But another MP service API `StartupAllCPUs` doesn't specifies any such requirement. Running the `func` simultaneously on APs results into coherency issue due to lack of acquire spin lock while accessing common data structure in multiprocessor environment. Change-Id: Ia95d11408f663212fd40daa9fd9b0881a07f1ce7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/57343/1 diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index a795c72..ce66d33 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -92,9 +92,8 @@ /* Run on BSP */ procedure(argument); - /* Run on APs */ - if (mp_run_on_aps((void *)procedure, argument, - MP_RUN_ON_ALL_CPUS, timeout_usec)) { + /* Run on APs Serially */ + if (mp_run_on_all_aps((void *)procedure, argument, timeout_usec, false)) { printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); return FSP_NOT_STARTED; } -- To view, visit https://review.coreboot.org/c/coreboot/+/57343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia95d11408f663212fd40daa9fd9b0881a07f1ce7 Gerrit-Change-Number: 57343 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86: Use MP_RUN_ON_ALL_CPUS macro instead of hardcoding
by Subrata Banik (Code Review) 02 Sep '21

02 Sep '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57342 ) Change subject: cpu/x86: Use MP_RUN_ON_ALL_CPUS macro instead of hardcoding ...................................................................... cpu/x86: Use MP_RUN_ON_ALL_CPUS macro instead of hardcoding This patch ensures mp_run_on_all_aps() is passing 'MP_RUN_ON_ALL_CPUS' macro rather hardcoding `0` while running `func` on all APs. Change-Id: Icd34371c0d4349e1eefe945958eda957c4794707 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/cpu/x86/mp_init.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/57342/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 3eef355..aa037f3 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -997,7 +997,7 @@ int ap_index, bsp_index; if (run_parallel) - return mp_run_on_aps(func, arg, 0, expire_us); + return mp_run_on_aps(func, arg, MP_RUN_ON_ALL_CPUS, expire_us); bsp_index = cpu_index(); -- To view, visit https://review.coreboot.org/c/coreboot/+/57342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd34371c0d4349e1eefe945958eda957c4794707 Gerrit-Change-Number: 57342 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/variants/brask: Enable PCIE port 7 for Ethernet
by Felix Held (Code Review) 02 Sep '21

02 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57273 ) Change subject: mb/google/brya/variants/brask: Enable PCIE port 7 for Ethernet ...................................................................... mb/google/brya/variants/brask: Enable PCIE port 7 for Ethernet Enable PCIE port 7 using clk 6 for RTL8125 Ethernet BUG=b:193750191 BRANCH=None TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ic60a66dbd6ad87cf9c0de85ca7df4d854c371bf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57273 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index d19f627..cc6664c 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -125,6 +125,14 @@ end device ref heci1 on end device ref sata on end + device ref pcie_rp7 on + # Enable PCIE 7 using clk 6 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE7 RTL8125 Ethernet NIC device ref pcie_rp8 on # Enable SD Card PCIE 8 using clk 3 register "pch_pcie_rp[PCH_RP(8)]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/57273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic60a66dbd6ad87cf9c0de85ca7df4d854c371bf5 Gerrit-Change-Number: 57273 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tigerlake: Set MAX_CPUS for TGL-H to 16
by Felix Held (Code Review) 02 Sep '21

02 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57267 ) Change subject: soc/intel/tigerlake: Set MAX_CPUS for TGL-H to 16 ...................................................................... soc/intel/tigerlake: Set MAX_CPUS for TGL-H to 16 TGL-H supports up to 8 cores (16 threads). Change-Id: I2ee1be37f564bf1b6249a6c223be093747c38ab5 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57267 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 3defba4..4ae25f0 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -85,6 +85,7 @@ config MAX_CPUS int + default 16 if SOC_INTEL_TIGERLAKE_PCH_H default 8 config DCACHE_RAM_BASE -- To view, visit https://review.coreboot.org/c/coreboot/+/57267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ee1be37f564bf1b6249a6c223be093747c38ab5 Gerrit-Change-Number: 57267 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/system76/*: cmos.layout: Reserve century byte
by Felix Held (Code Review) 02 Sep '21

02 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57055 ) Change subject: mb/system76/*: cmos.layout: Reserve century byte ...................................................................... mb/system76/*: cmos.layout: Reserve century byte Windows will write to the century byte (0x32), causing the option table checksum to be invalid and reset all options to their default values. Move options and checksum to start after the century byte. Change-Id: Ia395acacda1e251251c880587bbf61d7ee81ba3d Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57055 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- M src/mainboard/system76/gaze15/cmos.layout M src/mainboard/system76/lemp9/cmos.layout M src/mainboard/system76/oryp5/cmos.layout M src/mainboard/system76/oryp6/cmos.layout M src/mainboard/system76/whl-u/cmos.layout 5 files changed, 25 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/src/mainboard/system76/gaze15/cmos.layout b/src/mainboard/system76/gaze15/cmos.layout index c0275d6..ba36b0b 100644 --- a/src/mainboard/system76/gaze15/cmos.layout +++ b/src/mainboard/system76/gaze15/cmos.layout @@ -8,8 +8,11 @@ 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 4 e 6 debug_level +# RTC_CLK_ALTCENTURY +400 8 r 0 century + 409 2 e 7 power_on_after_fail +412 4 h 6 debug_level 984 16 h 0 check_sum enumerations @@ -33,4 +36,4 @@ checksums -checksum 392 983 984 +checksum 408 983 984 diff --git a/src/mainboard/system76/lemp9/cmos.layout b/src/mainboard/system76/lemp9/cmos.layout index c0275d6..ca7c7a4 100644 --- a/src/mainboard/system76/lemp9/cmos.layout +++ b/src/mainboard/system76/lemp9/cmos.layout @@ -8,8 +8,11 @@ 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 4 e 6 debug_level +# RTC_CLK_ALTCENTURY +400 8 r 0 century + 409 2 e 7 power_on_after_fail +412 4 e 6 debug_level 984 16 h 0 check_sum enumerations @@ -33,4 +36,4 @@ checksums -checksum 392 983 984 +checksum 408 983 984 diff --git a/src/mainboard/system76/oryp5/cmos.layout b/src/mainboard/system76/oryp5/cmos.layout index c0275d6..ca7c7a4 100644 --- a/src/mainboard/system76/oryp5/cmos.layout +++ b/src/mainboard/system76/oryp5/cmos.layout @@ -8,8 +8,11 @@ 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 4 e 6 debug_level +# RTC_CLK_ALTCENTURY +400 8 r 0 century + 409 2 e 7 power_on_after_fail +412 4 e 6 debug_level 984 16 h 0 check_sum enumerations @@ -33,4 +36,4 @@ checksums -checksum 392 983 984 +checksum 408 983 984 diff --git a/src/mainboard/system76/oryp6/cmos.layout b/src/mainboard/system76/oryp6/cmos.layout index c0275d6..ca7c7a4 100644 --- a/src/mainboard/system76/oryp6/cmos.layout +++ b/src/mainboard/system76/oryp6/cmos.layout @@ -8,8 +8,11 @@ 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 4 e 6 debug_level +# RTC_CLK_ALTCENTURY +400 8 r 0 century + 409 2 e 7 power_on_after_fail +412 4 e 6 debug_level 984 16 h 0 check_sum enumerations @@ -33,4 +36,4 @@ checksums -checksum 392 983 984 +checksum 408 983 984 diff --git a/src/mainboard/system76/whl-u/cmos.layout b/src/mainboard/system76/whl-u/cmos.layout index c0275d6..ca7c7a4 100644 --- a/src/mainboard/system76/whl-u/cmos.layout +++ b/src/mainboard/system76/whl-u/cmos.layout @@ -8,8 +8,11 @@ 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 4 e 6 debug_level +# RTC_CLK_ALTCENTURY +400 8 r 0 century + 409 2 e 7 power_on_after_fail +412 4 e 6 debug_level 984 16 h 0 check_sum enumerations @@ -33,4 +36,4 @@ checksums -checksum 392 983 984 +checksum 408 983 984 -- To view, visit https://review.coreboot.org/c/coreboot/+/57055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia395acacda1e251251c880587bbf61d7ee81ba3d Gerrit-Change-Number: 57055 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/fsp2_0/Makefile: add condition for FSP-T CBFS file
by Felix Held (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Andrey Petrov, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57220 ) Change subject: drivers/intel/fsp2_0/Makefile: add condition for FSP-T CBFS file ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > LOoks good to me after the [UNTESTED] tag is dropped. done -- To view, visit https://review.coreboot.org/c/coreboot/+/57220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id347336f2751c6d871f31d89c30a1222037c2d69 Gerrit-Change-Number: 57220 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 02 Sep 2021 15:17:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit September 2021