coreboot-gerrit September 2021

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Change in coreboot[master]: ADL: Disable the Devices for test
by Shaik Sameeruddin (Code Review) 02 Sep '21

02 Sep '21

Shaik Sameeruddin has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/57339 ) Change subject: ADL: Disable the Devices for test ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/57339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1613596d3fc3154a58a023809fe7d70976a33f1 Gerrit-Change-Number: 57339 Gerrit-PatchSet: 1 Gerrit-Owner: Shaik Sameeruddin <shaik.sameeruddin(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: ADL: Disable the Devices for test
by Shaik Sameeruddin (Code Review) 02 Sep '21

02 Sep '21

Shaik Sameeruddin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57339 ) Change subject: ADL: Disable the Devices for test ...................................................................... ADL: Disable the Devices for test 1.BT 2.Wifi 3.Camera Signed-off-by: sameeruddin shaik <shaik.sameeruddin(a)intel.com> Change-Id: Id1613596d3fc3154a58a023809fe7d70976a33f1 --- M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb 1 file changed, 5 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/57339/1 diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 25b81eb..4104ad1 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -36,18 +36,18 @@ register "gpio_pm[COMM_5]" = "0" # Enable CNVi BT - register "CnviBtCore" = "true" + # register "CnviBtCore" = "true" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2_C2 - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + # register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + # register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + # register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + # register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" @@ -137,12 +137,6 @@ device ref tcss_dma1 on end device ref xhci on end device ref shared_sram on end - device ref cnvi_wifi on - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device generic 0 on end - end - end device ref i2c3 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" @@ -165,14 +159,6 @@ .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end #PCIE6 WWAN - device ref pcie_rp8 on - # Enable SD Card PCIE 8 using clk 3 - register "pch_pcie_rp[PCH_RP(8)]" = "{ - .clk_src = 3, - .clk_req = 3, - .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, - }" - end #PCIE8 SD card device ref pcie_rp9 on # Enable NVMe PCIE 9 using clk 1 register "pch_pcie_rp[PCH_RP(9)]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/57339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1613596d3fc3154a58a023809fe7d70976a33f1 Gerrit-Change-Number: 57339 Gerrit-PatchSet: 1 Gerrit-Owner: Shaik Sameeruddin <shaik.sameeruddin(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Move WWAN PCIe config to brya0
by Shaik Sameeruddin (Code Review) 02 Sep '21

02 Sep '21

Shaik Sameeruddin has uploaded a new patch set (#2) to the change originally created by Tim Wawrzynczak. ( https://review.coreboot.org/c/coreboot/+/56724 ) Change subject: mb/google/brya: Move WWAN PCIe config to brya0 ...................................................................... mb/google/brya: Move WWAN PCIe config to brya0 So far the PCIe WWAN configuration is specific to brya0, therefore move the configuration to the overridetree. While there, also add a new chip and device in order to add the ExternalFacingPort property to this same root port. BUG=b:190408519 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I53fa12dff25ba970b5d7d7be4bc1f8e52a0ed4ae --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/brya0/overridetree.cb 3 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/56724/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53fa12dff25ba970b5d7d7be4bc1f8e52a0ed4ae Gerrit-Change-Number: 56724 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: tests: Add lib/cbfs-lookup-test test case
by Jakub Czapiga (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Julius Werner, Jan Dabros. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56813 ) Change subject: tests: Add lib/cbfs-lookup-test test case ...................................................................... Patch Set 10: (14 comments) File tests/lib/cbfs-lookup-test.c: https://review.coreboot.org/c/coreboot/+/56813/comment/5395b8bf_425b0964 PS7, Line 120: #if CONFIG(NO_CBFS_MCACHE) > ... […] Yes, we are compiling with -Os, but if you want to debug tests, then compiling it with -O0 is helpful :) https://review.coreboot.org/c/coreboot/+/56813/comment/9ffbc8e3_3f6d158d PS7, Line 439: &s->buf[5] > CBFS area begins with garbage data but eventually there comes a valid, correctly aligned file Done: - test_cbfs_garbage_data_before_aligned_file - test_cbfs_garbage_data_before_unaligned_file https://review.coreboot.org/c/coreboot/+/56813/comment/27fa409c_a5a7f092 PS7, Line 757: setup_test_cbfs_aligned > That's okay but there's still a bunch of duplication. […] I added these macros: - CBFS_LOOKUP_TEST_FAIL_BEYOND_RDEV - CBFS_LOOKUP_ALIGNED_TEST_FAIL_BEYOND_RDEV - CBFS_LOOKUP_UNALIGNED_TEST_FAIL_BEYOND_RDEV File tests/lib/cbfs-lookup-test.c: https://review.coreboot.org/c/coreboot/+/56813/comment/ad0f0a48_50771114 PS9, Line 32: assert > nit: I actually meant a Cmocka assert macro like assert_true(). […] Done https://review.coreboot.org/c/coreboot/+/56813/comment/c4246e56_eeff218c PS9, Line 464: ALIGN_UP(sizeof(test_file_1), CBFS_ALIGNMENT) > second_file_start? Yes. I forgot to replace it https://review.coreboot.org/c/coreboot/+/56813/comment/3a50aa7e_04ee4dde PS9, Line 466: assert > Again would probably be better as assert_true() Done https://review.coreboot.org/c/coreboot/+/56813/comment/1ce15786_65bc818f PS9, Line 526: termminator > nit: typo, and an unmatched parenthesis earlier in the sentence, and anyway why is this comment dupl […] Done https://review.coreboot.org/c/coreboot/+/56813/comment/47731286_ea2c3b1b PS9, Line 551: + strlen(TEST_DATA_1_FILENAME)) + 2; > I am confused what this test is doing? Isn't this valid? You make the filename field strlen() + 2 by […] Yes, this test should succeed. I places `+ 2` outside of cpu_to_be32(), and that (partialy) is why it fails. https://review.coreboot.org/c/coreboot/+/56813/comment/34fb4285_79b9ab33 PS9, Line 552: f->header.len -= 2; > I'm not really sure what this is supposed to do anyway, but please be aware that you're doing math o […] True, I forgot that this field has to be big endian. Fixed :) https://review.coreboot.org/c/coreboot/+/56813/comment/4f2efd4b_741886bf PS9, Line 554: assert > nit: more raw assert()s... […] Done https://review.coreboot.org/c/coreboot/+/56813/comment/e08c07e7_90657393 PS9, Line 627: attribute structure. However, file will be found, because offset is correct. */ Done. Also fixed in test_cbfs_attributes_offset_cut_off_at_len() > BTW, having a few more thorough tests for cbfs_find_attr() in isolation, maybe in another test unit, would also be nice at some point. This is indeed an important part of CBFS. I will take care of this in the near future :) https://review.coreboot.org/c/coreboot/+/56813/comment/f29d5620_425e927c PS9, Line 738: const struct cbfs_test_file test_file = { > nit: this isn't wrong, but it's somewhat confusing why you're suddenly switching from "copy in and m […] Done. Also for other tests. https://review.coreboot.org/c/coreboot/+/56813/comment/0e2ae99f_775ae7ad PS9, Line 840: .init_res = CONFIG(NO_CBFS_MCACHE) ? CB_SUCCESS : CB_CBFS_IO, > Ahhh... hmmm... hrrmmmm... funny. That's not really how I wanted this to work, I think. […] CB:57271 does fix this issue. Thank you :) https://review.coreboot.org/c/coreboot/+/56813/comment/6d4b0c13_ae1cd9c5 PS9, Line 843: CB_CBFS_MOCK_ASSERT_FAILURE > I think(?) as far as I can tell you're only hitting this in the cases where cbfs_mcache_build() returns an error, and then you're trying to use the resulting mcache anyway. That was the case. I was convinced, that it should fail, when cbfs_init_boot_device() fails to build MCache correctly. It's nice, that this bug was revealed. CB:57271 allowed to get rid of CB_CBFS_MOCK_ASSERT_FAILURE. -- To view, visit https://review.coreboot.org/c/coreboot/+/56813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ebebba1468c19661741de8a8456605b1c5f56b6 Gerrit-Change-Number: 56813 Gerrit-PatchSet: 10 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Thu, 02 Sep 2021 10:53:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: tests: Add lib/cbfs-lookup-test test case
by Jakub Czapiga (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Jakub Czapiga, Jan Dabros. Hello build bot (Jenkins), Julius Werner, Jan Dabros, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56813 to look at the new patch set (#10). Change subject: tests: Add lib/cbfs-lookup-test test case ...................................................................... tests: Add lib/cbfs-lookup-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I2ebebba1468c19661741de8a8456605b1c5f56b6 --- M tests/include/tests/lib/cbfs_util.h M tests/lib/Makefile.inc A tests/lib/cbfs-lookup-test.c M tests/mock/cbfs_file_mock.c 4 files changed, 1,135 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/56813/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/56813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ebebba1468c19661741de8a8456605b1c5f56b6 Gerrit-Change-Number: 56813 Gerrit-PatchSet: 10 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Rename MMCONF Kconfigs to ECAM_MMCONF
by Angel Pons (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Stefan Reinauer, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Johnny Lin, Suresh Bellampalli, Morgan Jang, Michal Motyl, Alexander Couzens, Felix Held, Shelley Chen, Furquan Shaikh, Lance Zhao, Jason Glenesk, Martin Roth, Damien Zammit, Lee Leahy, Marshall Dawson, Tim Wawrzynczak, Vanessa Eusebio, Huang Jin. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57333 ) Change subject: Rename MMCONF Kconfigs to ECAM_MMCONF ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/57333/comment/7c1c6b9d_68cf3b80 PS3, Line 11: This can be confusing as : other platforms, such as ARM, use a different way of mapping the pci : config space to memory. Out of curiosity, which mechanism does ARM use? File payloads/external/Makefile.inc: https://review.coreboot.org/c/coreboot/+/57333/comment/bab8cf4f_04c16425 PS3, Line 149: CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \ This change and the one in payloads/external/tianocore/Makefile.inc would prevent using any other MMCONF access methods with tianocore. Is this intentional? File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/57333/comment/78b77fba_c13c52fa PS3, Line 622: depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT) Does this specifically depend on ECAM, or just MMCONF? https://review.coreboot.org/c/coreboot/+/57333/comment/d63562b4_7fe5c033 PS3, Line 639: default 16 if ECAM_MMCONF_SUPPORT && ECAM_MMCONF_BUS_NUMBER <= 128 Same as above. -- To view, visit https://review.coreboot.org/c/coreboot/+/57333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Gerrit-Change-Number: 57333 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Comment-Date: Thu, 02 Sep 2021 10:44:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/gooey: Add MT53E512M32D1NP-046 as supported mem ...
by Stanley Wu (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Henry Sun, Stanley Wu, Paul Fagerburg, Karthik Ramasubramanian. Hello build bot (Jenkins), Henry Sun, Paul Fagerburg, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57310 to look at the new patch set (#2). Change subject: mb/google/dedede/var/gooey: Add MT53E512M32D1NP-046 as supported mem module ...................................................................... mb/google/dedede/var/gooey: Add MT53E512M32D1NP-046 as supported mem module Add supported memory part in the mem_parts_used.txt and generate the SPD ID for the part. The memory part being added is: MT53E512M32D1NP-046 WT:B BUG=b:194223174 BRANCH=dedede TEST=Build the gooey board. Change-Id: I7b83126a2bf98bb9d0ca05d397c288e0d99ed781 Signed-off-by: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/gooey/memory/Makefile.inc M src/mainboard/google/dedede/variants/gooey/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/gooey/memory/mem_list_variant.txt 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/57310/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b83126a2bf98bb9d0ca05d397c288e0d99ed781 Gerrit-Change-Number: 57310 Gerrit-PatchSet: 2 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/ec/google/chromeec: Add and modify APIs for USB-C DP ALT mode
by Derek Huang (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Brandon Breitenstein, Curtis Chen. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57138 ) Change subject: src/ec/google/chromeec: Add and modify APIs for USB-C DP ALT mode ...................................................................... Patch Set 7: (3 comments) File src/ec/google/chromeec/ec.c: https://review.coreboot.org/c/coreboot/+/57138/comment/aa35bbd8_b5889c4c PS5, Line 1513: TYPEC_CONTROL_COMMAND_ENTER_MODE > I assume these (and other undefined symbols) come from `ec_commands.h` ? […] I didn't get it. I didn't add anything in ec_commanfs.h, it looks up-to-date, there is no undefined symbol https://review.coreboot.org/c/coreboot/+/57138/comment/4e3a78d8_01236608 PS5, Line 1567: -1 means check all port > Please change this to a symbolic constant, e,g.: […] Done https://review.coreboot.org/c/coreboot/+/57138/comment/ff23aea9_4119ff30 PS5, Line 1592: >= 0 > `!= EC_ALL_PORTS` done -- To view, visit https://review.coreboot.org/c/coreboot/+/57138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3 Gerrit-Change-Number: 57138 Gerrit-PatchSet: 7 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 Sep 2021 09:41:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/google/chromeec: Add and modify APIs for USB-C DP ALT mode
by Derek Huang (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Furquan Shaikh, Brandon Breitenstein, Curtis Chen. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Zhuohao Lee, Brandon Breitenstein, Curtis Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57138 to look at the new patch set (#7). Change subject: src/ec/google/chromeec: Add and modify APIs for USB-C DP ALT mode ...................................................................... src/ec/google/chromeec: Add and modify APIs for USB-C DP ALT mode Add API to allow AP to send the direction to EC to enter DP ALT mode when EC supports EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY. Modify some APIs to get information for specified port. BUG=b:192947843 Signed-off-by: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3 --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/hatch/variants/baseboard/mainboard.c 4 files changed, 38 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/57138/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/57138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3 Gerrit-Change-Number: 57138 Gerrit-PatchSet: 7 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer: Create APIs for USB-C DP alternate mode support
by Derek Huang (Code Review) 02 Sep '21

02 Sep '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Curtis Chen, Zhuohao Lee, Brandon Breitenstein. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57139 ) Change subject: mb/google/volteer: Create APIs for USB-C DP alternate mode support ...................................................................... Patch Set 10: (1 comment) File src/soc/intel/common/block/tcss/tcss.c: https://review.coreboot.org/c/coreboot/+/57139/comment/a81106a5_dc764856 PS9, Line 296: WAIT_FOR_DISPLAYPORT_TIMEOUT > Yes, we have a draft idea at my 8/26 comment. […] mainboard_tcss_wait_for_displayport() checks if any device is connected on the specified port first, if nothing is connected it returns immediately, it won't wait for DP device and HPD So the worse case is 2 * WAIT_FOR_DISPLAYPORT_TIMEOUT = 2 seconds if port-0 and port-1 are connected to non-DP devices, and port-3 is connected to DP -- To view, visit https://review.coreboot.org/c/coreboot/+/57139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e6dd952d3183ecb76de6d4887ee573ef89bb50 Gerrit-Change-Number: 57139 Gerrit-PatchSet: 10 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Curtis Chen <curtis.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 Sep 2021 09:33:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Curtis Chen <curtis.chen(a)intel.com> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit September 2021