September 2021 - coreboot-gerrit

Change in coreboot[master]: mb/system76/*: cmos.layout: Reserve century byte
by Jeremy Soller (Code Review) Sept. 1, 2021

Sept. 1, 2021

Attention is currently required from: Tim Crawford. Jeremy Soller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57055 ) Change subject: mb/system76/*: cmos.layout: Reserve century byte ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia395acacda1e251251c880587bbf61d7ee81ba3d Gerrit-Change-Number: 57055 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 01:40:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Fix processor hang while plug unplug of TBT device
by Sugnan Prabhu S (Code Review) Sept. 1, 2021

Sept. 1, 2021

Attention is currently required from: Abhijeet Rao, Furquan Shaikh, Sugnan Prabhu S, Paul Menzel, Tim Wawrzynczak, Patrick Rudolph. Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56503 ) Change subject: soc/intel/alderlake: Fix processor hang while plug unplug of TBT device ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: Tim, Furquan, Can we merge this patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/56503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3577df519f64c6f7270dc5537278af76536774e Gerrit-Change-Number: 56503 Gerrit-PatchSet: 7 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.corp-partner.google.com> Gerrit-Attention: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 01 Sep 2021 01:36:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/goog/brya: Add probed fw_configs to SMBIOS OEM strings
by Keith Tzeng (Code Review) Sept. 1, 2021

Sept. 1, 2021

Attention is currently required from: Chen Wisley. Keith Tzeng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57142 ) Change subject: mb/goog/brya: Add probed fw_configs to SMBIOS OEM strings ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: please help review, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/57142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93cd9ef2d1ad963e66c422cff17b083abf731046 Gerrit-Change-Number: 57142 Gerrit-PatchSet: 4 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 01:19:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: driver/i2c/max98390: add dsm_param_name
by Keith Tzeng (Code Review) Sept. 1, 2021

Sept. 1, 2021

Attention is currently required from: Chen Wisley, Tim Wawrzynczak, Paul Menzel. Keith Tzeng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57119 ) Change subject: driver/i2c/max98390: add dsm_param_name ...................................................................... Patch Set 17: (1 comment) Patchset: PS17: Please help review, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/57119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I006572d6a6ea55298374c688dfd9d877835da82d Gerrit-Change-Number: 57119 Gerrit-PatchSet: 17 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 01 Sep 2021 01:18:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Add argument to send message to appropriate fix...
by Rizwan Qureshi (Code Review) Sept. 1, 2021

Sept. 1, 2021

Attention is currently required from: Patrick Rudolph. Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57295 to look at the new patch set (#2). Change subject: soc/intel/common/cse: Add argument to send message to appropriate fixed client ...................................................................... soc/intel/common/cse: Add argument to send message to appropriate fixed client There are multiple HECI clents in the CSE. Currently coreboot is sending HECI messages to only the MKHI client. Add an argument to heci_send_receive() funtion to provide flexibility to the caller to select the client for which the message is intended. In the follow-up patches there will be messages sent to one other client. BUG=None BRANCH=None TEST=Build and boot brya. HECI message send and receive to MKHI client is working. Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_eop.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 4 files changed, 17 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/57295/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c Gerrit-Change-Number: 57295 Gerrit-PatchSet: 2 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/cse: Add argument to send message to appropriate fix...
by Rizwan Qureshi (Code Review) Sept. 1, 2021

Sept. 1, 2021

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57295 ) Change subject: soc/intel/common/cse: Add argument to send message to appropriate fixed client ...................................................................... soc/intel/common/cse: Add argument to send message to appropriate fixed client There are multiple HECI clents in the CSE. Currently coreboot is sending HECI messages to only the MKHI client. Add an argument to heci_send_receive() funtion to provide flexibility to the caller to select the client for which the message is intended for. In the follow-up patches there will be messages sent to one other client. BUG=None BRANCH=None TEST=Build and boot brya. HECI message send and receive to MKHI client is working. Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_eop.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 4 files changed, 17 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/57295/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 7708c1b..f4a1ead 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -533,9 +533,10 @@ return 0; } -int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz) +int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz, + uint8_t client) { - if (!heci_send(snd_msg, snd_sz, BIOS_HOST_ADDR, HECI_MKHI_ADDR)) { + if (!heci_send(snd_msg, snd_sz, BIOS_HOST_ADDR, client)) { printk(BIOS_ERR, "HECI: send Failed\n"); return 0; } @@ -663,7 +664,8 @@ if (rst_type == CSE_RESET_ONLY) status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); else - status = heci_send_receive(&msg, sizeof(msg), &reply, &reply_size); + status = heci_send_receive(&msg, sizeof(msg), &reply, &reply_size, + HECI_MKHI_ADDR); printk(BIOS_DEBUG, "HECI: Global Reset %s!\n", status ? "success" : "failure"); return status; @@ -733,7 +735,7 @@ } if (!heci_send_receive(&msg, sizeof(struct hmrfpo_enable_msg), - &resp, &resp_size)) + &resp, &resp_size, HECI_MKHI_ADDR)) return 0; if (resp.hdr.result) { @@ -782,7 +784,7 @@ } if (!heci_send_receive(&msg, sizeof(struct hmrfpo_get_status_msg), - &resp, &resp_size)) { + &resp, &resp_size, HECI_MKHI_ADDR)) { printk(BIOS_ERR, "HECI: HMRFPO send/receive fail\n"); return -1; } @@ -847,7 +849,8 @@ heci_reset(); - if (!heci_send_receive(&fw_ver_msg, sizeof(fw_ver_msg), &resp, &resp_size)) + if (!heci_send_receive(&fw_ver_msg, sizeof(fw_ver_msg), &resp, &resp_size, + HECI_MKHI_ADDR)) goto fail; if (resp.hdr.result) diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 6e57439..aac8c06 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -112,7 +112,7 @@ printk(BIOS_INFO, "HECI: Sending End-of-Post\n"); - if (!heci_send_receive(&msg, sizeof(msg), &resp, &resp_size)) { + if (!heci_send_receive(&msg, sizeof(msg), &resp, &resp_size, HECI_MKHI_ADDR)) { printk(BIOS_ERR, "HECI: EOP send/receive fail\n"); return CSE_EOP_RESULT_ERROR; } diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 15d585d..762de2a 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -202,7 +202,8 @@ size_t resp_size = sizeof(struct get_bp_info_rsp); - if (!heci_send_receive(&info_req, sizeof(info_req), bp_info_rsp, &resp_size)) { + if (!heci_send_receive(&info_req, sizeof(info_req), bp_info_rsp, &resp_size, + HECI_MKHI_ADDR)) { printk(BIOS_ERR, "cse_lite: Could not get partition info\n"); return false; } @@ -254,7 +255,8 @@ struct mkhi_hdr switch_resp; size_t sw_resp_sz = sizeof(struct mkhi_hdr); - if (!heci_send_receive(&switch_req, sizeof(switch_req), &switch_resp, &sw_resp_sz)) + if (!heci_send_receive(&switch_req, sizeof(switch_req), &switch_resp, &sw_resp_sz, + HECI_MKHI_ADDR)) return false; if (switch_resp.result) { @@ -291,7 +293,7 @@ size_t data_clr_rsp_sz = sizeof(data_clr_rsp); if (!heci_send_receive(&data_clr_rq, sizeof(data_clr_rq), &data_clr_rsp, - &data_clr_rsp_sz)) { + &data_clr_rsp_sz, HECI_MKHI_ADDR)) { return false; } diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 153cb22..ff2d6f2 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -152,7 +152,8 @@ * rcv_msg of size rcv_sz * Returns 0 on failure and 1 on success. */ -int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz); +int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz, + uint8_t client); /* * Attempt device reset. This is useful and perhaps only thing left to do when -- To view, visit https://review.coreboot.org/c/coreboot/+/57295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c Gerrit-Change-Number: 57295 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/agesa/romstage.c: Move timestamp and console init up
by Felix Held (Code Review) Sept. 1, 2021

Sept. 1, 2021

Attention is currently required from: Arthur Heymans, Paul Menzel, Kyösti Mälkki. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55066 ) Change subject: drivers/intel/agesa/romstage.c: Move timestamp and console init up ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55066/comment/cf9ff0a0_d9aa949e PS2, Line 7: intel this should be amd -- To view, visit https://review.coreboot.org/c/coreboot/+/55066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26a37f9384a581a8a750efccc2100a5c6a6f0f85 Gerrit-Change-Number: 55066 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 00:55:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp1_1/romstage.c: Remove MCU update
by Felix Held (Code Review) Sept. 1, 2021

Sept. 1, 2021

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55064 ) Change subject: drivers/intel/fsp1_1/romstage.c: Remove MCU update ...................................................................... drivers/intel/fsp1_1/romstage.c: Remove MCU update On Braswell this is done in the bootblock before C code is executed. Change-Id: I72c7b821e04169ae237d8adb6a8348f06e87b047 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55064 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/romstage.c 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, but someone else must approve Frans Hendriks: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index ff03805..62b112a 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -103,10 +103,6 @@ timestamp_add_now(TS_START_ROMSTAGE); - /* Load microcode before RAM init */ - if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) - intel_update_microcode_from_cbfs(); - /* Display parameters */ if (!CONFIG(NO_MMCONF_SUPPORT)) printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/55064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72c7b821e04169ae237d8adb6a8348f06e87b047 Gerrit-Change-Number: 55064 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common: Change default spi speeds to 33MHz
by Felix Held (Code Review) Sept. 1, 2021

Sept. 1, 2021

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57148 ) Change subject: soc/amd/common: Change default spi speeds to 33MHz ...................................................................... soc/amd/common: Change default spi speeds to 33MHz In CB:56884 we discussed changing the default fast_read speed from 66MHz, which some platforms may not be capable of running, to 33MHz, which should be generally suitable for all platforms. This same change has been applied to the default for all SPI speeds. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Ibf926df6829ffdcbae947aaa245356f219615ce8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57148 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/spi/Kconfig 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig index 8853f6f..eb67597 100644 --- a/src/soc/amd/common/block/spi/Kconfig +++ b/src/soc/amd/common/block/spi/Kconfig @@ -37,7 +37,7 @@ int range 0 5 default 3 if EM100 - default 0 + default 1 help SPI Fast Speed to be programmed by the PSP. 0: 66.66Mhz @@ -77,7 +77,7 @@ int range 0 5 default 3 if EM100 - default 0 + default 1 help SPI ALT Speed to be programmed by coreboot. 0: 66.66Mhz @@ -91,7 +91,7 @@ int range 0 5 default 3 if EM100 - default 0 + default 1 help SPI TPM Speed to be programmed by coreboot. 0: 66.66Mhz -- To view, visit https://review.coreboot.org/c/coreboot/+/57148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf926df6829ffdcbae947aaa245356f219615ce8 Gerrit-Change-Number: 57148 Gerrit-PatchSet: 4 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/system76/*: cmos.layout: Reserve century byte
by Tim Crawford (Code Review) Sept. 1, 2021

Sept. 1, 2021

Attention is currently required from: Jeremy Soller. Hello build bot (Jenkins), Jeremy Soller, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57055 to look at the new patch set (#2). Change subject: mb/system76/*: cmos.layout: Reserve century byte ...................................................................... mb/system76/*: cmos.layout: Reserve century byte Windows will write to the century byte (0x32), causing the option table checksum to be invalid and reset all options to their default values. Move options and checksum to start after the century byte. Change-Id: Ia395acacda1e251251c880587bbf61d7ee81ba3d Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/mainboard/system76/gaze15/cmos.layout M src/mainboard/system76/lemp9/cmos.layout M src/mainboard/system76/oryp5/cmos.layout M src/mainboard/system76/oryp6/cmos.layout M src/mainboard/system76/whl-u/cmos.layout 5 files changed, 25 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/57055/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia395acacda1e251251c880587bbf61d7ee81ba3d Gerrit-Change-Number: 57055 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newpatchset

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