coreboot-gerrit September 2021

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Change in coreboot[master]: coreboot tables: Add type-c port info to coreboot table
by Nick Vaccaro (Code Review) 01 Sep '21

01 Sep '21

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Change in coreboot[master]: mb/google/volteer: Add type-c port info to coreboot table
by Nick Vaccaro (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57299 to look at the new patch set (#2). Change subject: mb/google/volteer: Add type-c port info to coreboot table ...................................................................... mb/google/volteer: Add type-c port info to coreboot table This change adds type-c port information for USB Type-C ports to the coreboot table. This allows depthcharge to know the usb2 and usb3 port number assignments for each available port, as well as the SBU and data line orientation for the board. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c Passing conn0 type-c info to payload: usb2:9 usb3:1 sbu:0 data:0 Passing conn1 type-c info to payload: usb2:4 usb3:2 sbu:1 data:0 Change-Id: Id5686e5b3dfc6f12aa3f8938f371c14d0b2e490d Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/mainboard.c 1 file changed, 35 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/57299/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5686e5b3dfc6f12aa3f8938f371c14d0b2e490d Gerrit-Change-Number: 57299 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/redrix: adjust uid for Maxim amp
by Keith Tzeng (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Chen Wisley, Paul Menzel, Angel Pons. Keith Tzeng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57208 ) Change subject: mb/google/brya/var/redrix: adjust uid for Maxim amp ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: please land this, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/57208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a3183b1e1ecbb109258d6e076551158e0b40ce1 Gerrit-Change-Number: 57208 Gerrit-PatchSet: 3 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 03:46:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot tables: Add type-c port info to coreboot table
by Nick Vaccaro (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Zhuohao Lee, Patrick Rudolph. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57069 ) Change subject: coreboot tables: Add type-c port info to coreboot table ...................................................................... Patch Set 9: (5 comments) File payloads/libpayload/libc/coreboot.c: https://review.coreboot.org/c/coreboot/+/57069/comment/17189068_e7d84543 PS8, Line 255: type_c_entry->port_count > something like `MIN(ARRAY_SIZE(info->type_c_config_info), type_c_entry->port_count)`? Done File src/drivers/intel/pmc_mux/conn/conn.c: PS8: > looks like stale changes Ack File src/mainboard/google/volteer/mainboard.c: https://review.coreboot.org/c/coreboot/+/57069/comment/73906a02_ddbc84d6 PS8, Line 79: pmc = pcidev_path_on_root(PCH_DEVFN_PMC); : if (!pmc || !pmc->link_list->children) { : printk(BIOS_ERR, "%s: unable to find PMC device or its mux\n", __func__); : return 0; : } : : /* : * Add each port underneath PMC.MUX; some variants may not have this defined, : * so it's okay to just silently return here. : */ : mux = pmc->link_list->children; : : while ((child = dev_bus_each_child(mux->link_list, child)) != NULL) { : if (count >= max_ports) : break; > We're now using this logic in several places, maybe there should be a helper function in pmc_mux to […] Sure, I'll change this to add that. https://review.coreboot.org/c/coreboot/+/57069/comment/d1312b76_718a2d18 PS8, Line 95: if (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) : || fw_config_probe(FW_CONFIG(DB_USB, USB3_ACTIVE)) : || fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)) : || fw_config_probe(FW_CONFIG(DB_USB, USB3_NO_A))) > I'd also move this out to the beginning of the function, so if this fails, then the function returns […] Done https://review.coreboot.org/c/coreboot/+/57069/comment/7d00602a_29f1a5c1 PS8, Line 109: return count; > nit: empty line after `}` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Gerrit-Change-Number: 57069 Gerrit-PatchSet: 9 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 01 Sep 2021 03:43:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Add type-c port info to coreboot table
by Nick Vaccaro (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Tim Wawrzynczak. Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57299 ) Change subject: mb/google/volteer: Add type-c port info to coreboot table ...................................................................... mb/google/volteer: Add type-c port info to coreboot table This change adds type-c port information for USB Type-C ports to the coreboot table. This allows depthcharge to know the usb2 and usb3 port number assignments for each available port, as well as the SBU and data line orientation for the board. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c Passing conn0 type-c info to payload: usb2:9 usb3:1 sbu:0 data:0 Passing conn1 type-c info to payload: usb2:4 usb3:2 sbu:1 data:0 Change-Id: Id5686e5b3dfc6f12aa3f8938f371c14d0b2e490d Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/mainboard.c 1 file changed, 36 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/57299/1 diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 7426445..67fc001 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <console/console.h> #include <acpi/acpi.h> #include <baseboard/variants.h> +#include <boot/coreboot_tables.h> +#include <console/console.h> #include <device/device.h> #include <drivers/spi/tpm/tpm.h> #include <ec/ec.h> @@ -35,21 +36,14 @@ * via fw_config + devicetree, i.e., change a register's value depending on fw_config * probing. */ - const struct device *pmc; const struct device *mux; const struct device *conn; - pmc = pcidev_path_on_root(PCH_DEVFN_PMC); - if (!pmc || !pmc->link_list->children) { - printk(BIOS_ERR, "%s: unable to find PMC device or its mux\n", __func__); - return; - } - /* * Find port 1 underneath PMC.MUX; some variants may not have this defined, so it's okay * to just silently return here. */ - mux = pmc->link_list->children; + mux = conn_get_type_c_list(); conn = dev_find_matching_device_on_bus(mux->link_list, is_port1); if (!conn) return; @@ -68,6 +62,39 @@ } } +int sysinfo_fill_type_c_info(struct type_c_config_info *info, uint32_t max_ports) +{ + const struct device *conn = NULL; + uint32_t count = 0; + + /* Return if device doesn't have relevant Type-C ports */ + if (!fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) + && !fw_config_probe(FW_CONFIG(DB_USB, USB3_ACTIVE)) + && !fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)) + && !fw_config_probe(FW_CONFIG(DB_USB, USB3_NO_A))) + return 0; + + conn = conn_get_type_c_list(); + while (conn != NULL) { + struct drivers_intel_pmc_mux_conn_config *config = conn->chip_info; + + if (count >= max_ports) + break; + + if (config) { + info[count].usb2_port_number = config->usb2_port_number; + info[count].usb3_port_number = config->usb3_port_number; + info[count].sbu_orientation = config->sbu_orientation; + info[count].data_orientation = config->hsl_orientation; + count++; + } + + conn = conn->sibling; + } + + return count; +} + static void mainboard_init(struct device *dev) { mainboard_ec_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/57299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5686e5b3dfc6f12aa3f8938f371c14d0b2e490d Gerrit-Change-Number: 57299 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: coreboot tables: Add type-c port info to coreboot table
by Nick Vaccaro (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Paul Menzel, Nick Vaccaro, Zhuohao Lee, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Zhuohao Lee, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57069 to look at the new patch set (#9). Change subject: coreboot tables: Add type-c port info to coreboot table ...................................................................... coreboot tables: Add type-c port info to coreboot table This change adds type-c port information for USB Type-C ports to the coreboot table. This allows depthcharge to know the usb2 and usb3 port number assignments for each available port, as well as the SBU and data line orientation for the board. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage' and verify it buidls successfully. Cherry-pick CL to enable this feature for volteer, flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c Passing conn0 type-c info to payload: usb2:9 usb3:1 sbu:0 data:0 Passing conn1 type-c info to payload: usb2:4 usb3:2 sbu:1 data:0 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/coreboot_tables.h M src/drivers/intel/pmc_mux/conn/chip.h M src/drivers/intel/pmc_mux/conn/conn.c M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c 8 files changed, 166 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/57069/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/57069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Gerrit-Change-Number: 57069 Gerrit-PatchSet: 9 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork: correct MST probes
by Peter Marheine (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Sam McNally, Furquan Shaikh, Felix Held. Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57298 ) Change subject: mb/google/zork: correct MST probes ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: There might be a case for the behavior this is working around being a bug, but since `device ref` behavior isn't documented and the sconfig compiler is complex enough I can't tell if it's intended or a bug. -- To view, visit https://review.coreboot.org/c/coreboot/+/57298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a8feb544f3fc198fe6313b226ad8995aad31c3e Gerrit-Change-Number: 57298 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 01 Sep 2021 03:38:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: correct MST probes
by Peter Marheine (Code Review) 01 Sep '21

01 Sep '21

Peter Marheine has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/57298 ) Change subject: mb/google/zork: correct MST probes ...................................................................... mb/google/zork: correct MST probes It turns out that putting a device ref in an overridetree at a different point in the tree will generate a duplicate device definition, such that the change introducing this support was ignoring the device presence specified by overridetree.cb and only using the baseboard configuration. I believe testing of that change was not redone after the baseboard was changed to disable the MST, so that conflicting behavior was not noticed. The incorrect behavior generated a disabled device for the MST at the location specified by the baseboard, and one with the probe as a child of the soc. At runtime this did a fw_config probe of the "I2C 00:4a" device, and later probed a different "I2C 00:4a" which was already disabled. As the disabled one came later, it seems to have completely disabled the MST, discarding the results of the variant-specific probe. BUG=b:185862297 TEST=10EC2141 device is now present on a Dali berknip BRANCH=zork Change-Id: I2a8feb544f3fc198fe6313b226ad8995aad31c3e Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> --- M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/berknip/overridetree.cb M src/mainboard/google/zork/variants/morphius/overridetree.cb M src/mainboard/google/zork/variants/trembyle/overridetree.cb M src/mainboard/google/zork/variants/woomax/overridetree.cb 5 files changed, 66 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/57298/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a8feb544f3fc198fe6313b226ad8995aad31c3e Gerrit-Change-Number: 57298 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork: correct MST probes
by Peter Marheine (Code Review) 01 Sep '21

01 Sep '21

Peter Marheine has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57298 ) Change subject: mb/google/zork: correct MST probes ...................................................................... mb/google/zork: correct MST probes It turns out that putting a device ref in an overridetree at a different point in the tree will generate a duplicate device definition, such that the change introducing this support was ignoring the device presence specified by overridetree.cb and only using the baseboard configuration. I believe testing of that change was not redone after the baseboard was changed to disable the MST, so that conflicting behavior was not noticed. The incorrect behavior generated a disabled device for the MST at the location specified by the baseboard, and one with the probe as a child of the soc. At runtime this did a fw_config probe of the "I2C 00:4a" device, and later probed a different "I2C 00:4a" which was already disabled. As the disabled one came later, it seems to have completely disabled the MST, discarding the results of the variant-specific probe. BUG=b:185862297 TEST=10EC2141 device is now present on a Dali berknip BRANCH=zork Change-Id: I2a8feb544f3fc198fe6313b226ad8995aad31c3e --- M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/berknip/overridetree.cb M src/mainboard/google/zork/variants/morphius/overridetree.cb M src/mainboard/google/zork/variants/trembyle/overridetree.cb M src/mainboard/google/zork/variants/woomax/overridetree.cb 5 files changed, 66 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/57298/1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 824a007..f8e5d9a 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -372,7 +372,7 @@ end device ref lpc_bridge on chip ec/google/chromeec - device pnp 0c09.0 on + device pnp 0c09.0 alias cros_ec on chip ec/google/chromeec/i2c_tunnel register "uid" = "0" register "remote_bus" = "8" @@ -398,7 +398,7 @@ register "name" = ""MSTH"" register "uid" = "1" register "remote_bus" = "9" - device generic 1.0 on + device generic 1.0 alias cros_ec_i2c_9 on chip drivers/i2c/generic register "hid" = ""10EC2141"" register "name" = ""MSTH"" diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 793be78..434d4b3 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -104,6 +104,22 @@ # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit + + device ref lpc_bridge on + chip ec/google/chromeec + device ref cros_ec on + chip ec/google/chromeec/i2c_tunnel + device ref cros_ec_i2c_9 on + chip drivers/i2c/generic + device ref db_mst on + probe USB_DAUGHTERBOARD BERKNIP_DB_DALI + end + end + end + end + end + end + end end # domain device ref i2c_2 on @@ -179,8 +195,4 @@ end end - device ref db_mst on - probe USB_DAUGHTERBOARD BERKNIP_DB_DALI - end - end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index bb5e0e7..c5507e9 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -80,6 +80,22 @@ # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit + + device ref lpc_bridge on + chip ec/google/chromeec + device ref cros_ec on + chip ec/google/chromeec/i2c_tunnel + device ref cros_ec_i2c_9 on + chip drivers/i2c/generic + device ref db_mst on + probe USB_DAUGHTERBOARD MORPHIUS_DB_DALI + end + end + end + end + end + end + end end # domain device ref i2c_2 on @@ -144,8 +160,4 @@ end end - device ref db_mst on - probe USB_DAUGHTERBOARD MORPHIUS_DB_DALI - end - end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb index 394b3bc..c4ddc57 100644 --- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb +++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb @@ -53,6 +53,22 @@ # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit + + device ref lpc_bridge on + chip ec/google/chromeec + device ref cros_ec on + chip ec/google/chromeec/i2c_tunnel + device ref cros_ec_i2c_9 on + chip drivers/i2c/generic + device ref db_mst on + probe USB_DAUGHTERBOARD TREMBYLE_DB_DALI_HDMI + end + end + end + end + end + end + end end # domain device ref i2c_2 on @@ -113,8 +129,4 @@ end end - device ref db_mst on - probe USB_DAUGHTERBOARD TREMBYLE_DB_DALI_HDMI - end - end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index 82a060f..dd2bddd 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -87,6 +87,22 @@ chip drivers/usb/acpi device usb 3.2 off end end + + device ref lpc_bridge on + chip ec/google/chromeec + device ref cros_ec on + chip ec/google/chromeec/i2c_tunnel + device ref cros_ec_i2c_9 on + chip drivers/i2c/generic + device ref db_mst on + probe USB_DAUGHTERBOARD WOOMAX_DB_DALI + end + end + end + end + end + end + end end # domain device ref i2c_2 on @@ -117,8 +133,4 @@ end end - device ref db_mst on - probe USB_DAUGHTERBOARD WOOMAX_DB_DALI - end - end # chip soc/amd/picasso -- To view, visit https://review.coreboot.org/c/coreboot/+/57298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a8feb544f3fc198fe6313b226ad8995aad31c3e Gerrit-Change-Number: 57298 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdfwtool: Add support for traditional recovery
by build bot (Jenkins) (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Zheng Bao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57131 ) Change subject: amdfwtool: Add support for traditional recovery ...................................................................... Patch Set 4: (4 comments) File util/amdfwtool/amdfwtool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127175): https://review.coreboot.org/c/coreboot/+/57131/comment/c7c7a469_1cfda03d PS4, Line 519: index ++; space prohibited before that '++' (ctx:WxO) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127175): https://review.coreboot.org/c/coreboot/+/57131/comment/45a03d46_aa701c95 PS4, Line 806: for (index = 0; index < count; index ++) { space prohibited before that '++' (ctx:WxB) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127175): https://review.coreboot.org/c/coreboot/+/57131/comment/ca7f5d3b_a2457191 PS4, Line 817: count ++; space prohibited before that '++' (ctx:WxO) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127175): https://review.coreboot.org/c/coreboot/+/57131/comment/80ffb562_9e404442 PS4, Line 1799: BUFF_OFFSET(ctx, RUN_TO_OFFSET(ctx, pspdir2->entries[etr].addr)), line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/57131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2671b95fe089aafdaf61b55bc9d2e8dcf6a66dbc Gerrit-Change-Number: 57131 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Wed, 01 Sep 2021 03:20:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit September 2021