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Change subject: mb/google/dedede/var/gooey: Configure I2C times for I2C devices
......................................................................
Patch Set 1: Code-Review+1
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Change subject: mb/google/dedede/var/gooey: Generate SPD ID for supported part
......................................................................
Patch Set 1:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57310/comment/ed42b2fa_acc60ebb
PS1, Line 2: stanley.wu
Please use *Stanley Wu*.
$ git config --global user.name "Stanley Wu"
$ git commit -s --amend "Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com>"
https://review.coreboot.org/c/coreboot/+/57310/comment/97443419_0d2b42f7
PS1, Line 7: Generate SPD ID for supported part
Maybe:
> Add MT53E512M32D1NP-046 as supported mem module
https://review.coreboot.org/c/coreboot/+/57310/comment/219aeb72_05285d72
PS1, Line 11: MT53E512M32D1NP-046 WT:B
1. What is the difference to MT53E512M32D2NP-046?
2. Any idea, who the manufacturer is?
https://review.coreboot.org/c/coreboot/+/57310/comment/af8b9e13_8f32e382
PS1, Line 17: Signed-off-by: stanley.wu <stanley1.wu(a)lcfc.corp-partner.google.com>
Ditto.
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Change subject: arch/x86: Skip returning default leaf value as `0`
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57305/comment/db90d591_dda24687
PS1, Line 12: skip
skips
https://review.coreboot.org/c/coreboot/+/57305/comment/be24f6c2_51c530b6
PS1, Line 14:
Please mention the hang on the ASRock E350M1, and also add a `Fixes:` tag.
Patchset:
PS1:
Thank you for addressing this so quickly.
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Change subject: arch/x86: Check unsupported CPU type while writing to SMBIOS table 7
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> E350M1 is booting again with this patch
Thanks for checking this.
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Change subject: arch/x86: Skip returning default leaf value as `0`
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Patch Set 1:
(1 comment)
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PS1:
I can only tell that it boots on E350M1
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Stanley Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57310 )
Change subject: mb/google/dedede/var/gooey: Generate SPD ID for supported part
......................................................................
mb/google/dedede/var/gooey: Generate SPD ID for supported part
Add supported memory part in the mem_parts_used.txt and generate the
SPD ID for the part. The memory part being added is:
MT53E512M32D1NP-046 WT:B
BUG=b:194223174
BRANCH=dedede
TEST=Build the gooey board.
Signed-off-by: stanley.wu <stanley1.wu(a)lcfc.corp-partner.google.com>
Change-Id: I7b83126a2bf98bb9d0ca05d397c288e0d99ed781
---
M src/mainboard/google/dedede/variants/gooey/memory/Makefile.inc
M src/mainboard/google/dedede/variants/gooey/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/gooey/memory/mem_list_variant.txt
3 files changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/57310/1
diff --git a/src/mainboard/google/dedede/variants/gooey/memory/Makefile.inc b/src/mainboard/google/dedede/variants/gooey/memory/Makefile.inc
index d0960c7..c0c0902 100644
--- a/src/mainboard/google/dedede/variants/gooey/memory/Makefile.inc
+++ b/src/mainboard/google/dedede/variants/gooey/memory/Makefile.inc
@@ -2,4 +2,4 @@
## This is an auto-generated file. Do not edit!!
SPD_SOURCES =
-SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE
+SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE, MT53E512M32D1NP-046 WT:B
diff --git a/src/mainboard/google/dedede/variants/gooey/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/gooey/memory/dram_id.generated.txt
index 0df7bfc..7576d17 100644
--- a/src/mainboard/google/dedede/variants/gooey/memory/dram_id.generated.txt
+++ b/src/mainboard/google/dedede/variants/gooey/memory/dram_id.generated.txt
@@ -2,3 +2,4 @@
MT53E512M32D2NP-046 WT:E 0 (0000)
K4U6E3S4AA-MGCR 0 (0000)
H9HCNNNBKMMLXR-NEE 0 (0000)
+MT53E512M32D1NP-046 WT:B 0 (0000)
diff --git a/src/mainboard/google/dedede/variants/gooey/memory/mem_list_variant.txt b/src/mainboard/google/dedede/variants/gooey/memory/mem_list_variant.txt
index 47159f8..04f01b3 100644
--- a/src/mainboard/google/dedede/variants/gooey/memory/mem_list_variant.txt
+++ b/src/mainboard/google/dedede/variants/gooey/memory/mem_list_variant.txt
@@ -1,3 +1,4 @@
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNBKMMLXR-NEE
+MT53E512M32D1NP-046 WT:B
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Swift Geek (Sebastian Grzywna) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57307 )
Change subject: mb/asrock/e350m1: Enable USB on mPCIe
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Tested on E350M1/USB3 with ath3k as full speed device, and a pendrive as a high speed device.
On master (with CB:56121) reverted it's visible in grub, USB appears to be broken in linux on this board since CB:38564 according to my limited testing. Applied on top of 9a5d6e958f4ff9fd35439bf6c6f37c852725592c works perfectly fine in linux.
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Change subject: util/cbftool: Fix the bug in parsing Uefipayload with extended header
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Patch Set 3: Code-Review+1
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