coreboot-gerrit September 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sc7280: Add PCIe RC driver in Coreboot
by build bot (Jenkins) (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Shelley Chen, Ravi kumar, Furquan Shaikh, Sudheer Amrabadi, Julius Werner, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53902 ) Change subject: sc7280: Add PCIe RC driver in Coreboot ...................................................................... Patch Set 34: (1 comment) File src/soc/qualcomm/sc7280/include/soc/pcie.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127219): https://review.coreboot.org/c/coreboot/+/53902/comment/6c890c2f_8a5ddcd1 PS34, Line 168: #define PCIE_DEV_FUNC (dev, func) {(PCI_SLOT(devfn)) | (PCI_FUNC(devfn))} Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/53902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631 Gerrit-Change-Number: 53902 Gerrit-PatchSet: 34 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Wed, 01 Sep 2021 11:56:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/google/herobrine: Increase the ROM size
by Ravi kumar (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Sajida Bhanu. Hello Sajida Bhanu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/57312 to review the following change. Change subject: mainboard/google/herobrine: Increase the ROM size ...................................................................... mainboard/google/herobrine: Increase the ROM size SPI NOR size should match with coreboot ROM size. On QCOM Piglin board SPI NOR size is 64MB and the default coreboot ROM size is 8MB. So, update coreboot ROM size to match with SPI NOR size. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board and checked basic boot up. Signed-off-by: Shaik Sajida Bhanu <sbhanu(a)codeaurora.org> Change-Id: Ifb41dc4bfbc43be7f2a53c8a8ebfd5f490f0de5f --- M src/drivers/spi/spi_flash.c M src/mainboard/google/herobrine/Kconfig 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/57312/1 diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index f3cecd5..47de069 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -506,6 +506,7 @@ mode_string = " (Dual I/O mode)"; else if (flash->flags.dual_output && spi.ctrlr->xfer_dual) mode_string = " (Dual Output mode)"; + printk(BIOS_INFO, "SF: Detected %02x %04x with sector size 0x%x, total 0x%x%s\n", flash->vendor, flash->model, flash->sector_size, flash->size, mode_string); diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig index e963f4c..a2e10a0 100644 --- a/src/mainboard/google/herobrine/Kconfig +++ b/src/mainboard/google/herobrine/Kconfig @@ -5,7 +5,8 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select BOARD_ROMSIZE_KB_8192 + select BOARD_ROMSIZE_KB_65536 if BOARD_GOOGLE_PIGLIN + select BOARD_ROMSIZE_KB_8192 if !BOARD_GOOGLE_PIGLIN select COMMON_CBFS_SPI_WRAPPER select EC_GOOGLE_CHROMEEC if !BOARD_GOOGLE_SENOR select EC_GOOGLE_CHROMEEC_RTC if !BOARD_GOOGLE_SENOR -- To view, visit https://review.coreboot.org/c/coreboot/+/57312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb41dc4bfbc43be7f2a53c8a8ebfd5f490f0de5f Gerrit-Change-Number: 57312 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Attention: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/qualcomm/sc7280: DDR One-Time-Training Support
by Ravi kumar (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Shelley Chen, Ravi kumar, Paul Menzel, Sudheer Amrabadi. Hello build bot (Jenkins), Sudheer Amrabadi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54352 to look at the new patch set (#31). Change subject: soc/qualcomm/sc7280: DDR One-Time-Training Support ...................................................................... soc/qualcomm/sc7280: DDR One-Time-Training Support Introduce DDR One-Time-Training Support Device reboots without training from second iteration and also DDR training data is 32kb size, hence update required in memlayout and to sync with upstream changes the Fmap size even got bumped up. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4 Signed-off-by: Sudheer Kumar Amrabadi <samrabad(a)codeaurora.org> --- M src/mainboard/google/herobrine/chromeos.fmd M src/soc/qualcomm/sc7280/memlayout.ld 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/54352/31 -- To view, visit https://review.coreboot.org/c/coreboot/+/54352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4 Gerrit-Change-Number: 54352 Gerrit-PatchSet: 31 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: qualcomm/sc7280: Move to use common clock driver for sc7280
by Ravi kumar (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Ravi kumar, Taniya Das, Paul Menzel, mturney mturney. Hello Shelley Chen, build bot (Jenkins), Taniya Das, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50580 to look at the new patch set (#62). Change subject: qualcomm/sc7280: Move to use common clock driver for sc7280 ...................................................................... qualcomm/sc7280: Move to use common clock driver for sc7280 It supports the clock consumers for QUP, SDCC, PCIE, Display to be able to configure & enable the desired clocks. The clock driver also supports reset of subsystems like AOP and SHRM. Also add support for Zonda PLL enable for CPU in common clock driver. Refactor the SC7280 clock driver to use the common clock driver APIs. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77 Signed-off-by: Taniya Das <tdas(a)codeaurora.org> --- M src/soc/qualcomm/common/clock.c M src/soc/qualcomm/common/include/soc/clock_common.h M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/clock.c M src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/clock.h 6 files changed, 914 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/50580/62 -- To view, visit https://review.coreboot.org/c/coreboot/+/50580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77 Gerrit-Change-Number: 50580 Gerrit-PatchSet: 62 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/qualcomm/common: clock: Add support for common clock driver
by Ravi kumar (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Ravi kumar, Paul Menzel, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Taniya Das, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56588 to look at the new patch set (#7). Change subject: soc/qualcomm/common: clock: Add support for common clock driver ...................................................................... soc/qualcomm/common: clock: Add support for common clock driver The clock driver supports configuring the general purpose PLLs, configuring the root clock generator (RCG), enable clock branch, enable gdsc and also the block resets. The common clock driver exposes PLL configuration functions and also different Agera PLL enable functions for the CPU PLLs. While at it, the common driver also supports reset of subsystems like AOP and SHRM. SC7180 clock driver is also refactored to use the common clock driver APIs. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Change-Id: I03d1b4a2fb90303c7259ec08f312d78b4e33ec39 Signed-off-by: Taniya Das <tdas(a)codeaurora.org> --- A src/soc/qualcomm/common/clock.c A src/soc/qualcomm/common/include/soc/clock_common.h M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/include/soc/clock.h 5 files changed, 513 insertions(+), 353 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/56588/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/56588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03d1b4a2fb90303c7259ec08f312d78b4e33ec39 Gerrit-Change-Number: 56588 Gerrit-PatchSet: 7 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: qualcomm/sc7180: Clean up drivers with common clock
by Ravi kumar (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Shelley Chen, Ravi kumar, Paul Menzel, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Taniya Das, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56587 to look at the new patch set (#8). Change subject: qualcomm/sc7180: Clean up drivers with common clock ...................................................................... qualcomm/sc7180: Clean up drivers with common clock As we move to use the common clock driver, the sc7180 clock driver, watchdog and display drivers requires few cleanups, thus update the impacted drivers. Earlier the display client is expected to provide 2n divider value, as the divider value in register is in form "2n-1". mdss_clk_cfg.div = half_divider ? (half_divider - 1) : 0; The older convention in the upcoming patches would be replaced with the common macro of QCOM_CLOCK_DIV, thus need the divider needs to be updated. mdss_clk_cfg.div = half_divider ? QCOM_CLOCK_DIV(half_divider) : 0; To accommodate impacting the functionality, the half_divider is taken care in the clock driver. BUG=b:182963902 TEST=Validated on qualcomm sc7180 development board Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66 Signed-off-by: Taniya Das <tdas(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/display/dsi_phy.c M src/soc/qualcomm/sc7180/include/soc/clock.h M src/soc/qualcomm/sc7180/watchdog.c 4 files changed, 70 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/56587/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/56587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66 Gerrit-Change-Number: 56587 Gerrit-PatchSet: 8 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/qualcomm/sc7280: DDR One-Time-Training Support
by Ravi Kumar Bokka (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Shelley Chen, Ravi kumar, Paul Menzel, Sudheer Amrabadi. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54352 ) Change subject: soc/qualcomm/sc7280: DDR One-Time-Training Support ...................................................................... Patch Set 30: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54352/comment/95c7dd08_9fa15d2d PS16, Line 10: > ping? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4 Gerrit-Change-Number: 54352 Gerrit-PatchSet: 30 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Wed, 01 Sep 2021 11:43:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Make framebuffer orientation to be configurable
by Nico Huber (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Furquan Shaikh, shkim, Paul Menzel, SH Kim, Julius Werner, Angel Pons, Andrey Petrov, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57199 ) Change subject: drivers/intel/fsp2_0: Make framebuffer orientation to be configurable ...................................................................... Patch Set 1: (3 comments) Patchset: PS1: > I heard that the panel hardware in use for bugzzy is not able to rotate the framebuffer itself. I meant the graphics hardware. For instance, Intel's display engine supports 90 degree rotation of the framebuffer since Skylake. File src/drivers/intel/fsp2_0/graphics.c: https://review.coreboot.org/c/coreboot/+/57199/comment/482d85b9_571f7c04 PS1, Line 103: enum lb_fb_orientation __weak fsp_get_framebuffer_orientation(void) > Not sure what you mean by "a common solution"? The `orientation` field in lb_framebuffer is the common solution that we already have, it's already used by several other boards. How the platform driver gets it there before calling fb_add_framebuffer is up to the platform driver, just like for all the other parameters. I assumed it meant a more common place in the code. There seems to be no need to make this FSP specific. > 1. Actually I'm not familiar with open source graphics init in coreboot, but it seems we have some interfaces to override the orientation setting for each panel and each project in coreboot(lib/edid_fill_fb.c), but Yu-Ping Wu mentioned we couldn't use it for intel project using FSP graphics init. There's a call to fb_add_framebuffer_info_ex() above. I have no idea why it couldn't be done inside that function or below. https://review.coreboot.org/c/coreboot/+/57199/comment/a39e6ec1_98cdc0d3 PS1, Line 106: } > If we'd put a config for screen orientation, do you think we should use the config for FSP graphics […] I don't see a difference if you do it here or there. What refactoring do you see necessary? NB. `edid_fill_fb.c` is not considered graphics init. It's just some infrastructure code to report framebuffers. Each silicon vendor has their own graphics init so far. Most ARM SoCs have it below their respective src/soc/ dir. For Intel (up to 9.5th gen display engine), we have 3rdparty/libgfxinit. AMD is the only silicon vendor I know about that keeps their display engine closed. Alas, libgfxinit is not developed much right now because Intel only updated their consumer products for some years and my employer doesn't care about those. And other coreboot-involved companies working with Intel don't care about open source. Their usual excuse that the hardware isn't documented and writing open-source code would be hard doesn't work for Intel graphics ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/57199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If51d2698d5fdf651183a908717076c8a14605997 Gerrit-Change-Number: 57199 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: shkim <sh_.kim(a)samsung.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 01 Sep 2021 10:45:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: shkim <sh_.kim(a)samsung.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: [WIP]Trigger cse_fw_sync before DRAM Init
by Paul Menzel (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Sridhar Siricilla, Tim Wawrzynczak, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55364 ) Change subject: soc/intel/alderlake: [WIP]Trigger cse_fw_sync before DRAM Init ...................................................................... Patch Set 3: (4 comments) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/55364/comment/d327693b_c122b8e9 PS3, Line 132: Init initialization https://review.coreboot.org/c/coreboot/+/55364/comment/7f96bdfe_6467d741 PS3, Line 132: Dependendcy Dependency https://review.coreboot.org/c/coreboot/+/55364/comment/2e6fdcc1_bb437485 PS3, Line 132: Dependendcy :CSE ` :` → `: ` https://review.coreboot.org/c/coreboot/+/55364/comment/b300e695_48a64936 PS3, Line 133: if (!s3wake) { : if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) Nit: You could put it in one line. -- To view, visit https://review.coreboot.org/c/coreboot/+/55364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d Gerrit-Change-Number: 55364 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 01 Sep 2021 10:06:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add HECI Reset flow in the CSE driver
by Paul Menzel (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Sridhar Siricilla, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55363 ) Change subject: soc/intel/common: Add HECI Reset flow in the CSE driver ...................................................................... Patch Set 2: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55363/comment/156af108_4dde14f8 PS2, Line 8: Please start by stating the problem. https://review.coreboot.org/c/coreboot/+/55363/comment/ffeb9e6f_ebfe9881 PS2, Line 9: This is required as part : of the HECI Interface initialization in order to put the host and CSE into : a known good state for communication. Please reference the specification. https://review.coreboot.org/c/coreboot/+/55363/comment/f43f3ab6_9cd10b14 PS2, Line 15: Is there bug for this? File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/55363/comment/4eae7dac_a3b41231 PS2, Line 104: makes make https://review.coreboot.org/c/coreboot/+/55363/comment/460c1ba5_cf6ca512 PS2, Line 104: Triggers Imperative mood: Trigger. https://review.coreboot.org/c/coreboot/+/55363/comment/db11a750_e57695e0 PS2, Line 105: heci_reset(); How much time does this take? (Please also mention that in the commit message.) -- To view, visit https://review.coreboot.org/c/coreboot/+/55363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie078beaa33c6a35ae8f5f460d4354766aa710fba Gerrit-Change-Number: 55363 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 01 Sep 2021 10:03:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit September 2021