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Change subject: soc/intel/alderlake: Add tpch device information under dptf
......................................................................
soc/intel/alderlake: Add tpch device information under dptf
Add tpch device information for FIVR functionality under dptf
for alderlake soc based platform.
Change-Id: Iad8e8bc0b7a104bbe582bc477936d0d00087f1d1
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/soc/intel/alderlake/dptf.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/57097/3
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Change subject: tpch: Introduce new thermal control mechanism for pch device
......................................................................
tpch: Introduce new thermal control mechanism for pch device
Introduce new thermal control mechanism for pch device.
Change-Id: I035d2844b9ba6a9532ae006fc1c43e34cb94328a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/drivers/intel/dptf/Kconfig
M src/drivers/intel/dptf/dptf.c
M src/drivers/intel/dptf/dptf.h
3 files changed, 75 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/57096/3
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Change subject: soc/intel/common: Add PMC IPC commands for FIVR
......................................................................
soc/intel/common: Add PMC IPC commands for FIVR
Add PMC IPC commands information for FIVR control functionality.
Change-Id: Iccb43b7ba4f0765499bf1844efbbb526bd671a8f
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/soc/intel/common/block/include/intelblocks/pmc_ipc.h
1 file changed, 9 insertions(+), 0 deletions(-)
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Change subject: soc/intel/alderlake: set power limits dynamically for thermal
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/alderlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/57035/comment/2ad0b915_578c4dc3
PS8, Line 74: sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF;
> if sa_pci_id == 0xFFFF should we halt? or assert some error?
Halt might not be good option, as per flow we show below line 90 error message.
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Hello build bot (Jenkins), Tim Wawrzynczak, Wisley Chen,
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Change subject: mb/google/brya/var/redrix: adjust uid for Maxim amp
......................................................................
mb/google/brya/var/redrix: adjust uid for Maxim amp
DEV0 - 0x3a i2c-MX98390:00: Right Speaker
DEV1 - 0x3b i2c-MX98390:01: Left Speaker
DEV2 - 0x38 i2c-MX98390:02: Right Tweeter
DEV2 - 0x39 i2c-MX98390:03: Left Tweeter
This is to consist with other 2 speakers configs, and m/c driver design.
uid0/1 = regular speakers.
uid2/3 = tweeter
BUG=191931762
TEST=FW_NAME=redrix emerge-brya coreboot
Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com>
Change-Id: I0a3183b1e1ecbb109258d6e076551158e0b40ce1
---
M src/mainboard/google/brya/variants/redrix/overridetree.cb
1 file changed, 4 insertions(+), 4 deletions(-)
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Mike Banon has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/51394 )
Change subject: lenovo/g505s: enable the AMD Core Performance Boost (CPB) feature
......................................................................
Abandoned
Since CB:51396 has been merged, this change is not needed anymore. However, since it has been referred to in a commit message of CB:51396, it shouldn't be removed - just abandoned.
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Change subject: soc/intel/alderlake: set power limits dynamically for thermal
......................................................................
Patch Set 8: Code-Review+1
(2 comments)
Patchset:
PS8:
Others LGTM.
File src/soc/intel/alderlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/57035/comment/9415a933_3763ac82
PS8, Line 74: sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF;
if sa_pci_id == 0xFFFF should we halt? or assert some error?
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Change subject: soc/intel/alderlake: set power limits dynamically for thermal
......................................................................
Patch Set 8:
(4 comments)
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/57035/comment/e7b97bfb_e97c00e7
PS7, Line 35: ADL_P_282_15W = 15,
> ex TDP_15W=15 then you can use in […]
Done
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/57035/comment/8a5368e7_99aba206
PS6, Line 34: enum soc_intel_alderlake_cpu_tdps {
> if the value are the same, you can just declare 9W 15W 28W 45W. […]
Ack
File src/soc/intel/alderlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/57035/comment/fb3986d4_d3a4fcbf
PS4, Line 80: switch (sa_pci_id) {
> That works 😊
Done
File src/soc/intel/alderlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/57035/comment/e381d982_92858872
PS7, Line 81: if (sa_pci_id == cpuid_to_adlp[i].cpu_id) {
> you can use && here as well
Done
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Change subject: util/cbftool: Fix the bug in parsing Uefipayload with extended header
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57296/comment/e769ea5e_02550d50
PS3, Line 14:
> Add in the commit message: […]
Please add the link and offending EDK2 commit hash to the commit message as well.
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