coreboot-gerrit September 2021

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Change in coreboot[master]: mb/google/brya/variants: fix override values for power limits
by Sumeet R Pawnikar (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Sumeet Pawnikar, Furquan Shaikh, Tim Wawrzynczak, Karthik Ramasubramanian. Hello Sumeet Pawnikar, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, EricR Lai, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57290 to look at the new patch set (#2). Change subject: mb/google/brya/variants: fix override values for power limits ...................................................................... mb/google/brya/variants: fix override values for power limits Fix override values for power limits for 28W and 45W TDP based 682 SKU. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I796e56321ae9c8312530a4b8986cd73a2245f5fa Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/brya/variants/baseboard/brya/ramstage.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/brya/variants/brya0/ramstage.c 3 files changed, 9 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/57290/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I796e56321ae9c8312530a4b8986cd73a2245f5fa Gerrit-Change-Number: 57290 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: set power limits dynamically for thermal
by Sumeet R Pawnikar (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Furquan Shaikh, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57035 to look at the new patch set (#8). Change subject: soc/intel/alderlake: set power limits dynamically for thermal ...................................................................... soc/intel/alderlake: set power limits dynamically for thermal Set power limit values dynamically based on CPU TDP and PCI ID of SKU. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Ic331a3debb076ef08a312a31edc1468974fd4902 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/systemagent.c 3 files changed, 57 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/57035/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/57035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic331a3debb076ef08a312a31edc1468974fd4902 Gerrit-Change-Number: 57035 Gerrit-PatchSet: 8 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: get tdp of CPU for different SKUs
by Sumeet R Pawnikar (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, Sumeet R Pawnikar, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, EricR Lai, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57143 to look at the new patch set (#4). Change subject: soc/intel/common: get tdp of CPU for different SKUs ...................................................................... soc/intel/common: get tdp of CPU for different SKUs Get tdp value of CPU for different SKUs based on PKG POWER MSR. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I9fba0a64da2f1d79d633054dddd9fdf1d3d8e258 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/power_limit.h M src/soc/intel/common/block/power_limit/power_limit.c 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/57143/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/57143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fba0a64da2f1d79d633054dddd9fdf1d3d8e258 Gerrit-Change-Number: 57143 Gerrit-PatchSet: 4 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/drawcia: change LTE reset pin to GPP_H17
by Chen Wisley (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Henry Sun, Paul Menzel, Karthik Ramasubramanian. Chen Wisley has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57204 ) Change subject: mb/google/dedede/var/drawcia: change LTE reset pin to GPP_H17 ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > Thanks for the update, and thanks for updating the issue too. LGTM, differ to Karthik to approve. Hi Karthik, Please help to review Thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/57204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib65580babf7d21535df2bd8d33bb19261bebfe15 Gerrit-Change-Number: 57204 Gerrit-PatchSet: 3 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 12:38:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Henry Sun <henrysun(a)google.com> Comment-In-Reply-To: Chen Wisley <wisley.chen(a)quantatw.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/redrix: adjust uid for Maxim amp
by Chen Wisley (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Paul Menzel, Angel Pons, Keith Tzeng. Chen Wisley has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57208 ) Change subject: mb/google/brya/var/redrix: adjust uid for Maxim amp ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57208/comment/ffee1c7e_8b661eed PS1, Line 13: > Please mention that in the commit message. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/57208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a3183b1e1ecbb109258d6e076551158e0b40ce1 Gerrit-Change-Number: 57208 Gerrit-PatchSet: 3 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 12:36:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/cbftool: Fix the bug in parsing Uefipayload with extended header
by King Sumo (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Patrick Rudolph, Paul Menzel, Dun Tan. King Sumo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57296 ) Change subject: util/cbftool: Fix the bug in parsing Uefipayload with extended header ...................................................................... Patch Set 3: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/57296/comment/0151471b_2fb7616f PS3, Line 10: This issue is caused by adding FvNameGuid : in UefiPayloadEntry.fdf in EDKII. There is an ext header between header : of Fv and header of PayloadEntry in Fv with FvNameGuid. The ext header : causes the UefiPayloadEntry to be found incorrectly when parsing Fv. > Is that a recent change in UefiPayload? Yes: commit 4bac086e8e007c7143e33f87bb96238326d1d6ba Author: Zhiguang Liu <zhiguang.liu(a)intel.com> Date: Wed Jul 14 14:24:45 2021 +0800 UefiPayloadPkg: Add FV Guid for DXEFV and PLDFV See also: https://bugzilla.tianocore.org/show_bug.cgi?id=3585 https://review.coreboot.org/c/coreboot/+/57296/comment/34897175_22212661 PS3, Line 14: Add in the commit message: Link: https://bugzilla.tianocore.org/show_bug.cgi?id=3585 -- To view, visit https://review.coreboot.org/c/coreboot/+/57296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id063efb1c8e6c7a96ec2182e87b71c7e8b7b6423 Gerrit-Change-Number: 57296 Gerrit-PatchSet: 3 Gerrit-Owner: Dun Tan <dun.tan(a)intel.com> Gerrit-Reviewer: King Sumo <kingsumos(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dun Tan <dun.tan(a)intel.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 12:27:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: update Haswell document on SPD
by Angel Pons (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Iru Cai, Iru Cai (vimacs). Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54745 ) Change subject: Documentation: update Haswell document on SPD ...................................................................... Patch Set 2: (1 comment) File Documentation/northbridge/intel/haswell/mrc.bin.md: https://review.coreboot.org/c/coreboot/+/54745/comment/7e06f392_801b3852 PS2, Line 102: The SPD addresses need to be left-shifted by 1 for `mrc.bin`, i.e., multiplied : by 2. For example, if the addresses read through `i2c-tools` when booted from : vendor firmware are `0x50` and `0x52`, the correct values would be `0xa0` and : `0xa4`. This is because the I2C addresses are 7 bits long. I believe the added paragraph is likely to confuse readers: do the SPD addresses in mainboard code need to be left-shifted or not? Instead of adding a new paragraph, I'd change this paragraph. The `spdi->addresses` values programmed in mainboard code are left-shifted in wrapper code to match the format MRC expects, so the SPD addresses in `spdi->addresses` do *not* need to be left-shifted. -- To view, visit https://review.coreboot.org/c/coreboot/+/54745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d545a1aeae9e4bf2ec792ab3dc85abd83fe1762 Gerrit-Change-Number: 54745 Gerrit-PatchSet: 2 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Attention: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 12:27:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nipperkin: Set eSPI alert as dedicated open drain
by Rob Barnes (Code Review) 01 Sep '21

01 Sep '21

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57313 ) Change subject: nipperkin: Set eSPI alert as dedicated open drain ...................................................................... nipperkin: Set eSPI alert as dedicated open drain Nipperkin boards use a dedicated eSPI alert#. Must be open drain to prevent power leaks. BUG=b:198409370 TEST=Build nipperkin BRANCH=None Change-Id: I4b23bfc6a1167aebfde5acd524fda043b63163dc Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 1 file changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/57313/1 diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index c182265..6b6be7e 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -4,4 +4,43 @@ device domain 0 on end # domain + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x62, + /* + * Only 0x62 and 0x66 are required. But, this is not supported by + * standard IO decodes and there are only 4 generic I/O windows + * available. Hence, open a window from 0x62-0x67. + */ + .size = 5, + }, + .generic_io_range[1] = { + .base = 0x800, /* EC_HOST_CMD_REGION0 */ + .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ + }, + .generic_io_range[2] = { + .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ + .size = 255, /* EC_MEMMAP_SIZE */ + }, + .generic_io_range[3] = { + .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ + .size = 8, /* 0x200 - 0x207 */ + }, + + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + + .alert_pin = ESPI_ALERT_PIN_OPEN_DRAIN, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 0, + .flash_ch_en = 0, + + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1), + }" + end # chip soc/amd/cezanne -- To view, visit https://review.coreboot.org/c/coreboot/+/57313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b23bfc6a1167aebfde5acd524fda043b63163dc Gerrit-Change-Number: 57313 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: add Intel Broadwell
by Angel Pons (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Felix Singer, Paul Menzel, Iru Cai, Iru Cai (vimacs). Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54744 ) Change subject: Documentation: add Intel Broadwell ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b1c29162a64030b5c100368f2471702e22b8311 Gerrit-Change-Number: 54744 Gerrit-PatchSet: 6 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Attention: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 12:17:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: add Intel Broadwell
by Angel Pons (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Felix Singer, Paul Menzel, Iru Cai, Iru Cai (vimacs). Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54744 ) Change subject: Documentation: add Intel Broadwell ...................................................................... Patch Set 6: Code-Review+1 (1 comment) File Documentation/soc/intel/broadwell/blobs.md: https://review.coreboot.org/c/coreboot/+/54744/comment/65299d00_0c5f27bc PS6, Line 38: Broadwell SoC code doesn't support non-ULT Haswell or non-ULT Broadwell boards. FWIW, I've tested Broadwell MRC.bin on the Asrock B85M Pro4 and it works properly. Of course, the code needs to be adapted and one needs to implement the things the Broadwell refcode blob does. -- To view, visit https://review.coreboot.org/c/coreboot/+/54744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b1c29162a64030b5c100368f2471702e22b8311 Gerrit-Change-Number: 54744 Gerrit-PatchSet: 6 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Attention: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 12:17:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit September 2021