coreboot-gerrit September 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: src/ec/google/chromeec: Add and modify APIs for USB-C DP ALT mode
by Tim Wawrzynczak (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Furquan Shaikh, Derek Huang, Brandon Breitenstein, Curtis Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57138 ) Change subject: src/ec/google/chromeec: Add and modify APIs for USB-C DP ALT mode ...................................................................... Patch Set 5: (2 comments) File src/ec/google/chromeec/ec.c: https://review.coreboot.org/c/coreboot/+/57138/comment/5df6246d_e4ff5549 PS5, Line 1567: -1 means check all port Please change this to a symbolic constant, e,g.: `#define EC_ALL_PORTS -1` https://review.coreboot.org/c/coreboot/+/57138/comment/33330e3d_a8a4ed56 PS5, Line 1592: >= 0 `!= EC_ALL_PORTS` -- To view, visit https://review.coreboot.org/c/coreboot/+/57138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3 Gerrit-Change-Number: 57138 Gerrit-PatchSet: 5 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 16:50:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Fix processor hang while plug unplug of TBT device
by Tim Wawrzynczak (Code Review) 01 Sep '21

01 Sep '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56503 ) Change subject: soc/intel/alderlake: Fix processor hang while plug unplug of TBT device ...................................................................... soc/intel/alderlake: Fix processor hang while plug unplug of TBT device Processor hang is observed while hot plug unplug of TBT device. BIOS should execute TBT PCIe RP RTD3 flow based on the value of TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if BIT30 in TBT FW version is not set. BUG=b:194880254 Change-Id: Ie3577df519f64c6f7270dc5537278af76536774e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56503 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/acpi/tcss.asl M src/soc/intel/alderlake/acpi/tcss_dma.asl 2 files changed, 10 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index d01d872..82cbad63 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -555,12 +555,13 @@ Printf("TDM0 does not exist.") } Else { If (\_SB.PCI0.TDM0.STAT == 1) { - If (\_SB.PCI0.TDM0.INFR != 1) { - Return - } /* DMA0 is not in D3Cold now. */ \_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */ + If (\_SB.PCI0.TDM0.IF30 != 1) { + Return + } + Printf("Push TBT RPs to D3Cold together") If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { /* Put RP0 to D3 cold. */ @@ -613,12 +614,13 @@ Printf("TDM1 does not exist.") } Else { If (\_SB.PCI0.TDM1.STAT == 1) { - If (\_SB.PCI0.TDM1.INFR != 1) { - Return - } /* DMA1 is not in D3Cold now */ \_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */ + If (\_SB.PCI0.TDM1.IF30 != 1) { + Return + } + Printf("Push TBT RPs to D3Cold together") If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { /* Put RP2 to D3 cold. */ diff --git a/src/soc/intel/alderlake/acpi/tcss_dma.asl b/src/soc/intel/alderlake/acpi/tcss_dma.asl index d00f794..0b5e03f 100644 --- a/src/soc/intel/alderlake/acpi/tcss_dma.asl +++ b/src/soc/intel/alderlake/acpi/tcss_dma.asl @@ -11,7 +11,8 @@ , 6, PMES, 1, /* 15, PME_STATUS */ Offset(0xC8), /* 0xC8, TBT NVM FW Revision */ - , 31, + , 30, + IF30, 1, /* ITBT FW Version Bit30 */ INFR, 1, /* TBT NVM FW Ready */ Offset(0xEC), /* 0xEC, TBT TO PCIE Register */ TB2P, 32, /* TBT to PCIe */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3577df519f64c6f7270dc5537278af76536774e Gerrit-Change-Number: 56503 Gerrit-PatchSet: 8 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Fix processor hang while plug unplug of TBT device
by Tim Wawrzynczak (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Abhijeet Rao, Furquan Shaikh, Sugnan Prabhu S, Paul Menzel, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56503 ) Change subject: soc/intel/alderlake: Fix processor hang while plug unplug of TBT device ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3577df519f64c6f7270dc5537278af76536774e Gerrit-Change-Number: 56503 Gerrit-PatchSet: 7 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.corp-partner.google.com> Gerrit-Attention: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.corp-partner.google.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 01 Sep 2021 16:46:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/redrix: adjust uid for Maxim amp
by Tim Wawrzynczak (Code Review) 01 Sep '21

01 Sep '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57208 ) Change subject: mb/google/brya/var/redrix: adjust uid for Maxim amp ...................................................................... mb/google/brya/var/redrix: adjust uid for Maxim amp DEV0 - 0x3a i2c-MX98390:00: Right Speaker DEV1 - 0x3b i2c-MX98390:01: Left Speaker DEV2 - 0x38 i2c-MX98390:02: Right Tweeter DEV2 - 0x39 i2c-MX98390:03: Left Tweeter This is to consist with other 2 speakers configs, and m/c driver design. uid0/1 = regular speakers. uid2/3 = tweeter BUG=191931762 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: I0a3183b1e1ecbb109258d6e076551158e0b40ce1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57208 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 8f845d1..0e0cab4 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -185,7 +185,7 @@ register "name" = ""MXW0"" register "r0_calib_key" = ""dsm_calib_r0_0"" register "temperature_calib_key" = ""dsm_calib_temp_0"" - device i2c 0x38 on end + device i2c 0x3a on end end chip drivers/i2c/max98390 register "desc" = ""MAX98390 Speaker Amp 1"" @@ -193,7 +193,7 @@ register "name" = ""MXW1"" register "r0_calib_key" = ""dsm_calib_r0_1"" register "temperature_calib_key" = ""dsm_calib_temp_1"" - device i2c 0x39 on end + device i2c 0x3b on end end chip drivers/i2c/max98390 register "desc" = ""MAX98390 Speaker Amp 2"" @@ -201,7 +201,7 @@ register "name" = ""MXW2"" register "r0_calib_key" = ""dsm_calib_r0_2"" register "temperature_calib_key" = ""dsm_calib_temp_2"" - device i2c 0x3a on end + device i2c 0x38 on end end chip drivers/i2c/max98390 register "desc" = ""MAX98390 Speaker Amp 3"" @@ -209,7 +209,7 @@ register "name" = ""MXW3"" register "r0_calib_key" = ""dsm_calib_r0_3"" register "temperature_calib_key" = ""dsm_calib_temp_3"" - device i2c 0x3b on end + device i2c 0x39 on end end end #I2C0 device ref i2c1 on -- To view, visit https://review.coreboot.org/c/coreboot/+/57208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a3183b1e1ecbb109258d6e076551158e0b40ce1 Gerrit-Change-Number: 57208 Gerrit-PatchSet: 5 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: skylake DDR4 boards: Set `CaVrefConfig` to 2
by Michael Niewöhner (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Felix Singer, Nico Huber, Frans Hendriks, Matt DeVillier, Angel Pons, Arthur Heymans, Patrick Rudolph, Wim Vervoorn. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57262 ) Change subject: skylake DDR4 boards: Set `CaVrefConfig` to 2 ...................................................................... Patch Set 2: (1 comment) File src/mainboard/kontron/bsl6/romstage.c: https://review.coreboot.org/c/coreboot/+/57262/comment/522e7168_046b8d66 PS2, Line 40: mem_cfg memory_params -- To view, visit https://review.coreboot.org/c/coreboot/+/57262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idab77daff311584b3e3061e9bf107c2fc1b7bdf1 Gerrit-Change-Number: 57262 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 16:43:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/device/Kconfig: introduce the AMD_DGPU_WITHOUT_EEPROM symbols
by Mike Banon (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Mike Banon. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57319 to look at the new patch set (#2). Change subject: src/device/Kconfig: introduce the AMD_DGPU_WITHOUT_EEPROM symbols ...................................................................... src/device/Kconfig: introduce the AMD_DGPU_WITHOUT_EEPROM symbols Some platforms like Lenovo G505S have the motherboard versions with the onboard AMD discrete GPU without its own dedicated EEPROM storage for VGA Option ROM. For such a discrete GPU to be usable with coreboot, the PCI init of GPUs has to be done differently. These AMD_DGPU_WITHOUT_EEPROM symbols can help for such cases. Change-Id: I424f93961c9d4a856dd6f5285417597cb117084d Signed-off-by: Mike Banon <mike.banon(a)3mdeb.com> --- M src/device/Kconfig 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/57319/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I424f93961c9d4a856dd6f5285417597cb117084d Gerrit-Change-Number: 57319 Gerrit-PatchSet: 2 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/device/Kconfig: introduce the AMD_DGPU_WITHOUT_EEPROM symbols
by Mike Banon (Code Review) 01 Sep '21

01 Sep '21

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57319 ) Change subject: src/device/Kconfig: introduce the AMD_DGPU_WITHOUT_EEPROM symbols ...................................................................... src/device/Kconfig: introduce the AMD_DGPU_WITHOUT_EEPROM symbols Some platforms like Lenovo G505S have the motherboard versions with the onboard AMD discrete GPU without its own dedicated EEPROM storage for VGA Option ROM. For such a discrete GPU to be usable with coreboot, the PCI init of GPUs has to be done differently. These AMD_DGPU_WITHOUT_EEPROM symbols can help for such cases. Change-Id: I424f93961c9d4a856dd6f5285417597cb117084d --- M src/device/Kconfig 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/57319/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index 5ae3466..3df5d79 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -58,6 +58,23 @@ Selected by mainboards that implement support for `libgfxinit`. Usually this requires a list of ports to be probed for displays. +config MAINBOARD_HAS_AMD_DGPU_WITHOUT_EEPROM + def_bool n + help + Selected by mainboards that have the onboard AMD discrete GPU + without its own dedicated EEPROM storage for VGA Option ROM. + +config AMD_DGPU_WITHOUT_EEPROM + def_bool n + prompt "AMD discrete GPU without EEPROM" + depends on MAINBOARD_HAS_AMD_DGPU_WITHOUT_EEPROM + help + Some platforms like Lenovo G505S have the motherboard versions + with the onboard AMD discrete GPU without its own dedicated EEPROM + storage for VGA Option ROM. For such a discrete GPU to be usable + with coreboot, the PCI initialization has to be done differently. + Enable this option if your motherboard has such a discrete GPU. + choice prompt "Graphics initialization" default NO_GFX_INIT if VGA_ROM_RUN_DEFAULT && PAYLOAD_SEABIOS -- To view, visit https://review.coreboot.org/c/coreboot/+/57319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I424f93961c9d4a856dd6f5285417597cb117084d Gerrit-Change-Number: 57319 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: set power limits dynamically for thermal
by EricR Lai (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Sumeet R Pawnikar, Patrick Rudolph, Karthik Ramasubramanian. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57035 ) Change subject: soc/intel/alderlake: set power limits dynamically for thermal ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/alderlake/systemagent.c: https://review.coreboot.org/c/coreboot/+/57035/comment/0fd78215_84919ff6 PS8, Line 74: sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF; > Halt might not be good option, as per flow we show below line 90 error message. If 0xFFFF we can skip the for loop. IDK, but PCI_DEVICE_ID shouldn't fail for SA ID? Tim, WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/57035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic331a3debb076ef08a312a31edc1468974fd4902 Gerrit-Change-Number: 57035 Gerrit-PatchSet: 8 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 16:03:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Create APIs for USB-C DP alternate mode support
by Zhuohao Lee (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Furquan Shaikh, Derek Huang, Brandon Breitenstein, Curtis Chen. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57139 ) Change subject: mb/google/volteer: Create APIs for USB-C DP alternate mode support ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: Tim/Furquan, do you have any comment for this patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/57139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e6dd952d3183ecb76de6d4887ee573ef89bb50 Gerrit-Change-Number: 57139 Gerrit-PatchSet: 9 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Curtis Chen <curtis.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 15:50:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Create APIs for USB-C DP alternate mode support
by Zhuohao Lee (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Derek Huang, Brandon Breitenstein, Curtis Chen. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57139 ) Change subject: mb/google/volteer: Create APIs for USB-C DP alternate mode support ...................................................................... Patch Set 9: (3 comments) File src/mainboard/google/volteer/mainboard.c: https://review.coreboot.org/c/coreboot/+/57139/comment/68c42052_b5763988 PS9, Line 155: if ((ret = google_chromeec_usb_get_pd_mux_info(port, &mux_flags)) < 0) Maybe can rephrase to: ret = google_chromeec_usb_get_pd_mux_info(port, &mux_flags); if ( ret != 0) { ... return ret; } https://review.coreboot.org/c/coreboot/+/57139/comment/1ae1bda4_d18f5d3f PS9, Line 161: /* If port is connected */ Do you mean the mux_flags is not empty then the port is connected? The mux_flags is used to return the mux_state, do you need to check the state to make sure the port is connected? File src/soc/intel/common/block/tcss/tcss.c: https://review.coreboot.org/c/coreboot/+/57139/comment/59b71f18_abace17e PS9, Line 296: WAIT_FOR_DISPLAYPORT_TIMEOUT If there are 3 typec ports and if the port 0, 1 don't connect the external display and port2 connects the external display, we will need around 3 * WAIT_FOR_DISPLAYPORT_TIMEOUT + WAIT_FOR_HPD_TIMEOUT = 6 second to light up the dev screen in the worst case right? -- To view, visit https://review.coreboot.org/c/coreboot/+/57139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e6dd952d3183ecb76de6d4887ee573ef89bb50 Gerrit-Change-Number: 57139 Gerrit-PatchSet: 9 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Curtis Chen <curtis.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 15:49:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit September 2021