coreboot-gerrit September 2021

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Change in coreboot[master]: mb/google/guybrush: If not using PCIe WWAN, disable the port
by build bot (Jenkins) (Code Review) 01 Sep '21

01 Sep '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57316 ) Change subject: mb/google/guybrush: If not using PCIe WWAN, disable the port ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/guybrush/port_descriptors.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127249): https://review.coreboot.org/c/coreboot/+/57316/comment/2267a1c8_7d20431d PS1, Line 191: if (variant_has_pcie_wwan()){ space required before the open brace '{' -- To view, visit https://review.coreboot.org/c/coreboot/+/57316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79c32e4814672c03ee0821786d5be1c77fd1b410 Gerrit-Change-Number: 57316 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Sep 2021 15:33:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Reorganize bootblock_mainboard_early_init()
by Martin Roth (Code Review) 01 Sep '21

01 Sep '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57318 ) Change subject: mb/google/guybrush: Reorganize bootblock_mainboard_early_init() ...................................................................... mb/google/guybrush: Reorganize bootblock_mainboard_early_init() This now skips all of the pieces done by PSP_verstage. BUG=None TEST=Boot Guybrush with & without PSP_verstage Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I5a6b8e2284e232c30c9f36ea7c6ab044e2644f7b --- M src/mainboard/google/guybrush/bootblock.c 1 file changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/57318/1 diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index dc5e046..cd27632 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -31,21 +31,6 @@ size_t base_num_gpios, override_num_gpios; const struct soc_amd_gpio *base_gpios, *override_gpios; - if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { - base_gpios = variant_early_gpio_table(&base_num_gpios); - override_gpios = variant_early_override_gpio_table(&override_num_gpios); - - gpio_configure_pads_with_override(base_gpios, base_num_gpios, - override_gpios, override_num_gpios); - - /* Set a timer to make sure there's enough delay for - * the Fibocom 350 PCIe init - */ - stopwatch_init_usecs_expire(&pcie_init_timeout_sw, FC350_PCIE_INIT_DELAY_US); - } - - printk(BIOS_DEBUG, "Bootblock configure eSPI\n"); - dword = pci_read_config32(SOC_LPC_DEV, 0x78); dword &= 0xFFFFF9F3; dword |= 0x200; @@ -53,6 +38,21 @@ pci_write_config32(SOC_LPC_DEV, 0x44, 0); pci_write_config32(SOC_LPC_DEV, 0x48, 0); + if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; + + base_gpios = variant_early_gpio_table(&base_num_gpios); + override_gpios = variant_early_override_gpio_table(&override_num_gpios); + + gpio_configure_pads_with_override(base_gpios, base_num_gpios, + override_gpios, override_num_gpios); + + /* Set a timer to make sure there's enough delay for + * the Fibocom 350 PCIe init + */ + stopwatch_init_usecs_expire(&pcie_init_timeout_sw, FC350_PCIE_INIT_DELAY_US); + printk(BIOS_DEBUG, "Bootblock configure eSPI\n"); + dword = pm_read32(0x90); dword |= 1 << 16; pm_write32(0x90, dword); -- To view, visit https://review.coreboot.org/c/coreboot/+/57318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a6b8e2284e232c30c9f36ea7c6ab044e2644f7b Gerrit-Change-Number: 57318 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Initialize WWAN GPIOs the same for PCI vs USB
by Martin Roth (Code Review) 01 Sep '21

01 Sep '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57317 ) Change subject: mb/google/guybrush: Initialize WWAN GPIOs the same for PCI vs USB ...................................................................... mb/google/guybrush: Initialize WWAN GPIOs the same for PCI vs USB Since the PCIE training for the WWAN PCIe port is no longer being run, we can initialize the GPIOs the same for all WWAN cards. BUG=b:193036827 TEST=Boot and reboot with fibocom FM350-GL & L850GL modules Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Idc9a7cb883fc8dd6bbc6077b8ea99182f17f888b --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/guybrush/gpio.c 2 files changed, 26 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/57317/1 diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 559a86d..50595cd 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -193,6 +193,12 @@ /* EN_PWR_WWAN_X */ PAD_GPO(GPIO_8, HIGH), +/* Put WWAN into reset */ + /* WWAN_RST_L */ + PAD_GPO(GPIO_24, LOW), + /* WWAN_DISABLE */ + PAD_GPO(GPIO_85, HIGH), + /* Enable ESPI, GSC Interrupt & I2C Communication */ /* GSC_SOC_INT_L */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), @@ -246,13 +252,13 @@ */ static const struct soc_amd_gpio bootblock_gpio_table[] = { - /* Enable WWAN & WLAN power, Deassert WWAN reset */ - /* EN_PWR_WWAN_X */ - PAD_GPO(GPIO_8, HIGH), + /* Enable WWAN, Deassert WWAN reset, keep WWAN PCIe Aux reset asserted */ /* WWAN_RST_L */ PAD_GPO(GPIO_24, HIGH), /* WWAN_DISABLE */ PAD_GPO(GPIO_85, LOW), + + /* Enable WLAN */ /* WLAN_DISABLE */ PAD_GPO(GPIO_130, LOW), }; @@ -264,14 +270,6 @@ /* PCIE_RST needs to be brought high before FSP-M runs */ static const struct soc_amd_gpio pcie_gpio_table[] = { - /* Allow WWAN power to be overridden by platform */ - /* EN_PWR_WWAN_X */ - PAD_GPO(GPIO_8, HIGH), - /* WWAN_RST_L */ - PAD_GPO(GPIO_24, HIGH), - /* WWAN_DISABLE */ - PAD_GPO(GPIO_85, LOW), - /* Deassert all AUX_RESET lines & PCIE_RST */ /* WWAN_AUX_RESET_L */ PAD_GPO(GPIO_18, HIGH), @@ -319,6 +317,7 @@ const struct soc_amd_gpio * __weak variant_early_override_gpio_table(size_t *size) { + /* Note that when overriding this, board ID & CBI is not available */ *size = 0; return NULL; } diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c index b6c8eec..85c2e60 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c +++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c @@ -8,7 +8,7 @@ #include <baseboard/variants.h> /* This table is used by guybrush variant with board version < 2. */ -static const struct soc_amd_gpio bid1_gpio_table[] = { +static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = { /* Unused TP183 */ PAD_NC(GPIO_31), /* EN_SPKR */ @@ -21,41 +21,25 @@ /* This table is used by guybrush variant with board version < 2. */ /* Use AUX Reset lines instead of PCIE_RST for Board Version 1 */ -static const struct soc_amd_gpio bid1_early_gpio_table[] = { +static const struct soc_amd_gpio override_early_gpio_table[] = { /* SD_AUX_RESET_L */ PAD_GPO(GPIO_70, LOW), }; /* This table is used by guybrush variant with board version < 2. */ static const struct soc_amd_gpio bid1_pcie_gpio_table[] = { - /* EN_PWR_WWAN_X */ - PAD_GPO(GPIO_8, LOW), - /* WWAN_RST_L */ - PAD_GPO(GPIO_24, LOW), - /* WWAN_DISABLE */ - PAD_GPO(GPIO_85, HIGH), /* SD_AUX_RESET_L */ PAD_GPO(GPIO_70, HIGH), }; -/* This table is used by guybrush variant with board version >= 2. */ -static const struct soc_amd_gpio bid2_pcie_gpio_table[] = { - /* EN_PWR_WWAN_X */ - PAD_GPO(GPIO_8, LOW), - /* WWAN_RST_L */ - PAD_GPO(GPIO_24, LOW), - /* WWAN_DISABLE */ - PAD_GPO(GPIO_85, HIGH), -}; - const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version = board_id(); *size = 0; if (board_version < 2) { - *size = ARRAY_SIZE(bid1_gpio_table); - return bid1_gpio_table; + *size = ARRAY_SIZE(bid1_ramstage_gpio_table); + return bid1_ramstage_gpio_table; } return NULL; @@ -63,27 +47,27 @@ const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size) { - uint32_t board_version = board_id(); - *size = 0; - - if (board_version < 2) { - *size = ARRAY_SIZE(bid1_early_gpio_table); - return bid1_early_gpio_table; - } - - return NULL; + /* + * This code is run before the EC is available to check the board ID + * since this is needed to work on Board ID 1 and is unused on other + * versions of guybrush, just enable it. + * + * Guybrush BID>1: Unused TP27; BID==1: SD_AUX_RESET_L + */ + *size = ARRAY_SIZE(override_early_gpio_table); + return override_early_gpio_table; } const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) { uint32_t board_version = board_id(); *size = 0; - if (board_version < 2) { *size = ARRAY_SIZE(bid1_pcie_gpio_table); return bid1_pcie_gpio_table; } + return NULL; +} - *size = ARRAY_SIZE(bid2_pcie_gpio_table); - return bid2_pcie_gpio_table; + } -- To view, visit https://review.coreboot.org/c/coreboot/+/57317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc9a7cb883fc8dd6bbc6077b8ea99182f17f888b Gerrit-Change-Number: 57317 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: If not using PCIe WWAN, disable the port
by Martin Roth (Code Review) 01 Sep '21

01 Sep '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57316 ) Change subject: mb/google/guybrush: If not using PCIe WWAN, disable the port ...................................................................... mb/google/guybrush: If not using PCIe WWAN, disable the port Check to see if the PCIe slot needs to be activated for the WWAN card. If it doesn't, leave it unused so it will be powered off and not do the PCIe training. BUG=b:193036827 TEST=Boot & Reboot guybrush with both PCIe & USB WWAN cards. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I79c32e4814672c03ee0821786d5be1c77fd1b410 --- M src/mainboard/google/guybrush/port_descriptors.c 1 file changed, 78 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/57316/1 diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index e1c78da..657a689 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -7,7 +7,7 @@ #include <types.h> /* All PCIe Resets are handled in coreboot */ -static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { +static const fsp_dxio_descriptor guybrush_czn_pci_wwan_descriptors[] = { { /* WLAN */ .engine_type = PCIE_ENGINE, .port_present = true, @@ -64,7 +64,7 @@ .clk_req = CLK_REQ3, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, - { /* TODO: remove this temporay workaround */ + { /* TODO: remove this temporary workaround */ .engine_type = PCIE_ENGINE, .port_present = true, .start_logical_lane = 8, @@ -75,7 +75,7 @@ .clk_req = CLK_REQ5, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, - { /* TODO: remove this temporay workaround */ + { /* TODO: remove this temporary workaround */ .engine_type = PCIE_ENGINE, .port_present = true, .start_logical_lane = 16, @@ -88,6 +88,73 @@ } }; +/* All PCIe Resets are handled in coreboot */ +static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { + { /* WLAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = PCI_SLOT(WLAN_DEVFN), + .function_number = PCI_FUNC(WLAN_DEVFN), + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* SD */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 1, + .end_logical_lane = 1, + .device_number = PCI_SLOT(SD_DEVFN), + .function_number = PCI_FUNC(SD_DEVFN), + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* NVME */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 4, + .end_logical_lane = 7, + .device_number = PCI_SLOT(NVME_DEVFN), + .function_number = PCI_FUNC(NVME_DEVFN), + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ3, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* TODO: remove this temporary workaround */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 8, + .end_logical_lane = 11, + .device_number = PCIE_GPP_BRIDGE_2_DEV, + .function_number = PCIE_GPP_2_4_FUNC, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ5, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* TODO: remove this temporary workaround */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 16, + .end_logical_lane = 23, + .device_number = PCIE_GPP_BRIDGE_1_DEV, + .function_number = PCIE_GPP_1_0_FUNC, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ6, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + } +}; /* TODO: verify the DDI table, since this is mostly an educated guess right now */ static const fsp_ddi_descriptor guybrush_czn_ddi_descriptors[] = { { /* DDI0 - eDP */ @@ -121,8 +188,14 @@ const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - *dxio_descs = guybrush_czn_dxio_descriptors; - *dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors); + if (variant_has_pcie_wwan()){ + *dxio_descs = guybrush_czn_pci_wwan_descriptors; + *dxio_num = ARRAY_SIZE(guybrush_czn_pci_wwan_descriptors); + + } else { + *dxio_descs = guybrush_czn_dxio_descriptors; + *dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors); + } *ddi_descs = guybrush_czn_ddi_descriptors; *ddi_num = ARRAY_SIZE(guybrush_czn_ddi_descriptors); } -- To view, visit https://review.coreboot.org/c/coreboot/+/57316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79c32e4814672c03ee0821786d5be1c77fd1b410 Gerrit-Change-Number: 57316 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Update PCIe WWAN path for WWAN PCIe check
by Martin Roth (Code Review) 01 Sep '21

01 Sep '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57315 ) Change subject: mb/google/guybrush: Update PCIe WWAN path for WWAN PCIe check ...................................................................... mb/google/guybrush: Update PCIe WWAN path for WWAN PCIe check variant_has_pcie_wwan() was always coming back as disabled because find_dev_nested_path() couldn't find the device until the domain was added to the array. BUG=b:193036827 TEST=Boot guybrush with PCIe & USB WWAN devices. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Id94fa0b0ff5c29fa447e869220d27ccfe61438c6 --- M src/mainboard/google/guybrush/variants/baseboard/helpers.c 1 file changed, 9 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/57315/1 diff --git a/src/mainboard/google/guybrush/variants/baseboard/helpers.c b/src/mainboard/google/guybrush/variants/baseboard/helpers.c index 5297a49..cde31c2 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/helpers.c +++ b/src/mainboard/google/guybrush/variants/baseboard/helpers.c @@ -34,11 +34,15 @@ __weak bool variant_has_pcie_wwan(void) { static const struct device_path pcie_wwan_path[] = { - { - .type = DEVICE_PATH_PCI, - .pci.devfn = PCIE_GPP_2_2_DEVFN, - }, - }; + { + .type = DEVICE_PATH_DOMAIN, + .domain.domain = 0x0, + }, + { + .type = DEVICE_PATH_PCI, + .pci.devfn = WWAN_DEVFN + }, +}; return variant_has_device_enabled(pcie_wwan_path, ARRAY_SIZE(pcie_wwan_path)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/57315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id94fa0b0ff5c29fa447e869220d27ccfe61438c6 Gerrit-Change-Number: 57315 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Move common Kconfig from mb Kconfig.name to Kconfig
by Subrata Banik (Code Review) 01 Sep '21

01 Sep '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57314 ) Change subject: mb/intel/adlrvp: Move common Kconfig from mb Kconfig.name to Kconfig ...................................................................... mb/intel/adlrvp: Move common Kconfig from mb Kconfig.name to Kconfig CONFIG_DRIVERS_INTEL_MIPI_CAMERA and CONFIG_SOC_INTEL_COMMON_BLOCK_IPU are getting selected for all ADLRVPs irrespective of ADL-P and ADL-M (internal and external EC SKUs) hence, selects those Kconfigs from mainboard Kconfig rather Kconfig.name. Also, select DRIVERS_INTEL_SOUNDWIRE as per alphabetical order. TEST=No changes are seen while the .config file is getting auto generated. Change-Id: I62d5ec19c3364da79ebe7287b1b3d6eb2a0efca0 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/Kconfig.name 2 files changed, 3 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/57314/1 diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index eed3b30..33e5e7b 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -9,15 +9,17 @@ select MAINBOARD_HAS_CHROMEOS select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC - select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_INTEL_DPTF + select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_INTEL_PMC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC + select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_USB_ACPI select DRIVERS_SPI_ACPI select SOC_INTEL_ALDERLAKE select SOC_INTEL_ALDERLAKE_PCH_M if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC select HAVE_SPD_IN_CBFS select DRIVERS_SOUNDWIRE_ALC711 + select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_CSE_LITE_SKU select DRIVERS_I2C_MAX98373 select FW_CONFIG if BOARD_INTEL_ADLRVP_M_EXT_EC diff --git a/src/mainboard/intel/adlrvp/Kconfig.name b/src/mainboard/intel/adlrvp/Kconfig.name index c53bab2..418ba12 100644 --- a/src/mainboard/intel/adlrvp/Kconfig.name +++ b/src/mainboard/intel/adlrvp/Kconfig.name @@ -2,26 +2,18 @@ bool "Alderlake-P RVP" select DRIVERS_UART_8250IO select MAINBOARD_USES_IFD_EC_REGION - select DRIVERS_INTEL_MIPI_CAMERA - select SOC_INTEL_COMMON_BLOCK_IPU config BOARD_INTEL_ADLRVP_P_EXT_EC bool "Alderlake-P RVP with Chrome EC" select INTEL_LPSS_UART_FOR_CONSOLE - select DRIVERS_INTEL_MIPI_CAMERA - select SOC_INTEL_COMMON_BLOCK_IPU config BOARD_INTEL_ADLRVP_M bool "Alderlake-M RVP" select DRIVERS_UART_8250IO select MAINBOARD_USES_IFD_EC_REGION - select DRIVERS_INTEL_MIPI_CAMERA - select SOC_INTEL_COMMON_BLOCK_IPU select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED config BOARD_INTEL_ADLRVP_M_EXT_EC bool "Alderlake-M RVP with Chrome EC" select INTEL_LPSS_UART_FOR_CONSOLE - select DRIVERS_INTEL_MIPI_CAMERA - select SOC_INTEL_COMMON_BLOCK_IPU select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED -- To view, visit https://review.coreboot.org/c/coreboot/+/57314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62d5ec19c3364da79ebe7287b1b3d6eb2a0efca0 Gerrit-Change-Number: 57314 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Doc/mb/ocp: Add hyperlink to src/mainboard/ocp/deltalake/vpd.h
by Felix Held (Code Review) 01 Sep '21

01 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57255 ) Change subject: Doc/mb/ocp: Add hyperlink to src/mainboard/ocp/deltalake/vpd.h ...................................................................... Doc/mb/ocp: Add hyperlink to src/mainboard/ocp/deltalake/vpd.h It would be easier for people to find the defined variables. Change-Id: I6d181f6602aa5d55019ea2110b2d8e1fa7e0159c Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57255 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> --- M Documentation/mainboard/ocp/deltalake.md 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jonathan Zhang: Looks good to me, approved diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md index b85f8ce..4510866 100644 --- a/Documentation/mainboard/ocp/deltalake.md +++ b/Documentation/mainboard/ocp/deltalake.md @@ -63,7 +63,7 @@ - systemboot_log_level: u-root package systemboot log levels, would be mapped to quiet/verbose in systemboot as that is all we have for now. 5 to 8 would be mapped to verbose, 0 to 4 and 9 would be mapped to quiet. -- VPDs affecting coreboot are listed/documented in src/mainboard/ocp/deltalake/vpd.h. +- VPDs affecting coreboot are listed/documented in [src/mainboard/ocp/deltalake/vpd.h]. ## Working features The solution is developed using LinuxBoot payload with Linux kernel 5.2.9, @@ -179,3 +179,4 @@ [All about u-root]: https://github.com/linuxboot/book/tree/master/u-root [u-root]: https://u-root.org/ [ChromeOS VPD]: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md +[src/mainboard/ocp/deltalake/vpd.h]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… -- To view, visit https://review.coreboot.org/c/coreboot/+/57255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d181f6602aa5d55019ea2110b2d8e1fa7e0159c Gerrit-Change-Number: 57255 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src/ec/google/chromeec: Add and modify APIs for USB-C DP ALT mode
by Zhuohao Lee (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Derek Huang, Brandon Breitenstein, Curtis Chen. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57138 ) Change subject: src/ec/google/chromeec: Add and modify APIs for USB-C DP ALT mode ...................................................................... Patch Set 5: Code-Review+1 (3 comments) Patchset: PS5: The overall is LGTM. Tim/Furquan, do you have any comment for this patch? File src/ec/google/chromeec/ec.h: https://review.coreboot.org/c/coreboot/+/57138/comment/58a9fc07_242dd6a0 PS5, Line 29: uint16_t svid, int port maybe can swap port and svid to align with the other api. ie: (int port, uint16_t svid) https://review.coreboot.org/c/coreboot/+/57138/comment/bb908c7e_d0b538d1 PS5, Line 39: long timeout, int port Maybe can swap the port and timeout, ie: (int port, long timeout) -- To view, visit https://review.coreboot.org/c/coreboot/+/57138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3 Gerrit-Change-Number: 57138 Gerrit-PatchSet: 5 Gerrit-Owner: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 15:19:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Fix Idle S0ix issue due to dynamic GPIO PM disabled
by Tim Wawrzynczak (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Meera Ravindranath. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56926 ) Change subject: mb/google/brya: Fix Idle S0ix issue due to dynamic GPIO PM disabled ...................................................................... Patch Set 7: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56926/comment/b5460552_28c90eda PS7, Line 9: GPIO PM was disabled for brya to evaluate if longer interrupt pulses : are required for ADL.Since ADL requires 4us long pulses(EDS:626817), : GPIO PM can be enabled.All devices currently tested on brya support 4us : long pulses.This change drops the GPIO PM override and : re-enables dynamic GPIO PM. : Spaces after periods and before `(` please -- To view, visit https://review.coreboot.org/c/coreboot/+/56926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c7b66b5514d8b80775ab7578ce7b12181af7882 Gerrit-Change-Number: 56926 Gerrit-PatchSet: 7 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 15:12:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Enable thermal control functionality for tpch
by Sumeet R Pawnikar (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57098 to look at the new patch set (#2). Change subject: mb/google/brya: Enable thermal control functionality for tpch ...................................................................... mb/google/brya: Enable thermal control functionality for tpch Enable thermal control functionality for tpch device on brya device. Change-Id: I6a35a101599bb811fcddaabab5296f8c6c12af31 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/57098/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a35a101599bb811fcddaabab5296f8c6c12af31 Gerrit-Change-Number: 57098 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit September 2021