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Taniya Das has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56588 )
Change subject: soc/qualcomm/common: clock: Add support for common clock driver
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
Hi Shelly, I have addressed few more changes which was missed in the last approved changes. Please help review again. Thanks.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: wifi: Add support for per-platform antenna gain
......................................................................
wifi: Add support for per-platform antenna gain
Add support for the PPAG ACPI BIOS configuration table as per the
connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
BUG=b:193665559
TEST=Generated SAR file with the PPAG related configuration values and
verified that the SSDT has the PPAG ACPI table.
Change-Id: Ie8d25113feeeb4a4242cfd7d72a5091d2d5fb389
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com>
---
M src/drivers/wifi/generic/acpi.c
M src/include/sar.h
M src/vendorcode/google/chromeos/sar.c
3 files changed, 90 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/57060/8
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56750
to look at the new patch set (#25).
Change subject: wifi: Add support for new revisions of SAR table entries
......................................................................
wifi: Add support for new revisions of SAR table entries
Existing SAR infrastructure supports only revision 0 of the SAR tables.
This patch modifies it to extend support for intel wifi 6 and wifi 6e
configurations as per the connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
The SAR table and WGDS configuration block sizes were static in the
legacy SAR file format. Following is the format of the new binary file.
+------------------------------------------------------------+
| Field | Size | Description |
+------------------------------------------------------------+
| Marker | 4 bytes | "$SAR" |
+------------------------------------------------------------+
| Version | 1 byte | Current version = 1 |
+------------------------------------------------------------+
| SAR table | 2 bytes | Offset of SAR table from start of |
| offset | | the header |
+------------------------------------------------------------+
| WGDS | 2 bytes | Offset of WGDS table from start of |
| offset | | the header |
+------------------------------------------------------------+
| Data | n bytes | Data for the different tables |
+------------------------------------------------------------+
This change supports both the legacy and the new format of SAR file
BUG=b:193665559
TEST=Checked the SSDT entries for WRDS, EWRD and WGDS with different
binaries generated by setting different versions in the config.star
Change-Id: I08c3f321938eba04e8bcff4d87cb215422715bb2
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com>
---
M src/drivers/wifi/generic/acpi.c
M src/include/sar.h
M src/vendorcode/google/chromeos/sar.c
3 files changed, 385 insertions(+), 136 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/56750/25
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#21).
Change subject: wifi: Add support for DSM methods for intel wifi card
......................................................................
wifi: Add support for DSM methods for intel wifi card
Add support for DSM methods as per the connectivity document
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
BUG=b:191720858
TEST=Check the generated SSDT tables for DSM methods
Change-Id: Ie154edf188531fe6c260274edaa694cf3b3605d3
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com>
---
M src/drivers/wifi/generic/acpi.c
M src/include/sar.h
M src/vendorcode/google/chromeos/sar.c
3 files changed, 164 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/56751/21
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57061
to look at the new patch set (#9).
Change subject: wifi: Add support for wifi time average SAR config
......................................................................
wifi: Add support for wifi time average SAR config
Add support for the WTAS ACPI BIOS configuration table as per the
connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
BUG=b:193665559
TEST=Generated SAR file with the WTAS related configuration values and
verified that the SSDT has the WTAS ACPI table.
Change-Id: I42cf3cba7974e6db0e05de30846ef103a15fd584
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com>
---
M src/drivers/wifi/generic/acpi.c
M src/include/sar.h
M src/vendorcode/google/chromeos/sar.c
3 files changed, 78 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/57061/9
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57025 )
Change subject: HACK: Herobrine: Reinit TPM INT gpio after qclib executes
......................................................................
Patch Set 4:
(2 comments)
File src/soc/qualcomm/common/qclib.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127230):
https://review.coreboot.org/c/coreboot/+/57025/comment/9f1bfb5a_0b4647a3
PS4, Line 220: mainboard_blob_fix();
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127230):
https://review.coreboot.org/c/coreboot/+/57025/comment/6947a0c7_a5184dcc
PS4, Line 220: mainboard_blob_fix();
please, no spaces at the start of a line
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Change subject: HACK: Herobrine: Reinit TPM INT GPIO
......................................................................
Patch Set 4:
(2 comments)
File src/mainboard/google/herobrine/mainboard.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127229):
https://review.coreboot.org/c/coreboot/+/57022/comment/711913c1_39da6c20
PS4, Line 52: mainboard_blob_fix();
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127229):
https://review.coreboot.org/c/coreboot/+/57022/comment/d8881fb2_40eb23e1
PS4, Line 52: mainboard_blob_fix();
please, no spaces at the start of a line
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