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Change subject: soc/intel/alderlake: [WIP]Trigger cse_fw_sync before DRAM Init
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/romstage/romstage.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127191):
https://review.coreboot.org/c/coreboot/+/55364/comment/7106c7aa_f97e7e2c
PS3, Line 140: if (!s3wake) {
braces {} are not necessary for single statement blocks
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Change subject: soc/tigerlake: Don't send CSE EOP if CSME is disabled
......................................................................
Patch Set 10:
This change is ready for review.
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Change subject: Added multiboot support to cbfstool and made changes to behaviour for cbfs add-payload
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
How can this be tested?
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Change subject: util/cbftool: Fix the bug in parsing Uefipayload with extended header
......................................................................
Patch Set 3:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57296/comment/6cddf87a_b7146ee8
PS3, Line 7: Fix the bug
Fix bug
https://review.coreboot.org/c/coreboot/+/57296/comment/6ca1d04c_659b6a9c
PS3, Line 7: cbftool
cbfstool
https://review.coreboot.org/c/coreboot/+/57296/comment/455d85c0_22a4c6e6
PS3, Line 7: Uefipayload
UefiPayload
https://review.coreboot.org/c/coreboot/+/57296/comment/baafd061_7421730c
PS3, Line 9: The patch is to fix "Not a usable UEFI firmware volume" issue when
: creating CBFS/flash image.
Is that documented somewhere? Please add a reference, or elaborate how to reproduce this. I am also curious, because a lot of people are using this, I think, and I have not heard about the problem yet.
https://review.coreboot.org/c/coreboot/+/57296/comment/563d7e9d_0ed806fa
PS3, Line 10: This issue is caused by adding FvNameGuid
: in UefiPayloadEntry.fdf in EDKII. There is an ext header between header
: of Fv and header of PayloadEntry in Fv with FvNameGuid. The ext header
: causes the UefiPayloadEntry to be found incorrectly when parsing Fv.
Is that a recent change in UefiPayload?
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Kyösti Mälkki, Swift Geek (Sebastian Grzywna),
I'd like you to reexamine a change. Please visit
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Change subject: arch/x86: Check unsupported CPU type while writing to SMBIOS table 7
......................................................................
arch/x86: Check unsupported CPU type while writing to SMBIOS table 7
Don't attempt to fill the SMBIOS table if the CPU doesn't support
deterministic cache CPUID.
TEST=Able to fix the hang issue seen on ASRock E350M1 with commit hash
e2b5fee.
Change-Id: Id65dc963e235f7080370a32cf69bcc4bee94d28f
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/arch/x86/smbios.c
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/57306/2
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Change subject: arch/x86: Skip returning default leaf value as `0`
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57305/comment/ea8907a4_f263eee2
PS1, Line 12: skip
> skips
Ack
https://review.coreboot.org/c/coreboot/+/57305/comment/0e79220c_e404af1b
PS1, Line 14:
> Please mention the hang on the ASRock E350M1, and also add a `Fixes:` tag.
Ack
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Change subject: arch/x86: Skip returning default leaf value as `0`
......................................................................
arch/x86: Skip returning default leaf value as `0`
`cpu_get_cache_info_leaf()` function is responsible to report leaf
value for CPU that have support for deterministic cache cpuid. As per
available datasheets from AMD and Intel the supported CPUID leaf are
0x8000_001d for AMD and 0x04 for Intel. Hence, this CL skips returning
default leaf value as `0`.
TEST=Able to fix the hang issue seen on ASRock E350M1 with commit hash
e2b5fee
Change-Id: Iee33b39298e7821ac5280d998172b58a70c8715b
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/arch/x86/cpu_common.c
1 file changed, 2 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/57305/2
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Change subject: amdfwtool: Remove some duplicate binaries/entries in PSP table
......................................................................
Patch Set 5:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57064/comment/96a39df4_7441ce53
PS5, Line 9: these
Which ones exactly?
https://review.coreboot.org/c/coreboot/+/57064/comment/3dfb4e75_4b71edfe
PS5, Line 12: goint
going
https://review.coreboot.org/c/coreboot/+/57064/comment/b36cb262_9d0ef8ca
PS5, Line 22: Issue
issue
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Change subject: amdfwtool: Detect the flag multilevel to decide the actual value
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57063/comment/971c6ffc_4e439207
PS4, Line 9: define
defined
https://review.coreboot.org/c/coreboot/+/57063/comment/049b0918_3622e78a
PS4, Line 12:
How much space is saved?
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Change subject: mb/google/brya/var/redrix: adjust uid for Maxim amp
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57208/comment/84de3672_a07c579d
PS1, Line 13:
> This is to consist with other 2 speakers configs, and m/c driver design. […]
Please mention that in the commit message.
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