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Change in coreboot[master]: [WIP] mb/hp: Add EliteBook 820 G2
by Iru Cai (vimacs) (Code Review) 05 Jun '23

05 Jun '23

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46630 to review the following change. Change subject: [WIP] mb/hp: Add EliteBook 820 G2 ...................................................................... [WIP] mb/hp: Add EliteBook 820 G2 Currently it boots to SeaBIOS. Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A src/mainboard/hp/820g2/Kconfig A src/mainboard/hp/820g2/Kconfig.name A src/mainboard/hp/820g2/Makefile.inc A src/mainboard/hp/820g2/acpi/ec.asl A src/mainboard/hp/820g2/acpi/superio.asl A src/mainboard/hp/820g2/acpi_tables.c A src/mainboard/hp/820g2/board_info.txt A src/mainboard/hp/820g2/devicetree.cb A src/mainboard/hp/820g2/dsdt.asl A src/mainboard/hp/820g2/gma-mainboard.ads A src/mainboard/hp/820g2/gpio.c A src/mainboard/hp/820g2/hda_verb.c A src/mainboard/hp/820g2/mainboard.c A src/mainboard/hp/820g2/pei_data.c A src/mainboard/hp/820g2/romstage.c 15 files changed, 444 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46630/1 diff --git a/src/mainboard/hp/820g2/Kconfig b/src/mainboard/hp/820g2/Kconfig new file mode 100644 index 0000000..f617551 --- /dev/null +++ b/src/mainboard/hp/820g2/Kconfig @@ -0,0 +1,34 @@ +if BOARD_HP_820_G2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select SOC_INTEL_BROADWELL + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default "hp/820g2" + +config MAINBOARD_PART_NUMBER + string + default "EliteBook 820 G2" + +config VGA_BIOS_FILE + string + default "pci8086,1616.rom" + +config VGA_BIOS_ID + string + default "8086,1616" + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/hp/820g2/Kconfig.name b/src/mainboard/hp/820g2/Kconfig.name new file mode 100644 index 0000000..3fcf1a1 --- /dev/null +++ b/src/mainboard/hp/820g2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_820_G2 + bool "EliteBook 820 G2" diff --git a/src/mainboard/hp/820g2/Makefile.inc b/src/mainboard/hp/820g2/Makefile.inc new file mode 100644 index 0000000..2543ee7 --- /dev/null +++ b/src/mainboard/hp/820g2/Makefile.inc @@ -0,0 +1,4 @@ +romstage-y += gpio.c +romstage-y += pei_data.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ramstage-y += pei_data.c diff --git a/src/mainboard/hp/820g2/acpi/ec.asl b/src/mainboard/hp/820g2/acpi/ec.asl new file mode 100644 index 0000000..d39c59a --- /dev/null +++ b/src/mainboard/hp/820g2/acpi/ec.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 6) +/* FIXME: EC support */ +} diff --git a/src/mainboard/hp/820g2/acpi/superio.asl b/src/mainboard/hp/820g2/acpi/superio.asl new file mode 100644 index 0000000..55b1db5 --- /dev/null +++ b/src/mainboard/hp/820g2/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/820g2/acpi_tables.c b/src/mainboard/hp/820g2/acpi_tables.c new file mode 100644 index 0000000..ca6f64b --- /dev/null +++ b/src/mainboard/hp/820g2/acpi_tables.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> +#include <arch/ioapic.h> +#include <soc/acpi.h> +#include <soc/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + acpi_init_gnvs(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + return acpi_madt_irq_overrides(current); +} diff --git a/src/mainboard/hp/820g2/board_info.txt b/src/mainboard/hp/820g2/board_info.txt new file mode 100644 index 0000000..db677c6 --- /dev/null +++ b/src/mainboard/hp/820g2/board_info.txt @@ -0,0 +1,2 @@ +Category: laptop +FIXME: put ROM package, ROM socketed, ROM protocol, Flashrom support, Release year diff --git a/src/mainboard/hp/820g2/devicetree.cb b/src/mainboard/hp/820g2/devicetree.cb new file mode 100644 index 0000000..57cf333 --- /dev/null +++ b/src/mainboard/hp/820g2/devicetree.cb @@ -0,0 +1,119 @@ +chip soc/intel/broadwell # FIXME: check these values + register "alt_gp_smi_en" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x000402e9" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpe0_en_1" = "0" + register "gpe0_en_2" = "0" + register "gpe0_en_3" = "0" + register "gpe0_en_4" = "0" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight_pwm_hz" = "200" + register "pcie_port_coalesce" = "1" + register "pcie_port_force_aspm" = "0" + register "sata_devslp_disable" = "0" + register "sata_devslp_mux" = "0" + register "sata_port0_gen3_dtle" = "0x0" + register "sata_port0_gen3_tx" = "0x0" + register "sata_port1_gen3_dtle" = "0x0" + register "sata_port1_gen3_tx" = "0x0" + register "sata_port2_gen3_dtle" = "0x0" + register "sata_port2_gen3_tx" = "0x0" + register "sata_port3_gen3_dtle" = "0x0" + register "sata_port3_gen3_tx" = "0x0" + register "sata_port_map" = "0xa" + register "sio_acpi_mode" = "0" + register "sio_i2c0_voltage" = "0" + register "sio_i2c1_voltage" = "0" + device cpu_cluster 0x0 on + device lapic 0x0 on + end + end + device domain 0x0 on + device pci 00.0 on # Host bridge + subsystemid 0x103c 0x225a + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x103c 0x225a + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x103c 0x225a + end + device pci 13.0 off # Smart Sound Audio DSP + end + device pci 14.0 on # xHCI Controller + subsystemid 0x103c 0x225a + end + device pci 15.0 off # Serial I/O DMA + end + device pci 15.1 off # I2C0 + end + device pci 15.2 off # I2C1 + end + device pci 15.3 off # GSPI0 + end + device pci 15.4 off # GSPI1 + end + device pci 15.5 off # UART0 + end + device pci 15.6 off # UART1 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x103c 0x225a + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 17.0 off # SDIO + end + device pci 19.0 on # Intel Gigabit Ethernet Unsupported PCI device 8086:15a2 + subsystemid 0x103c 0x225a + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x103c 0x225a + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x103c 0x225a + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x103c 0x225a + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 on # PCIe Port #4 + subsystemid 0x103c 0x225a + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x225a + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge + subsystemid 0x103c 0x225a + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x103c 0x225a + end + device pci 1f.3 on # SMBus + subsystemid 0x103c 0x225a + end + device pci 1f.6 off # Thermal + end + end +end diff --git a/src/mainboard/hp/820g2/dsdt.asl b/src/mainboard/hp/820g2/dsdt.asl new file mode 100644 index 0000000..666115d --- /dev/null +++ b/src/mainboard/hp/820g2/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <soc/intel/broadwell/acpi/platform.asl> + #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/broadwell/acpi/systemagent.asl> + #include <soc/intel/broadwell/acpi/pch.asl> + } +} diff --git a/src/mainboard/hp/820g2/gma-mainboard.ads b/src/mainboard/hp/820g2/gma-mainboard.ads new file mode 100644 index 0000000..7b90060 --- /dev/null +++ b/src/mainboard/hp/820g2/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + HDMI1, + HDMI2, + eDP); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/820g2/gpio.c b/src/mainboard/hp/820g2/gpio.c new file mode 100644 index 0000000..b4ef103 --- /dev/null +++ b/src/mainboard/hp/820g2/gpio.c @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> + +const struct gpio_config mainboard_gpio_config[] = { + [0] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [2] = PCH_GPIO_OUT_LOW, + [3] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [4] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [5] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [6] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [7] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [8] = PCH_GPIO_OUT_HIGH, + [9] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [10] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [11] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [12] = PCH_GPIO_NATIVE, + [13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [14] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [15] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [18] = PCH_GPIO_OUT_HIGH, + [19] = PCH_GPIO_NATIVE, + [20] = PCH_GPIO_NATIVE, + [21] = PCH_GPIO_NATIVE, + [22] = PCH_GPIO_NATIVE, + [23] = PCH_GPIO_NATIVE, + [24] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .reset = GPIO_RESET_RSMRST }, + [25] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = PCH_GPIO_OUT_HIGH, + [29] = PCH_GPIO_OUT_HIGH, + [30] = PCH_GPIO_NATIVE, + [31] = PCH_GPIO_NATIVE, + [32] = PCH_GPIO_NATIVE, + [33] = PCH_GPIO_NATIVE, + [34] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [35] = PCH_GPIO_NATIVE, + [36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [37] = PCH_GPIO_NATIVE, + [38] = PCH_GPIO_NATIVE, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [40] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [41] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [42] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [43] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [44] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [48] = PCH_GPIO_OUT_HIGH, + [49] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [50] = PCH_GPIO_OUT_HIGH, + [51] = PCH_GPIO_OUT_HIGH, + [52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [53] = PCH_GPIO_OUT_HIGH, + [54] = PCH_GPIO_OUT_HIGH, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .owner = GPIO_OWNER_GPIO, + .irqen = GPIO_IRQ_ENABLE, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = PCH_GPIO_OUT_HIGH, + [57] = PCH_GPIO_OUT_LOW, + [58] = PCH_GPIO_OUT_HIGH, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [60] = PCH_GPIO_OUT_HIGH, + [61] = PCH_GPIO_OUT_LOW, + [62] = PCH_GPIO_NATIVE, + [63] = PCH_GPIO_NATIVE, + [64] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [65] = PCH_GPIO_OUT_LOW, + [66] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [69] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [70] = PCH_GPIO_OUT_LOW, + [71] = PCH_GPIO_NATIVE, + [72] = PCH_GPIO_NATIVE, + [73] = PCH_GPIO_NATIVE, + [74] = PCH_GPIO_NATIVE, + [75] = PCH_GPIO_NATIVE, + [76] = PCH_GPIO_NATIVE, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [80] = PCH_GPIO_OUT_LOW, + [81] = PCH_GPIO_NATIVE, + [82] = PCH_GPIO_OUT_HIGH, + [83] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [84] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [85] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [87] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [88] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [89] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [90] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [93] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [94] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + PCH_GPIO_END +}; diff --git a/src/mainboard/hp/820g2/hda_verb.c b/src/mainboard/hp/820g2/hda_verb.c new file mode 100644 index 0000000..ed96b9f --- /dev/null +++ b/src/mainboard/hp/820g2/hda_verb.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x00000000, /* Codec Vendor / Device ID: */ + 0x00000000, /* Subsystem ID */ + 13, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0421101f), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x04a11020), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40748605), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/820g2/mainboard.c b/src/mainboard/hp/820g2/mainboard.c new file mode 100644 index 0000000..98cc811 --- /dev/null +++ b/src/mainboard/hp/820g2/mainboard.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/820g2/pei_data.c b/src/mainboard/hp/820g2/pei_data.c new file mode 100644 index 0000000..90c45f6 --- /dev/null +++ b/src/mainboard/hp/820g2/pei_data.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->ec_present = 1; + + /* FIXME: check this */ + pei_data->dimm_channel0_disabled = 2; + pei_data->dimm_channel1_disabled = 2; + pei_data->spd_addresses[0] = 0xa0; + pei_data->spd_addresses[2] = 0xa4; + pei_data->dq_pins_interleaved = 0; + + /* FIXME: USB2 ports */ + pei_data_usb2_port(pei_data, 0, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_DOCK); + pei_data_usb2_port(pei_data, 1, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 2, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 3, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + pei_data_usb2_port(pei_data, 4, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 5, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + + /* FIXME: USB3 ports */ + pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); +} diff --git a/src/mainboard/hp/820g2/romstage.c b/src/mainboard/hp/820g2/romstage.c new file mode 100644 index 0000000..8fc2f9e --- /dev/null +++ b/src/mainboard/hp/820g2/romstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include <soc/romstage.h> + +void mainboard_pre_raminit(struct romstage_params *rp) +{ + /* Fill out PEI DATA */ + mainboard_fill_pei_data(&rp->pei_data); +} + +void mainboard_post_raminit(struct romstage_params *rp) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Gerrit-Change-Number: 46630 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 27

Change in coreboot[master]: libgfxinit: Allow to configure screen rotation
by Nico Huber (Code Review) 05 Jun '23

05 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38922 ) Change subject: libgfxinit: Allow to configure screen rotation ...................................................................... libgfxinit: Allow to configure screen rotation This allows us to configure a default screen rotation in 90 degree steps. The framebuffer contents will then be displayed by the same amount in the other direction. The 90 and 270 degree settings are only supported by newer display engines, from Skylake / Apollo Lake on. Change-Id: Iac75cefbd34f28c55ec20ee152fe67351cc48653 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/device/Kconfig M src/drivers/intel/gma/hires_fb/gma-gfx_init.adb 2 files changed, 47 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/38922/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index a25bb91..6859c24 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -478,6 +478,27 @@ Set the maximum height of the framebuffer. This may help with default fonts too tiny for high-resolution displays. +choice DEFAULT_SCREEN_ROTATION + prompt "Default screen rotation" + depends on LINEAR_FRAMEBUFFER && MAINBOARD_USE_LIBGFXINIT + default DEFAULT_SCREEN_ROTATION_NONE + +config DEFAULT_SCREEN_ROTATION_NONE + bool "None" + +config DEFAULT_SCREEN_ROTATION_90 + bool "90 degrees CCW" + depends on GFX_GMA_GENERATION = "Broxton" || GFX_GMA_GENERATION = "Skylake" + +config DEFAULT_SCREEN_ROTATION_180 + bool "180 degrees" + +config DEFAULT_SCREEN_ROTATION_270 + bool "90 degrees CW" + depends on GFX_GMA_GENERATION = "Broxton" || GFX_GMA_GENERATION = "Skylake" + +endchoice + endmenu # "Display" config PCI diff --git a/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb index 1393784..014e92b 100644 --- a/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb +++ b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb @@ -54,9 +54,20 @@ ---------------------------------------------------------------------------- + procedure Screen_Rotation (rotation : out Rotation_Type) + is + begin + rotation := + (if Config.DEFAULT_SCREEN_ROTATION_90 then Rotated_90 + elsif Config.DEFAULT_SCREEN_ROTATION_180 then Rotated_180 + elsif Config.DEFAULT_SCREEN_ROTATION_270 then Rotated_270 + else No_Rotation); + end Screen_Rotation; + procedure gfxinit (lightup_ok : out Interfaces.C.int) is use type pos32; + use type word32; use type word64; ports : Port_List; @@ -84,10 +95,21 @@ end loop; fb := configs (Primary).Framebuffer; - fb.Width := Width_Type (min_h); - fb.Height := Height_Type (min_v); - fb.Stride := Div_Round_Up (fb.Width, 16) * 16; - fb.V_Stride := fb.Height; + Screen_Rotation (fb.Rotation); + + if fb.Rotation = Rotated_90 or fb.Rotation = Rotated_270 then + fb.Width := Width_Type (min_v); + fb.Height := Height_Type (min_h); + fb.Stride := Div_Round_Up (fb.Width, 32) * 32; + fb.V_Stride := Div_Round_Up (fb.Height, 32) * 32; + fb.Tiling := Y_Tiled; + fb.Offset := word32 (GTT_Rotation_Offset) * GTT_Page_Size; + else + fb.Width := Width_Type (min_h); + fb.Height := Height_Type (min_v); + fb.Stride := Div_Round_Up (fb.Width, 16) * 16; + fb.V_Stride := fb.Height; + end if; for i in Pipe_Index loop exit when configs (i).Port = Disabled; -- To view, visit https://review.coreboot.org/c/coreboot/+/38922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac75cefbd34f28c55ec20ee152fe67351cc48653 Gerrit-Change-Number: 38922 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 20

Change in coreboot[master]: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant
by Iru Cai (vimacs) (Code Review) 04 Jun '23

04 Jun '23

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39398 to review the following change. Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ...................................................................... mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A Documentation/mainboard/hp/8560w.md A Documentation/mainboard/hp/8560w_flash.webp M Documentation/mainboard/index.md M src/mainboard/hp/snb_ivb_laptops/Kconfig M src/mainboard/hp/snb_ivb_laptops/Kconfig.name A src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt A src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb 10 files changed, 477 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/39398/1 diff --git a/Documentation/mainboard/hp/8560w.md b/Documentation/mainboard/hp/8560w.md new file mode 100644 index 0000000..6a7c197 --- /dev/null +++ b/Documentation/mainboard/hp/8560w.md @@ -0,0 +1,82 @@ +# HP EliteBook 8560w + +This page describes how to run coreboot on the [HP EliteBook 8560w]. + +## Required proprietary blobs + +- Intel Firmware Descriptor, ME and GbE firmware +- EC: please read [EliteBook Series](elitebook_series) + +## Flashing instructions + +HP EliteBook 8560w has an 8MB SOIC-8 flash chip on the bottom of the +mainboard. You just need to remove the service cover, and use an SOIC-8 +clip to read and flash the chip. + +![8560w_chip_location](8560w_flash.webp) + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Model | MX25L6406E | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | no | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| In circuit flashing | yes | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +## Untested + +- mainboards with 4 memory slots + +## Working + +- i7-2720QM, 8G+8G +- Arch Linux boot from SeaBIOS payload +- EHCI debug: the port is beside the eSATA port +- SATA +- eSATA +- USB2 and USB3 +- keyboard +- Gigabit Ethernet +- WLAN +- WWAN +- VGA and DisplayPort +- audio +- EC ACPI +- Using `me_cleaner` +- dock: PS/2 keyboard, USB, DisplayPort +- TPM +- S3 suspend/resume + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | SMSC LPC47n217 | ++------------------+--------------------------------------------------+ +| EC | SMSC KBC1126 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[HP EliteBook 8560w]: https://support.hp.com/us-en/product/hp-elitebook-8560w-mobile-workstation/… diff --git a/Documentation/mainboard/hp/8560w_flash.webp b/Documentation/mainboard/hp/8560w_flash.webp new file mode 100644 index 0000000..b8295bc --- /dev/null +++ b/Documentation/mainboard/hp/8560w_flash.webp Binary files differ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index e46e0f3..a20a0bf 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -55,6 +55,7 @@ ### EliteBook series - [EliteBook common](hp/elitebook_series.md) +- [EliteBook 8560w](hp/8560w.md) - [EliteBook 8760w](hp/8760w.md) ## Intel diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig index d0105ff..0ec0d27 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig @@ -37,6 +37,7 @@ default "2760p" if BOARD_HP_2760P default "8460p" if BOARD_HP_8460P default "8470p" if BOARD_HP_8470P + default "8560w" if BOARD_HP_8560W default "8770w" if BOARD_HP_8770W default "folio_9470m" if BOARD_HP_FOLIO_9470M default "revolve_810_g1" if BOARD_HP_REVOLVE_810_G1 @@ -47,6 +48,7 @@ default "EliteBook 2760p" if BOARD_HP_2760P default "EliteBook 8460p" if BOARD_HP_8460P default "EliteBook 8470p" if BOARD_HP_8470P + default "EliteBook 8560w" if BOARD_HP_8560W default "EliteBook 8770w" if BOARD_HP_8770W default "EliteBook Folio 9470m" if BOARD_HP_FOLIO_9470M default "EliteBook Revolve 810 G1" if BOARD_HP_REVOLVE_810_G1 @@ -75,6 +77,7 @@ default 1 if BOARD_HP_2760P default 1 if BOARD_HP_8460P default 2 if BOARD_HP_8470P + default 1 if BOARD_HP_8560W default 2 if BOARD_HP_8770W default 0 if BOARD_HP_FOLIO_9470M default 2 if BOARD_HP_REVOLVE_810_G1 # FIXME: check this diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name index c4a8662..360373e 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name @@ -61,6 +61,17 @@ select SOUTHBRIDGE_INTEL_C216 select SUPERIO_SMSC_LPC47N217 +config BOARD_HP_8560W + bool "EliteBook 8560w" + + select BOARD_HP_SNB_IVB_LAPTOPS + select BOARD_ROMSIZE_KB_8192 + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_SMSC_LPC47N217 + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + config BOARD_HP_8770W bool "EliteBook 8770w" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt new file mode 100644 index 0000000..af1e296 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-elitebook-8560w-mobile-workstation/… +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c new file mode 100644 index 0000000..57eafe2 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/smsc/lpc47n217/lpc47n217.h> +#include <ec/hp/kbc1126/ec.h> + +#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* USB0 */ + { 1, 1, 0 }, /* USB1 */ + { 1, 1, 1 }, /* eSATA */ + { 1, 1, 1 }, /* camera */ + { 0, 0, 2 }, + { 1, 0, 2 }, /* bluetooth */ + { 0, 0, 3 }, + { 1, 0, 3 }, + { 0, 1, 4 }, + { 1, 1, 4 }, /* WWAN */ + { 1, 0, 5 }, + { 1, 0, 5 }, /* dock */ + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c new file mode 100644 index 0000000..29358aa --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c new file mode 100644 index 0000000..d7573d5 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c1631, /* Subsystem ID */ + + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c1631), + AZALIA_PIN_CFG(0, 0x0a, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0b, 0x0421401f), + AZALIA_PIN_CFG(0, 0x0c, 0x04a11020), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0x90a60130), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb new file mode 100644 index 0000000..d716b46 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb @@ -0,0 +1,60 @@ +# +# This file is part of the coreboot project. +# +# Copyright 2020 The coreboot project Authors. +# +# SPDX-License-Identifier: GPL-2.0-or-later +# + +chip northbridge/intel/sandybridge + device domain 0x0 on + subsystemid 0x103c 0x1631 inherit + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 off end # Internal graphics + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" + # HDD(0), ODD(1), eSATA(4) + register "sata_port_map" = "0x3b" + + device pci 1c.0 on end # PCIe Port #1, WWAN + device pci 1c.1 on end # PCIe Port #2, ExpressCard + device pci 1c.2 on end # PCIe Port #3, SD/MMC + device pci 1c.3 on end # PCIe Port #4, WLAN + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8, NEC USB 3.0 Host Controller + device pci 1f.0 on # LPC bridge + chip ec/hp/kbc1126 + register "ec_data_port" = "0x60" + register "ec_cmd_port" = "0x64" + register "ec_ctrl_reg" = "0xca" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end + chip superio/smsc/lpc47n217 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 off end # COM2 + end + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/39398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950 Gerrit-Change-Number: 39398 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: util: add a tool to dump and insert MEC1322 firmware
by Iru Cai (vimacs) (Code Review) 21 May '23

21 May '23

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41393 to review the following change. Change subject: util: add a tool to dump and insert MEC1322 firmware ...................................................................... util: add a tool to dump and insert MEC1322 firmware Refer to chip/mec1322/util/pack_ec.py in chromeec project for MEC1322 firmware format. Tested on the backup files of the system and private flashes of HP EliteBook 820 G1. This tool can dump the EC firmware from both flashes and insert the EC firmware to the original ROM file and make the ROM unchanged. It needs to be tested on real hardware to see if a modified ROM with a re-inserted EC firmware works. Change-Id: I999bf0289216bf72c4f8f19182c7670d7008b5f9 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/README.md A util/mec1322/Makefile A util/mec1322/mec1322.c 3 files changed, 324 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/41393/1 diff --git a/util/README.md b/util/README.md index 8b05f6f..672d1da 100644 --- a/util/README.md +++ b/util/README.md @@ -63,6 +63,7 @@ * __marvell__ - Add U-Boot boot loader for Marvell ARMADA38X `C` * __[me_cleaner](https://github.com/corna/me_cleaner)__ - Tool for partial deblobbing of Intel ME/TXE firmware images `Python` +* __mec1322__ - Dumps and inserts MEC1322 EC firmware `C` * __mma__ - Memory Margin Analysis automation tests `Bash` * __msrtool__ - Dumps chipset-specific MSR registers. `C` * __mtkheader__ - Generate MediaTek bootload header. `Python2` diff --git a/util/mec1322/Makefile b/util/mec1322/Makefile new file mode 100644 index 0000000..4ccbe92 --- /dev/null +++ b/util/mec1322/Makefile @@ -0,0 +1,21 @@ +## This file is part of the coreboot project. +## +## SPDX-License-Identifier: GPL-2.0-or-later + +obj = mec1322 +HOSTCC := $(if $(shell type gcc 2>/dev/null),gcc,cc) + +ifeq ($(VERIFY_SIG),1) + CFLAGS += -DVERIFY_SIG + LIBS := -lcrypto +endif + +all: $(obj) + +%: %.c + $(HOSTCC) $(CFLAGS) -Wall -o $@ $< $(LIBS) + +clean: + rm -f $(obj) + +.PHONY: all clean diff --git a/util/mec1322/mec1322.c b/util/mec1322/mec1322.c new file mode 100644 index 0000000..7ee83bb --- /dev/null +++ b/util/mec1322/mec1322.c @@ -0,0 +1,302 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <stdio.h> +#include <string.h> +#include <stdint.h> +#include <stdlib.h> + +#ifdef VERIFY_SIG +#include <openssl/obj_mac.h> +#include <openssl/rsa.h> +#include <openssl/sha.h> +#endif + +void usage(void) +{ + fprintf(stderr, + "Usage:\n" + "\tmec1322 dump [-s <flash size>] [-o <outfile>] <infile>\n" + "\tmec1322 insert [-s <flash size>] [-f <image>] <infile> <header_loc>\n"); + + exit(1); +} + +const int SPI_CLOCK_LIST[] = {48, 24, 12, 8}; +const uint8_t SPI_READ_CMD_LIST[] = {0x3, 0xb, 0x3b}; + +// FIXME: uint32_t cannot be used directly on big endian systems +struct mec1322_header { + uint8_t sig[6]; // "CSMS\0\0" + uint8_t spi_clk; + uint8_t spi_read_cmd; + uint32_t load_addr; + uint32_t entry_point; + uint16_t payload_blks; // payload_len >> 6 + uint8_t padding0[2]; + uint32_t payload_offset; + uint8_t padding1[8]; + uint8_t payload_key_exp[16]; // @0x20 + uint8_t payload_key_modulus[256]; // @0x30 +}; + +uint8_t crc8(const uint8_t *data, size_t len) +{ + const uint8_t CRC_TABLE[] = {0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, + 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d}; + uint8_t crc = 0; + for (size_t i = 0; i < len; i++) { + uint8_t v = data[i]; + crc = (crc << 4) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]); + crc = (crc << 4) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]); + } + return crc ^ 0x55; +} + +// return the total length of the firmware, including header, +// header_signature, and payload +// return 0 if there's error +size_t parse_header(const struct mec1322_header *hdr) +{ + if (memcmp(hdr->sig, "CSMS", 4) != 0) { + fprintf(stderr, "MEC1322 header signature error!\n"); + return 0; + } + + printf("SPI clock = %hhd MHz\n", SPI_CLOCK_LIST[hdr->spi_clk]); + printf("SPI read cmd = 0x%hhx\n", SPI_READ_CMD_LIST[hdr->spi_read_cmd]); + printf("load address = 0x%x\n", hdr->load_addr); + printf("entry point = 0x%x\n", hdr->entry_point); + size_t payload_len = (size_t)hdr->payload_blks * 64; + printf("payload length = 0x%lx\n", payload_len); + printf("payload offset = 0x%x\n", hdr->payload_offset); + return payload_len + hdr->payload_offset; +} + +int verify_payload_signature(const struct mec1322_header *hdr, void *payload, + const uint8_t *sig) +{ +#ifdef VERIFY_SIG + uint8_t hash[32]; + uint8_t sigrev[256]; + + for (size_t i = 0; i < 256; i++) + sigrev[i] = sig[255 - i]; + + RSA *rsa = RSA_new(); + BIGNUM *modulus = BN_lebin2bn(hdr->payload_key_modulus, 256, NULL); + BIGNUM *exp = BN_lebin2bn(hdr->payload_key_exp, 8, NULL); + RSA_set0_key(rsa, modulus, exp, NULL); + + SHA256(payload, (size_t)(hdr->payload_blks) * 64, hash); + + int v = RSA_verify(NID_sha256, hash, 32, sigrev, 256, rsa); + if (!v) + fprintf(stderr, "MEC1322 payload RSA signature error!\n"); + else + printf("MEC1322 payload RSA signature matches the payload.\n"); + + return v; +#else + fprintf(stderr, + "** MEC1322 payload signature verification is not enabled.\n" + "** You can run `make VERIFY_SIG=1` to enable it.\n"); + return 1; +#endif +} + +int mec1322_dump(int argc, char *argv[]) +{ + FILE *infile, *outfile = NULL; + long spisize = 0; + + while (argc > 2) { + if (strcmp(argv[0], "-s") == 0) { + spisize = strtol(argv[1], NULL, 0); + argc -= 2; + argv += 2; + continue; + } + if (strcmp(argv[0], "-o") == 0) { + outfile = fopen(argv[1], "w"); + if (outfile == NULL) { + fprintf(stderr, "Fail to open file %s!\n", argv[1]); + exit(1); + } + argc -= 2; + argv += 2; + continue; + } + // otherwise, print usage and exit + usage(); + } + + if (argc != 1) + usage(); + + // without the above options, it's the input file + infile = fopen(argv[0], "r"); + if (infile == NULL) { + fprintf(stderr, "Fail to open file %s!\n", argv[0]); + exit(1); + } + + if (spisize == 0) { + fseek(infile, -1, SEEK_END); + spisize = ftell(infile) + 1; + + printf("Input file size is 0x%lx.\n", spisize); + } + + // read MEC1322 firmware tag + fseek(infile, -256, SEEK_END); + uint8_t fwTag[4]; + uint32_t header_loc; + fread(fwTag, 1, 4, infile); + + if (crc8(fwTag, 3) == fwTag[3]) { + header_loc = (((uint32_t)fwTag[0]) << 8) | (((uint32_t)fwTag[1]) << 16) + | (((uint32_t)fwTag[2]) << 24); + printf("MEC1322 firmware header location is 0x%x.\n", header_loc); + } else { + fprintf(stderr, "MEC1322 tag CRC8 error!\n"); + return 1; + } + + // we use the distance of header_loc to end when seeking + struct mec1322_header hdr; + fseek(infile, header_loc - spisize, SEEK_END); + fread(&hdr, 1, sizeof(hdr), infile); + size_t fwlen = parse_header(&hdr); + if (fwlen == 0) { + fprintf(stderr, "Error parsing MEC1322 firmware header!\n"); + return 1; + } + + if (outfile) { + fseek(infile, header_loc - spisize, SEEK_END); + void *image = malloc(fwlen); + fread(image, 1, fwlen, infile); + fwrite(image, 1, fwlen, outfile); + + uint8_t rsasig[256]; + fread(rsasig, 1, 256, infile); + fwrite(rsasig, 1, 256, outfile); + + if (!verify_payload_signature(&hdr, image + hdr.payload_offset, rsasig)) + return 1; + + free(image); + fclose(outfile); + } + + fclose(infile); + return 0; +} + +int mec1322_insert(int argc, char *argv[]) +{ + FILE *infile, *ecfile = NULL; + void *image = NULL; + size_t fwlen; + long spisize = 0; + long header_loc; + + if (argc < 2) + usage(); + + while (argc > 2) { + if (strcmp(argv[0], "-s") == 0) { + spisize = strtol(argv[1], NULL, 0); + argc -= 2; + argv += 2; + continue; + } + if (strcmp(argv[0], "-f") == 0) { + ecfile = fopen(argv[1], "r"); + if (ecfile == NULL) { + fprintf(stderr, "Fail to open EC file %s!\n", argv[1]); + return 1; + } + argc -= 2; + argv += 2; + continue; + } + usage(); + } + + if (argc != 2) + usage(); + + infile = fopen(argv[0], "r+"); + header_loc = strtol(argv[1], NULL, 0); + + if (infile == NULL) { + fprintf(stderr, "Fail to open firmware image %s!\n", argv[1]); + return 1; + } + + if (spisize == 0) { + fseek(infile, -1, SEEK_END); + spisize = ftell(infile) + 1; + + printf("Input file size is 0x%lx.\n", spisize); + } + + if (ecfile != NULL) { + struct mec1322_header hdr; + fread(&hdr, 1, sizeof(hdr), ecfile); + fwlen = parse_header(&hdr); + + if (fwlen == 0) { + fprintf(stderr, "Error parsing MEC1322 firmware header!\n"); + return 1; + } + fseek(ecfile, 0, SEEK_SET); + size_t totallen = fwlen + 256; // firmware length with signature + image = malloc(totallen); + fread(image, 1, totallen, ecfile); + fclose(ecfile); + + if (!verify_payload_signature(&hdr, image + hdr.payload_offset, image + fwlen)) + return 1; + + fwlen = totallen; + } + + if (header_loc & 0xff) { + fprintf(stderr, "Header location should be aligned to 256 bytes!\n"); + return 1; + } + uint8_t fwTag[4] = {header_loc >> 8, header_loc >> 16, header_loc >> 24}; + fwTag[3] = crc8(fwTag, 3); + + // write tag + fseek(infile, -256, SEEK_END); + fwrite(fwTag, 1, 4, infile); + + // if EC image is given, write EC image + if (image) { + fseek(infile, header_loc - spisize, SEEK_END); + fwrite(image, 1, fwlen, infile); + free(image); + } + + fclose(infile); + + return 0; +} + +int main(int argc, char *argv[]) +{ + if (argc < 3) + usage(); + + if (strcmp(argv[1], "dump") == 0) + return mec1322_dump(argc - 2, argv + 2); + + if (strcmp(argv[1], "insert") == 0) + return mec1322_insert(argc - 2, argv + 2); + + // no action provided + usage(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I999bf0289216bf72c4f8f19182c7670d7008b5f9 Gerrit-Change-Number: 41393 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

5 13

Change in coreboot[master]: [WIP] mb/hp: Add HP ProBook 640 G1
by Iru Cai (vimacs) (Code Review) 21 May '23

21 May '23

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46130 to review the following change. Change subject: [WIP] mb/hp: Add HP ProBook 640 G1 ...................................................................... [WIP] mb/hp: Add HP ProBook 640 G1 Generate code from autoport. It boots to Arch Linux in a USB disk from SeaBIOS payload. EC ACPI doesn't work yet. This board doesn't have HP Sure Start enabled, so we can use all the flash regions, and relocate the EC firmware with CB:41393. Change-Id: I07f433784292e3765bde3736414ff0eae525a046 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A Documentation/mainboard/hp/640g1.md A src/mainboard/hp/probook_640_g1/Kconfig A src/mainboard/hp/probook_640_g1/Kconfig.name A src/mainboard/hp/probook_640_g1/Makefile.inc A src/mainboard/hp/probook_640_g1/acpi/ec.asl A src/mainboard/hp/probook_640_g1/acpi/platform.asl A src/mainboard/hp/probook_640_g1/acpi/superio.asl A src/mainboard/hp/probook_640_g1/acpi_tables.c A src/mainboard/hp/probook_640_g1/board_info.txt A src/mainboard/hp/probook_640_g1/bootblock.c A src/mainboard/hp/probook_640_g1/devicetree.cb A src/mainboard/hp/probook_640_g1/dsdt.asl A src/mainboard/hp/probook_640_g1/gma-mainboard.ads A src/mainboard/hp/probook_640_g1/gpio.c A src/mainboard/hp/probook_640_g1/hda_verb.c A src/mainboard/hp/probook_640_g1/mainboard.c A src/mainboard/hp/probook_640_g1/romstage.c 17 files changed, 635 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46130/1 diff --git a/Documentation/mainboard/hp/640g1.md b/Documentation/mainboard/hp/640g1.md new file mode 100644 index 0000000..048633f --- /dev/null +++ b/Documentation/mainboard/hp/640g1.md @@ -0,0 +1,65 @@ +# HP ProBook 640 G1 + +This page is about the notebook [HP ProBook 640 G1]. + +## Release status + +(TBD) + +## Required proprietary blobs + +The following blobs are required to operate the hardware: + +1. EC firmware +2. Intel ME firmware +3. mrc.bin + +HP EliteBook Folio 9480m uses SMSC MEC1322 as its embedded controller. +The EC firmware is stored in the flash chip. We can extract the EC firmware from +the OEM firmware, and insert it in the coreboot image. + +Intel ME firmware is in the flash chip. It is not needed when building coreboot. + +The Haswell memory reference code binary is needed when building coreboot. +Please see [mrc.bin](../../northbridge/intel/haswell/mrc.bin). + +## Programming + +(TBD) + +## Debugging + +The serial port on dock can be used to debug the laptop. + +## Test status + +### Known issues + +(TBD) + +- EC ACPI is not working yet. + +### Untested + +(TBD) + +### Working + +(TBD) + +## Technology + +```eval_rst ++------------------+-----------------------------+ +| CPU | Intel Haswell (FCPGA946) | ++------------------+-----------------------------+ +| PCH | Intel Lynx Point HM87 | ++------------------+-----------------------------+ +| EC | SMSC MEC1322 | ++------------------+-----------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+-----------------------------+ +``` + +[HP ProBook 640 G1]: https://support.hp.com/us-en/product/hp-probook-640-g1-notebook-pc/5405392/ +[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c04823617 diff --git a/src/mainboard/hp/probook_640_g1/Kconfig b/src/mainboard/hp/probook_640_g1/Kconfig new file mode 100644 index 0000000..d23a3fb --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/Kconfig @@ -0,0 +1,42 @@ +if BOARD_HP_PROBOOK_640_G1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select EC_HP_KBC1126 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_SMSC_LPC47N217 + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default "hp/probook_640_g1" + +config MAINBOARD_PART_NUMBER + string + default "HP ProBook 640 G1" + +config VGA_BIOS_FILE + string + default "pci8086,0416.rom" + +config VGA_BIOS_ID + string + default "8086,0416" + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 + +config EC_HP_KBC1126_ECFW_IN_CBFS + bool + default n + +endif diff --git a/src/mainboard/hp/probook_640_g1/Kconfig.name b/src/mainboard/hp/probook_640_g1/Kconfig.name new file mode 100644 index 0000000..f809069 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_PROBOOK_640_G1 + bool "ProBook 640 G1" diff --git a/src/mainboard/hp/probook_640_g1/Makefile.inc b/src/mainboard/hp/probook_640_g1/Makefile.inc new file mode 100644 index 0000000..fa23791 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += bootblock.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/probook_640_g1/acpi/ec.asl b/src/mainboard/hp/probook_640_g1/acpi/ec.asl new file mode 100644 index 0000000..ab3a35c --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/hp/kbc1126/acpi/ec.asl> \ No newline at end of file diff --git a/src/mainboard/hp/probook_640_g1/acpi/platform.asl b/src/mainboard/hp/probook_640_g1/acpi/platform.asl new file mode 100644 index 0000000..8023ae8 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/acpi/platform.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + \_SB.PCI0.LPCB.EC0.ACPI = 1 + \_SB.PCI0.LPCB.EC0.SLPT = 0 + + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC0.SLPT = Arg0 +} diff --git a/src/mainboard/hp/probook_640_g1/acpi/superio.asl b/src/mainboard/hp/probook_640_g1/acpi/superio.asl new file mode 100644 index 0000000..55b1db5 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/probook_640_g1/acpi_tables.c b/src/mainboard/hp/probook_640_g1/acpi_tables.c new file mode 100644 index 0000000..f9ac854 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/acpi_tables.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/lynxpoint/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/probook_640_g1/board_info.txt b/src/mainboard/hp/probook_640_g1/board_info.txt new file mode 100644 index 0000000..28b9c2f --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/board_info.txt @@ -0,0 +1,5 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +FIXME: put ROM package, ROM socketed, Release year +Board URL: https://support.hp.com/us-en/product/hp-probook-640-g1-notebook-pc/5405392/ diff --git a/src/mainboard/hp/probook_640_g1/bootblock.c b/src/mainboard/hp/probook_640_g1/bootblock.c new file mode 100644 index 0000000..b5b6d43 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/bootblock.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/pch.h> +#include <superio/smsc/lpc47n217/lpc47n217.h> +#include <ec/hp/kbc1126/ec.h> + +#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) + +void mainboard_config_superio(void) +{ + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); +} diff --git a/src/mainboard/hp/probook_640_g1/devicetree.cb b/src/mainboard/hp/probook_640_g1/devicetree.cb new file mode 100644 index 0000000..4056b9d --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/devicetree.cb @@ -0,0 +1,88 @@ +chip northbridge/intel/haswell # FIXME: check ec_present, dq_pins_interleaved, usb_xhci_on_resume, gfx + register "dq_pins_interleaved" = "false" + register "ec_present" = "true" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight_pwm_hz" = "200" + register "usb_xhci_on_resume" = "false" + device cpu_cluster 0x0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x103c 0x1993 inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "docking_supported" = "1" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "sata_ahci" = "1" + register "sata_port0_gen3_dtle" = "0x7" + # 0(HDD), 1(ODD), 5(M.2) + register "sata_port_map" = "0x37" + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7, WLAN + device pci 1c.7 on end # PCIe Port #8, Card Reader + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip ec/hp/kbc1126 + register "ec_data_port" = "0x62" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" + register "ec_fan_ctrl_value" = "0x5f" + device pnp ff.1 off end + end + chip superio/smsc/lpc47n217 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 off end # COM2 + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/hp/probook_640_g1/dsdt.asl b/src/mainboard/hp/probook_640_g1/dsdt.asl new file mode 100644 index 0000000..769d907 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/dsdt.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/hp/probook_640_g1/gma-mainboard.ads b/src/mainboard/hp/probook_640_g1/gma-mainboard.ads new file mode 100644 index 0000000..a6af0ac --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/gma-mainboard.ads @@ -0,0 +1,23 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/probook_640_g1/gpio.c b/src/mainboard/hp/probook_640_g1/gpio.c new file mode 100644 index 0000000..629117a --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/gpio.c @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio2 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio9 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio19 = GPIO_INVERT, + .gpio21 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/probook_640_g1/hda_verb.c b/src/mainboard/hp/probook_640_g1/hda_verb.c new file mode 100644 index 0000000..5c0f943 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x00000000, /* Codec Vendor / Device ID: */ + 0x00000000, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x00000000), + AZALIA_PIN_CFG(0, 0x0a, 0x21011030), + AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), + AZALIA_PIN_CFG(0, 0x0c, 0x03a11020), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x2181102e), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0xd5a30140), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/probook_640_g1/mainboard.c b/src/mainboard/hp/probook_640_g1/mainboard.c new file mode 100644 index 0000000..3f023d0 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/mainboard.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/probook_640_g1/romstage.c b/src/mainboard/hp/probook_640_g1/romstage.c new file mode 100644 index 0000000..63c2fb8 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/romstage.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQF, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQB, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQB, PIRQC, PIRQD); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} + +void mb_get_spd_map(uint8_t spd_map[4]) +{ + spd_map[0] = 0xa0; + spd_map[2] = 0xa2; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, /* dock */ + { 0x0080, 1, 0, USB_PORT_BACK_PANEL }, /* right */ + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, /* right */ + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, /* left */ + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0080, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 3, USB_PORT_BACK_PANEL }, /* webcam */ + { 0x0080, 1, 3, USB_PORT_DOCK }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, /* left */ + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 5, USB_PORT_BACK_PANEL }, /* M.2 */ + { 0x0110, 1, 5, USB_PORT_BACK_PANEL }, /* WLAN */ + { 0x0110, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0080, 1, 6, USB_PORT_DOCK }, + }; + struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 0, 2 }, + }; + memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); + memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07f433784292e3765bde3736414ff0eae525a046 Gerrit-Change-Number: 46130 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: drivers/intel/gma: Move IGD OpRegion to CBMEM
by Nico Huber (Code Review) 18 May '23

18 May '23

Hello Matt DeVillier, Angel Pons, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40724 to review the following change. Change subject: drivers/intel/gma: Move IGD OpRegion to CBMEM ...................................................................... drivers/intel/gma: Move IGD OpRegion to CBMEM It never was in GNVS, it never belonged among the ACPI tables. Having it in CBMEM, makes it easy to look the location up on resume, and saves us additional boilerplate. Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/drivers/intel/gma/opregion.c M src/drivers/intel/gma/opregion.h M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/x4x/gma.c M src/soc/intel/apollolake/graphics.c M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/baytrail/gfx.c M src/soc/intel/baytrail/include/soc/nvs.h M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/acpi/globalnvs.asl M src/soc/intel/braswell/gfx.c M src/soc/intel/braswell/include/soc/nvs.h M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/igd.c M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/cannonlake/graphics.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/graphics.h M src/soc/intel/icelake/graphics.c M src/soc/intel/jasperlake/graphics.c M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/graphics.c M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/tigerlake/graphics.c M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/nvs.h M src/southbridge/intel/i82801dx/nvs.h M src/southbridge/intel/i82801gx/acpi/globalnvs.asl M src/southbridge/intel/i82801gx/nvs.h M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/nvs.h M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/nvs.h M src/southbridge/intel/ibexpeak/nvs.h M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/nvs.h 41 files changed, 82 insertions(+), 1,236 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/40724/1 diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 56449d0..764af46 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -69,7 +69,7 @@ } /* Write ASLS PCI register and prepare SWSCI register. */ -void intel_gma_opregion_register(uintptr_t opregion) +static void intel_gma_opregion_register(uintptr_t opregion) { struct device *igd; u16 reg16; @@ -106,17 +106,16 @@ } /* Restore ASLS register on S3 resume and prepare SWSCI. */ -void intel_gma_restore_opregion(void) +static enum cb_err intel_gma_restore_opregion(void) { - if (acpi_is_wakeup_s3()) { - const void *const gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - uintptr_t aslb; - - if (gnvs && (aslb = gma_get_gnvs_aslb(gnvs))) - intel_gma_opregion_register(aslb); - else - printk(BIOS_ERR, "Error: GNVS or ASLB not set.\n"); + const igd_opregion_t *const opregion = cbmem_find(CBMEM_ID_IGD_OPREGION); + if (!opregion) { + printk(BIOS_ERR, "GMA: Failed to find IGD OpRegion.\n"); + return CB_ERR; } + /* Write ASLS PCI register and prepare SWSCI register. */ + intel_gma_opregion_register((uintptr_t)opregion); + return CB_SUCCESS; } static enum cb_err vbt_validate(struct region_device *rdev) @@ -236,14 +235,17 @@ } /* Initialize IGD OpRegion, called from ACPI code and OS drivers */ -enum cb_err -intel_gma_init_igd_opregion(igd_opregion_t *opregion) +enum cb_err intel_gma_init_igd_opregion(void) { + igd_opregion_t *opregion; struct region_device rdev; optionrom_vbt_t *vbt = NULL; optionrom_vbt_t *ext_vbt; bool found = false; + if (acpi_is_wakeup_s3()) + return intel_gma_restore_opregion(); + /* Search for vbt.bin in CBFS. */ if (locate_vbt_cbfs(&rdev) == CB_SUCCESS && vbt_validate(&rdev) == CB_SUCCESS) { @@ -285,6 +287,12 @@ return CB_ERR; } + opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof(*opregion)); + if (!opregion) { + printk(BIOS_ERR, "GMA: Failed to add IGD OpRegion to CBMEM.\n"); + return CB_ERR; + } + memset(opregion, 0, sizeof(igd_opregion_t)); memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h index 4967691..69c7bc2 100644 --- a/src/drivers/intel/gma/opregion.h +++ b/src/drivers/intel/gma/opregion.h @@ -243,11 +243,7 @@ u8 coreblock_biossignon[155]; } __packed optionrom_vbt_t; -void intel_gma_opregion_register(uintptr_t opregion); -void intel_gma_restore_opregion(void); -uintptr_t gma_get_gnvs_aslb(const void *gnvs); -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb); -enum cb_err intel_gma_init_igd_opregion(igd_opregion_t *opregion); +enum cb_err intel_gma_init_igd_opregion(void); /* * Returns the CBFS filename of the VBT blob. diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 25f7518..a517622 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -32,19 +32,6 @@ write32(res2mmio(gtt_res, reg, 0), data); } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static u32 get_cdclk(struct device *const dev) { const u16 cdclk_sel = @@ -205,7 +192,7 @@ } } - intel_gma_restore_opregion(); + intel_gma_init_igd_opregion(); } static void gma_generate_ssdt(struct device *device) @@ -215,32 +202,6 @@ drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long -gma_write_acpi_tables(struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static const char *gma_acpi_name(const struct device *dev) { return "GFX0"; @@ -258,7 +219,6 @@ .init = gma_func0_init, .ops_pci = &gma_pci_ops, .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index c6b8fab..f00f8a7 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -210,19 +210,6 @@ return 0; } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void power_well_enable(void) { gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE); @@ -510,7 +497,7 @@ gma_pm_init_post_vbios(dev); gma_enable_swsci(); - intel_gma_restore_opregion(); + intel_gma_init_igd_opregion(); } static void gma_generate_ssdt(struct device *dev) @@ -520,30 +507,6 @@ drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static struct pci_operations gma_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; @@ -555,7 +518,6 @@ .init = gma_func0_init, .acpi_fill_ssdt = gma_generate_ssdt, .ops_pci = &gma_pci_ops, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 8a19b3e..794267c 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -44,19 +44,6 @@ #define DEFAULT_BLC_PWM 180 -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static int gtt_setup(u8 *mmiobase) { unsigned long PGETBL_save; @@ -709,7 +696,7 @@ pci_dev_init(dev); } - intel_gma_restore_opregion(); + intel_gma_init_igd_opregion(); } /* This doesn't reclaim stolen UMA memory, but IGD could still @@ -764,32 +751,6 @@ pci_dev_read_resources(dev); } -static unsigned long -gma_write_acpi_tables(struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static const char *gma_acpi_name(const struct device *dev) { return "GFX0"; @@ -808,7 +769,6 @@ .disable = gma_func0_disable, .ops_pci = &gma_pci_ops, .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, }; diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index c8bbbfd..49068b1 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -65,19 +65,6 @@ return 0; } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void gma_pm_init_post_vbios(struct device *dev) { struct northbridge_intel_ironlake_config *conf = dev->chip_info; @@ -181,7 +168,7 @@ gma_pm_init_post_vbios(dev); gma_enable_swsci(); - intel_gma_restore_opregion(); + intel_gma_init_igd_opregion(); } static void gma_read_resources(struct device *dev) @@ -210,32 +197,6 @@ drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long -gma_write_acpi_tables(struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static struct pci_operations gma_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; @@ -247,7 +208,6 @@ .acpi_fill_ssdt = gma_generate_ssdt, .init = gma_func0_init, .ops_pci = &gma_pci_ops, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index d398b55..0d4e34d 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -43,19 +43,6 @@ static struct resource *gtt_res = NULL; static struct resource *mmio_res = NULL; -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static int gtt_setup(u8 *mmiobase) { u32 gttbase; @@ -275,31 +262,7 @@ generate_fake_intel_oprom(&conf->gfx, dev, "$VBT PINEVIEW"); } - intel_gma_restore_opregion(); -} - -static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; + intel_gma_init_igd_opregion(); } static const char *gma_acpi_name(const struct device *dev) @@ -318,7 +281,6 @@ .init = gma_func0_init, .ops_pci = &gma_pci_ops, .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 5c4f548..7a7a767 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -303,19 +303,6 @@ return 0; } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void gma_pm_init_pre_vbios(struct device *dev) { u32 reg32; @@ -637,7 +624,7 @@ } gma_enable_swsci(); - intel_gma_restore_opregion(); + intel_gma_init_igd_opregion(); } static void gma_generate_ssdt(struct device *device) @@ -647,30 +634,6 @@ drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static const char *gma_acpi_name(const struct device *dev) { return "GFX0"; @@ -702,7 +665,6 @@ .disable = gma_func0_disable, .ops_pci = &gma_pci_ops, .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index f5335ec..133008a 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -28,19 +28,6 @@ #define BASE_FREQUENCY 96000 -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void gma_func0_init(struct device *dev) { u32 reg32; @@ -67,7 +54,7 @@ pci_dev_init(dev); } - intel_gma_restore_opregion(); + intel_gma_init_igd_opregion(); } static void gma_func0_disable(struct device *dev) @@ -87,32 +74,6 @@ drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long -gma_write_acpi_tables(struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static const char *gma_acpi_name(const struct device *dev) { return "GFX0"; @@ -131,7 +92,6 @@ .ops_pci = &gma_pci_ops, .disable = gma_func0_disable, .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 033b300..36e0a26 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -50,21 +50,6 @@ /* Initialize PCI device, load/execute BIOS Option ROM */ pci_dev_init(dev); } -} -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - /* FIXME: Add platform specific mailbox initialization */ - - current += sizeof(igd_opregion_t); - return acpi_align_current(current); + intel_gma_init_igd_opregion(); } diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index 4aa600f..83d7f46 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -54,48 +54,6 @@ TOLM, 32, // 0x34 - Top of Low Memory CBMC, 32, // 0x38 - coreboot mem console pointer - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native PCIe support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support - /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 64c9061..9b9679f 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -353,19 +353,6 @@ } } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void gfx_init(struct device *dev) { /* Pre VBIOS Init */ @@ -382,8 +369,7 @@ /* Post VBIOS Init */ gfx_post_vbios_init(dev); - /* Restore opregion on S3 resume */ - intel_gma_restore_opregion(); + intel_gma_init_igd_opregion(); } static void gma_generate_ssdt(struct device *dev) @@ -393,39 +379,12 @@ drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long -gma_write_acpi_tables(struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static struct device_operations gfx_device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gfx_init, .ops_pci = &soc_pci_ops, - .write_acpi_tables = gma_write_acpi_tables, .acpi_fill_ssdt = gma_generate_ssdt, }; diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index df81573..e7c64b9 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -47,40 +47,7 @@ u32 cbmc; /* 0x38 - coreboot memconsole */ u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */ - /* IGD OpRegion */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - - u8 unused[11]; + u8 unused[76]; /* ChromeOS specific (0x100-0xfff)*/ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 1e6cea2..2bcc873 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -461,14 +461,6 @@ return current; } -/* Initialize IGD OpRegion, called from ACPI code */ -static int update_igd_opregion(igd_opregion_t *opregion) -{ - /* FIXME: Add platform specific mailbox initialization */ - - return 0; -} - unsigned long southcluster_write_acpi_tables(struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { @@ -480,19 +472,6 @@ current = acpi_align_current(current); } - if (CONFIG(INTEL_GMA_ADD_VBT)) { - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - intel_gma_init_igd_opregion(opregion); - if (gnvs) - gnvs->aslb = (u32)opregion; - update_igd_opregion(opregion); - current += sizeof(igd_opregion_t); - current = acpi_align_current(current); - } - ssdt2 = (acpi_header_t *)current; memset(ssdt2, 0, sizeof(acpi_header_t)); acpi_create_serialio_ssdt(ssdt2); diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index 860f4d7..4f6ed90 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -56,48 +56,6 @@ TOLM, 32, /* 0x34 - Top of Low Memory */ CBMC, 32, /* 0x38 - coreboot mem console pointer */ - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native PCIe support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support - /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index d6671f6..a603268 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -61,20 +61,7 @@ /* Post VBIOS Init */ gfx_post_vbios_init(dev); } - intel_gma_restore_opregion(); -} - -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; + intel_gma_init_igd_opregion(); } static void gma_generate_ssdt(struct device *dev) diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 32d6b8a..adefcda 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -49,40 +49,7 @@ u32 cbmc; /* 0x38 - coreboot memconsole */ u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */ - /* IGD OpRegion */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - - u8 unused[11]; + u8 unused[76]; /* ChromeOS specific (0x100-0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl index a28ef4b..aa3c344 100644 --- a/src/soc/intel/broadwell/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/acpi/globalnvs.asl @@ -46,48 +46,6 @@ PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit GPEI, 64, // 0x28 - 0x2f - GPE wake status bit - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native PCIe support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support - /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index dbb4205..79d0ae5 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -492,19 +492,6 @@ gtt_rmw(0x64810, 0xfffff800, dpdiv); } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void igd_init(struct device *dev) { int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT); @@ -588,32 +575,7 @@ gfx_set_init_done(lightup_ok); } - intel_gma_restore_opregion(); -} - -static unsigned long -gma_write_acpi_tables(struct device *const dev, unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; + intel_gma_init_igd_opregion(); } static void gma_generate_ssdt(struct device *dev) @@ -629,7 +591,6 @@ .enable_resources = &pci_dev_enable_resources, .init = &igd_init, .ops_pci = &broadwell_pci_ops, - .write_acpi_tables = gma_write_acpi_tables, .acpi_fill_ssdt = gma_generate_ssdt, }; diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index b2bc97a..925a699 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -39,40 +39,7 @@ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ u8 unused1[132]; /* 0x30 - 0xb3 - unused */ - /* IGD OpRegion */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd2; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - - u8 unused2[11]; + u8 unused2[76]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index 84e9776..9046119 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -72,20 +72,6 @@ /* Initialize PCI device, load/execute BIOS Option ROM */ pci_dev_init(dev); } -} -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - return acpi_align_current(current); + intel_gma_init_igd_opregion(); } diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 55c181b..0b2d635 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -132,7 +132,6 @@ .init = graphics_soc_init, .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = graphics_soc_write_acpi_opregion, .acpi_fill_ssdt = gma_generate_ssdt, #endif .scan_bus = scan_generic_bus, diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h index 5a68952..3af5728 100644 --- a/src/soc/intel/common/block/include/intelblocks/graphics.h +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -19,20 +19,6 @@ */ void graphics_soc_init(struct device *dev); -/* - * Write ASL entry for Graphics opregion - * Input: - * struct device *device: device structure - * current: start address of graphics opregion - * rsdp: pointer to RSDT (and XSDT) structure - * - * Output: - * End address of graphics opregion so that the called - * can use the same for future calls to write_acpi_tables - */ -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp); - /* i915 controller info for ACPI backlight controls */ const struct i915_gpu_controller_info * intel_igd_get_controller_info(struct device *device); diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index 0ee340c..ab2fc54 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -30,6 +30,11 @@ void graphics_soc_init(struct device *dev) { + /* IGD needs to Bus Master */ + uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + /* * GFX PEIM module inside FSP binary is taking care of graphics * initialization based on RUN_FSP_GOP Kconfig @@ -39,30 +44,12 @@ * In case of non-FSP solution, SoC need to select VGA_ROM_RUN * Kconfig to perform GFX initialization through VGA OpRom. */ - if (CONFIG(RUN_FSP_GOP)) - return; + if (CONFIG(RUN_FSP_GOP)) { + /* nothing to do */ + } else { + /* Initialize PCI device, load/execute BIOS Option ROM */ + pci_dev_init(dev); + } - /* IGD needs to Bus Master */ - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); -} - -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - return acpi_align_current(current); + intel_gma_init_igd_opregion(); } diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c index 0ee340c..bd9f9d3 100644 --- a/src/soc/intel/jasperlake/graphics.c +++ b/src/soc/intel/jasperlake/graphics.c @@ -30,6 +30,11 @@ void graphics_soc_init(struct device *dev) { + /* IGD needs to Bus Master */ + uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + /* * GFX PEIM module inside FSP binary is taking care of graphics * initialization based on RUN_FSP_GOP Kconfig @@ -39,30 +44,13 @@ * In case of non-FSP solution, SoC need to select VGA_ROM_RUN * Kconfig to perform GFX initialization through VGA OpRom. */ - if (CONFIG(RUN_FSP_GOP)) + if (CONFIG(RUN_FSP_GOP)) { + /* nothing to do */ return; + } else { + /* Initialize PCI device, load/execute BIOS Option ROM */ + pci_dev_init(dev); + } - /* IGD needs to Bus Master */ - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); -} - -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - return acpi_align_current(current); + intel_gma_init_igd_opregion(); } diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 7c40630..85d8ff6 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -60,48 +60,6 @@ A4GB, 64, // 0x55 - 0x5C Base of above 4GB MMIO Resource A4GS, 64, // 0x5D - 0x64 Length of above 4GB MMIO Resource - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native PCIe support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support - /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index c338a67..bc9a31b 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -125,55 +125,7 @@ pci_dev_init(dev); } - intel_gma_restore_opregion(); -} - -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - -/* Initialize IGD OpRegion, called from ACPI code */ -static void update_igd_opregion(igd_opregion_t *opregion) -{ - /* FIXME: Add platform specific mailbox initialization */ -} - -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - - /* If GOP is not used, exit here */ - if (!CONFIG(INTEL_GMA_ADD_VBT)) - return current; - - /* If IGD is disabled, exit here */ - if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF) - return current; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - if (gnvs) - gnvs->aslb = (u32)(uintptr_t)opregion; - update_igd_opregion(opregion); - current += sizeof(igd_opregion_t); - current = acpi_align_current(current); - - printk(BIOS_DEBUG, "current = %lx\n", current); - return current; + intel_gma_init_igd_opregion(); } const struct i915_gpu_controller_info * diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 480805b..8621106 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -49,42 +49,7 @@ u8 e4gm; /* 0x54 - Enable above 4GB MMIO Resource */ u64 a4gb; /* 0x55 - 0x5C Base of above 4GB MMIO Resource */ u64 a4gs; /* 0x5D - 0x64 Length of above 4GB MMIO Resource */ - u8 rsvd[79]; - - /* IGD OpRegion */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - - u8 unused[11]; + u8 rsvd[155]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c index 4054bd5..2164338 100644 --- a/src/soc/intel/tigerlake/graphics.c +++ b/src/soc/intel/tigerlake/graphics.c @@ -36,6 +36,11 @@ void graphics_soc_init(struct device *dev) { + /* IGD needs to Bus Master */ + uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + /* * GFX PEIM module inside FSP binary is taking care of graphics * initialization based on RUN_FSP_GOP Kconfig @@ -45,30 +50,12 @@ * In case of non-FSP solution, SoC need to select VGA_ROM_RUN * Kconfig to perform GFX initialization through VGA OpRom. */ - if (CONFIG(RUN_FSP_GOP)) - return; + if (CONFIG(RUN_FSP_GOP)) { + /* nothing to do */ + } else { + /* Initialize PCI device, load/execute BIOS Option ROM */ + pci_dev_init(dev); + } - /* IGD needs to Bus Master */ - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); -} - -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - return acpi_align_current(current); + intel_gma_init_igd_opregion(); } diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 8e99d49..2d42107 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -109,47 +109,8 @@ /* XHCI */ Offset (0xb2), XHCI, 8, - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native PCIe support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support + Offset (0xf5), TPIQ, 8, // 0xf5 - trackpad IRQ value /* ChromeOS specific */ diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 25c392d..8cb07b8 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -97,38 +97,7 @@ u8 rsvd11[6]; /* XHCI */ u8 xhci; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ + u8 rsvd12[65]; u8 tpiq; /* 0xf5 - trackpad IRQ value */ u8 rsvd13[10]; /* 0xf6 - rsvd */ diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h index c556573..75e0d0d 100644 --- a/src/southbridge/intel/i82801dx/nvs.h +++ b/src/southbridge/intel/i82801dx/nvs.h @@ -91,27 +91,7 @@ u8 gtf2[7]; u8 idem; u8 idet; - u8 rsvd11[7]; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; - u8 ipat; - u8 itvf; - u8 itvm; - u8 ipsc; - u8 iblc; - u8 ibia; - u8 issc; - u8 i409; - u8 i509; - u8 i609; - u8 i709; - u8 idmm; - u8 idms; - u8 if1e; - u8 hvco; - u32 nxd[8]; - u8 rsvd12[8]; + u8 rsvd11[67]; /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ u8 bten; diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index d71b1e0..4f3abeb 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -105,33 +105,6 @@ GTF2, 56, // 0xa4 - GTF task file buffer for port 2 IDEM, 8, // 0xab - IDE mode (compatible / enhanced) IDET, 8, // 0xac - IDE - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD DVMT Mode - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 /* Mainboard Specific (TODO move elsewhere) */ Offset (0xf0), DOCK, 8, // 0xf0 - Docking Status diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h index 980ab0b..0ddaf07 100644 --- a/src/southbridge/intel/i82801gx/nvs.h +++ b/src/southbridge/intel/i82801gx/nvs.h @@ -90,27 +90,7 @@ u8 gtf2[7]; u8 idem; u8 idet; - u8 rsvd11[7]; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; - u8 ipat; - u8 itvf; - u8 itvm; - u8 ipsc; - u8 iblc; - u8 ibia; - u8 issc; - u8 i409; - u8 i509; - u8 i609; - u8 i709; - u8 idmm; - u8 idms; - u8 if1e; - u8 hvco; - u32 nxd[8]; - u8 rsvd12[8]; + u8 rsvd11[67]; /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ u8 bten; diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index 6778fe7..a9824d2 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -109,33 +109,6 @@ GTF2, 56, // 0xa4 - GTF task file buffer for port 2 IDEM, 8, // 0xab - IDE mode (compatible / enhanced) IDET, 8, // 0xac - IDE - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD DVMT Mode - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 /* Mainboard Specific (TODO move elsewhere) */ Offset (0xf0), DOCK, 8, // 0xf0 - Docking Status diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index 0954daa..d1d3a73 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -92,27 +92,7 @@ u8 gtf2[7]; u8 idem; u8 idet; - u8 rsvd11[7]; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; - u8 ipat; - u8 itvf; - u8 itvm; - u8 ipsc; - u8 iblc; - u8 ibia; - u8 issc; - u8 i409; - u8 i509; - u8 i609; - u8 i709; - u8 idmm; - u8 idms; - u8 if1e; - u8 hvco; - u32 nxd[8]; - u8 rsvd12[8]; + u8 rsvd11[67]; /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ u8 bten; diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index ce810eb..dbc23b4 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -109,33 +109,6 @@ GTF2, 56, // 0xa4 - GTF task file buffer for port 2 IDEM, 8, // 0xab - IDE mode (compatible / enhanced) IDET, 8, // 0xac - IDE - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD DVMT Mode - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 /* Mainboard Specific (TODO move elsewhere) */ Offset (0xf0), DOCK, 8, // 0xf0 - Docking Status diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h index 95bfa26..82b1b1e 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/nvs.h @@ -90,27 +90,7 @@ u8 gtf2[7]; u8 idem; u8 idet; - u8 rsvd11[7]; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; - u8 ipat; - u8 itvf; - u8 itvm; - u8 ipsc; - u8 iblc; - u8 ibia; - u8 issc; - u8 i409; - u8 i509; - u8 i609; - u8 i709; - u8 idmm; - u8 idms; - u8 if1e; - u8 hvco; - u32 nxd[8]; - u8 rsvd12[8]; + u8 rsvd11[67]; /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ u8 bten; diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index c091b6f..bd02ec3 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -96,39 +96,7 @@ u8 rsvd11[6]; /* XHCI */ u8 xhci; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - u8 rsvd13[11]; /* 0xf5 - rsvd */ + u8 rsvd13[76]; /* 0xf5 - rsvd */ /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index ad7df7f..12e3950 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -104,48 +104,6 @@ Offset (0xa0), CBMC, 32, // 0xa0 - coreboot mem console pointer - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native PCIe support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support - /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index c35b4b5..ff0ea27 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -73,40 +73,7 @@ u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */ u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */ u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */ - u8 rsvd6[16]; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - u8 rsvd13[11]; /* 0xf5 - rsvd */ + u8 rsvd6[92]; /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -- To view, visit https://review.coreboot.org/c/coreboot/+/40724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29 Gerrit-Change-Number: 40724 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 24

Change in coreboot[master]: arch/x86: Add option to compress postcar stage
by Arthur Heymans (Code Review) 10 May '23

10 May '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36674 ) Change subject: arch/x86: Add option to compress postcar stage ...................................................................... arch/x86: Add option to compress postcar stage The LZ4 decompressor was already linked in romstage. Change-Id: I89fdc6066027447bf72968c66e6f5eb5fbb630c7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/x86/Makefile.inc 2 files changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/36674/1 diff --git a/src/Kconfig b/src/Kconfig index 0d56291..17bf545 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -158,6 +158,16 @@ that decompression might slow down booting if the boot flash is connected through a slow link (i.e. SPI). +config COMPRESS_POSTCAR + bool "Compress postcar with LZ4" + depends on POSTCAR_STAGE + # Default value set at the end of the file + help + Compress postcar with LZ4 to save flash space and speed up boot, + since the time for reading the image from SPI (and in the vboot + case verifying it) is usually much greater than the time spent + decompressing. + config COMPRESS_PRERAM_STAGES bool "Compress romstage and verstage with LZ4" depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE) @@ -1203,6 +1213,9 @@ config COMPRESS_RAMSTAGE default y if !UNCOMPRESSED_RAMSTAGE +config COMPRESS_POSTCAR + default y + config COMPRESS_PRERAM_STAGES depends on !ARCH_X86 default y diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 447fd57..8c35176 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -278,11 +278,16 @@ $(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod cp $< $@ +CBFS_POSTCAR_COMPRESS_FLAG := none +ifeq ($(CONFIG_COMPRESS_POSTCAR),y) +CBFS_POSTCAR_COMPRESS_FLAG := lz4 +endif + # Add postcar to CBFS cbfs-files-$(CONFIG_POSTCAR_STAGE) += $(CONFIG_CBFS_PREFIX)/postcar $(CONFIG_CBFS_PREFIX)/postcar-file := $(objcbfs)/postcar.elf $(CONFIG_CBFS_PREFIX)/postcar-type := stage -$(CONFIG_CBFS_PREFIX)/postcar-compression := none +$(CONFIG_CBFS_PREFIX)/postcar-compression := $(CBFS_POSTCAR_COMPRESS_FLAG) ############################################################################### # ramstage -- To view, visit https://review.coreboot.org/c/coreboot/+/36674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89fdc6066027447bf72968c66e6f5eb5fbb630c7 Gerrit-Change-Number: 36674 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

10 24

Change in ...coreboot[master]: mb/lenovo/x60: Override default SPI OPs
by Arthur Heymans (Code Review) 10 May '23

10 May '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33041 Change subject: mb/lenovo/x60: Override default SPI OPs ...................................................................... mb/lenovo/x60: Override default SPI OPs The thinkpad X60 with SST flash needs different SPI OPs to make flashrom happy. flashrom uses AAI for writing. One potential issue is that fast_read is not possible anymore, but on x86 the flash is memory mapped so this won't matter. Change-Id: Id65fc632b33962bd505283c842c45feb85c75e5f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x60/mainboard.c 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/33041/1 diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 274a151..3aef020 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <spi_flash.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/device.h> @@ -26,6 +27,7 @@ #include <drivers/intel/gma/int15.h> #include <drivers/lenovo/lenovo.h> #include <arch/acpigen.h> +#include <southbridge/intel/common/spi.h> #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT @@ -66,6 +68,28 @@ return ARRAY_SIZE(cst_entries); } + +static const struct intel_spi_config spi_config_sst = { + .opprefixes = {0x06, 0x50}, + .ops = {{0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ + {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */ + {0x03, READ_WITH_ADDR}, /* READ: Read Data */ + {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ + {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ + {0x9f, READ_NO_ADDR}, /* RDID: Read ID */ + {0xad, WRITE_NO_ADDR}, /* Auto Address Increment Word Program */ + {0x04, WRITE_NO_ADDR}} /* Write Disable */ +}; + +void intel_southbridge_override_spi(struct intel_spi_config *spi_config) +{ + const struct spi_flash *flash = boot_device_spi_flash(); + + if (strcmp(flash->name, "SST25VF016B") == 0) { + memcpy(spi_config, &spi_config_sst, sizeof(spi_config_sst)); + } +} + static void mainboard_init(struct device *dev) { struct device *idedev, *sdhci_dev; -- To view, visit https://review.coreboot.org/c/coreboot/+/33041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id65fc632b33962bd505283c842c45feb85c75e5f Gerrit-Change-Number: 33041 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 15

Change in coreboot[master]: ec/google/chromeec: Guard battery-related ACPI code
by Matt DeVillier (Code Review) 30 Apr '23

30 Apr '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48859 ) Change subject: ec/google/chromeec: Guard battery-related ACPI code ...................................................................... ec/google/chromeec: Guard battery-related ACPI code Boards which do not have a built-in battery, like Fizz and Puff-based Chromeboxes, still report the board using a battery but one not being connected, leading to a red battery icon with a disabled symbol in many OSes. Mitigate this by guarding the inclusion of battery.asl with ifndef EC_NO_BATTERY_PRESENT, and define this for Fizz and Puff-based boards. Also guard _Qxx methods which reference BAT0. Test: build/boot Puff variant, boot OS (eg, Windows 10 2H20), check that a missing battery is not reported by the OS. Change-Id: I41df5a925c9a15553d9e818a2efed2210311fd45 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/google/chromeec/acpi/ec.asl M src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/hatch/variants/baseboard/include/puff/ec.h 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/48859/1 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 218d08b..effc2bf 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -263,20 +263,25 @@ // Battery Low Event Method (_Q06, 0, NotSerialized) { +#ifndef EC_NO_BATTERY_PRESENT Store ("EC: BATTERY LOW", Debug) Notify (BAT0, 0x80) +#endif } // Battery Critical Event Method (_Q07, 0, NotSerialized) { +#ifndef EC_NO_BATTERY_PRESENT Store ("EC: BATTERY CRITICAL", Debug) Notify (BAT0, 0x80) +#endif } // Battery Info Event Method (_Q08, 0, NotSerialized) { +#ifndef EC_NO_BATTERY_PRESENT Store ("EC: BATTERY INFO", Debug) Notify (BAT0, 0x81) #ifdef EC_ENABLE_SECOND_BATTERY_DEVICE @@ -284,6 +289,7 @@ Notify (BAT1, 0x81) } #endif +#endif } // Thermal Overload Event @@ -323,8 +329,10 @@ // Battery Shutdown Imminent Method (_Q11, 0, NotSerialized) { +#ifndef EC_NO_BATTERY_PRESENT Store ("EC: BATTERY SHUTDOWN", Debug) Notify (BAT0, 0x80) +#endif } // Throttle Start @@ -357,6 +365,7 @@ // Battery Status Method (_Q17, 0, NotSerialized) { +#ifndef EC_NO_BATTERY_PRESENT Store ("EC: BATTERY STATUS", Debug) Notify (BAT0, 0x80) #ifdef EC_ENABLE_SECOND_BATTERY_DEVICE @@ -364,6 +373,7 @@ Notify (BAT1, 0x80) } #endif +#endif } // MKBP interrupt. @@ -567,7 +577,9 @@ #endif #include "ac.asl" +#ifndef EC_NO_BATTERY_PRESENT #include "battery.asl" +#endif #include "cros_ec.asl" #ifdef EC_ENABLE_ALS_DEVICE diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h index 504b6de..b02a389 100644 --- a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h @@ -53,4 +53,7 @@ #define EC_ENABLE_MKBP_DEVICE /* Enable cros_ec_keyb device */ +/* Fizz-based boards do not have a built-in battery */ +#define EC_NO_BATTERY_PRESENT + #endif diff --git a/src/mainboard/google/hatch/variants/baseboard/include/puff/ec.h b/src/mainboard/google/hatch/variants/baseboard/include/puff/ec.h index 986cf61..36e1b73 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/puff/ec.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/puff/ec.h @@ -56,4 +56,7 @@ /* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ #define EC_ENABLE_SYNC_IRQ +/* Puff-based boards do not have a built-in battery */ +#define EC_NO_BATTERY_PRESENT + #endif /* __BASEBOARD_EC_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41df5a925c9a15553d9e818a2efed2210311fd45 Gerrit-Change-Number: 48859 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: arch/x86/include/arch/pci_io_cfg.h: Fix UndefinedBehavior sanitizer c...
by Shawn C (Code Review) 10 Apr '23

10 Apr '23

Shawn C has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49076 ) Change subject: arch/x86/include/arch/pci_io_cfg.h: Fix UndefinedBehavior sanitizer complain ...................................................................... arch/x86/include/arch/pci_io_cfg.h: Fix UndefinedBehavior sanitizer complain GCC build option "-fsanitize=shift" will complain: "runtime error: left shift of 1 by 31 places cannot be represented in type 'int'" Signed-off-by: Shawn C <citypw(a)hardenedlinux.org> Change-Id: I6eeee1e92b616f68aa60eb74771912dd00ff7712 --- M src/arch/x86/include/arch/pci_io_cfg.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/49076/1 diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index 61dd106..5e9761e 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -10,7 +10,7 @@ static __always_inline uint32_t pci_io_encode_addr(pci_devfn_t dev, uint16_t reg) { - uint32_t addr = 1 << 31; + uint32_t addr = 1UL << 31; addr |= dev >> 4; addr |= reg & 0xfc; -- To view, visit https://review.coreboot.org/c/coreboot/+/49076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6eeee1e92b616f68aa60eb74771912dd00ff7712 Gerrit-Change-Number: 49076 Gerrit-PatchSet: 1 Gerrit-Owner: Shawn C <citypw(a)hardenedlinux.org> Gerrit-MessageType: newchange

4 9

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