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Change subject: amdfwtool: Add support for A/B recovery
......................................................................
Patch Set 9:
(2 comments)
File util/amdfwtool/amdfwtool.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127172):
https://review.coreboot.org/c/coreboot/+/56773/comment/0714e058_d33efe9c
PS9, Line 1698: pspdir2_b = new_psp_dir(&ctx, cb_config.multi_level); /* same as above */
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127172):
https://review.coreboot.org/c/coreboot/+/56773/comment/41e1051f_fd3ba009
PS9, Line 1749: //biosdir = new_bios_dir(&ctx, cb_config.multi_level); /* TODO: move here? */
line over 96 characters
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Hello build bot (Jenkins), Zheng Bao,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57131
to look at the new patch set (#4).
Change subject: amdfwtool: Add support for traditional recovery
......................................................................
amdfwtool: Add support for traditional recovery
Change-Id: I2671b95fe089aafdaf61b55bc9d2e8dcf6a66dbc
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
M util/amdfwtool/data_parse.c
3 files changed, 54 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/57131/4
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56773
to look at the new patch set (#9).
Change subject: amdfwtool: Add support for A/B recovery
......................................................................
amdfwtool: Add support for A/B recovery
The rom layout for A/B recovery:
EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A
0x4A -> PSP L2 B -> BIOS L2 B
To enable A/B recovery in PSP layout, add "--recovery-ab" to
amdfwtool.
Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
M util/amdfwtool/data_parse.c
3 files changed, 216 insertions(+), 55 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/56773/9
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Ray Ni has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57296 )
Change subject: util/cbftool: Fix the bug in parsing Uefipayload with extended header
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Can you please update the commit message to explain what issue was met that needs this fix?
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Change subject: amdfwtool: Detect the flag multilevel to decide the actual value
......................................................................
Patch Set 4:
(2 comments)
File util/amdfwtool/amdfwtool.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127168):
https://review.coreboot.org/c/coreboot/+/57063/comment/cf7cabda_3d61a230
PS4, Line 589: amd_cb_config *cb_config)
need consistent spacing around '*' (ctx:WxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127168):
https://review.coreboot.org/c/coreboot/+/57063/comment/d032842a_9d335f0f
PS4, Line 770: amd_cb_config *cb_config)
need consistent spacing around '*' (ctx:WxV)
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Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57096 )
Change subject: tpch: Introduce new thermal control mechanism for pch device
......................................................................
Patch Set 2:
(4 comments)
Patchset:
PS1:
> Why did you break this out into a separate chip driver? […]
ACK
File src/drivers/intel/tpch/tpch.h:
https://review.coreboot.org/c/coreboot/+/57096/comment/15059077_c2d2c1d5
PS1, Line 15: /* IPC command to control FIVR Configuration */
: #define V_PMC_PWRM_IPC_CMD_COMMAND_FIVR 0xA3
: /* IPC subcommand to write FIVR Register */
: #define V_PMC_PWRM_IPC_CMD_CMD_ID_FIVR_WRITE 0x01
: /* IPC subcommand to control RFI Control 0 register logic write */
: #define V_PMC_PWRM_IPC_SUBCMD_RFI_CTRL0_LOGIC 0x00
: /* IPC subcommand to control RFI Control 4 register logic write */
: #define V_PMC_PWRM_IPC_SUBCMD_RFI_CTRL4_LOGIC 0x01
> These should probably go in […]
Done
File src/drivers/intel/tpch/tpch.c:
https://review.coreboot.org/c/coreboot/+/57096/comment/cdd241e3_ffe03abb
PS1, Line 26: acpigen_emit_namestring("IPCS");
: acpigen_write_integer(V_PMC_PWRM_IPC_CMD_COMMAND_FIVR);
: acpigen_write_integer(V_PMC_PWRM_IPC_CMD_CMD_ID_FIVR_WRITE);
: acpigen_write_integer(0x8);
: acpigen_write_integer(V_PMC_PWRM_IPC_SUBCMD_RFI_CTRL0_LOGIC);
: acpigen_write_dword(3);
: acpigen_emit_byte(RETURN_OP);
: acpigen_write_package(0);
: acpigen_write_method_end();
: acpigen_pop_len();
:
: acpigen_write_method_serialized("RFC1", 1);
: acpigen_emit_namestring("IPCS");
: acpigen_write_integer(V_PMC_PWRM_IPC_CMD_COMMAND_FIVR);
: acpigen_write_integer(V_PMC_PWRM_IPC_CMD_CMD_ID_FIVR_WRITE);
: acpigen_write_integer(0x8);
: acpigen_write_integer(V_PMC_PWRM_IPC_SUBCMD_RFI_CTRL4_LOGIC);
> Got it, thanks! Should the GFC0 and GFC1 methods be implemented too?
Welcome. Yes, I'm working phase wise manner, will submit separate new CL for GFC0 and GFC1 methods on top of this.
https://review.coreboot.org/c/coreboot/+/57096/comment/57ce1790_64a8c763
PS1, Line 51: devices
> nit: space after `devices`
Ack
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Change subject: mb/system76/*: cmos.layout: Reserve century byte
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/alderlake: Fix processor hang while plug unplug of TBT device
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
Tim, Furquan,
Can we merge this patch?
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