coreboot-gerrit September 2021

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Change in coreboot[master]: mb/pcengines/apu2: add and use IOMUX defines
by Felix Held (Code Review) 03 Sep '21

03 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56836 ) Change subject: mb/pcengines/apu2: add and use IOMUX defines ...................................................................... mb/pcengines/apu2: add and use IOMUX defines Add GPIO IOMUX defines for the pins that are used in the mainboard code which enables using the PAD_GPI and PAD_GPO macros. TEST=Timeless build for APU2/3/4/5 results in identical binary. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie32df9ed2cb6a5670a29cff91e085a3585c8bcf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56836 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/pcengines/apu2/gpio_ftns.h M src/mainboard/pcengines/apu2/romstage.c 2 files changed, 30 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h index 6386220..fb4edd9 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.h +++ b/src/mainboard/pcengines/apu2/gpio_ftns.h @@ -26,4 +26,18 @@ #define GPIO_68 0x48 // PE4_WDIS (SIMSWAP1 on APU5) #define GPIO_71 0x4D // PROCHOT +#define GPIO_22_IOMUX_GPIOxx 0 +#define GPIO_32_IOMUX_GPIOxx 0 +#define GPIO_33_IOMUX_GPIOxx 0 +#define GPIO_49_IOMUX_GPIOxx 2 +#define GPIO_50_IOMUX_GPIOxx 2 +#define GPIO_51_IOMUX_GPIOxx 2 +#define GPIO_55_IOMUX_GPIOxx 3 +#define GPIO_57_IOMUX_GPIOxx 1 +#define GPIO_58_IOMUX_GPIOxx 1 +#define GPIO_59_IOMUX_GPIOxx 3 +#define GPIO_64_IOMUX_GPIOxx 2 +#define GPIO_68_IOMUX_GPIOxx 0 +#define GPIO_71_IOMUX_GPIOxx 0 + #endif /* GPIO_FTNS_H */ diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 9b1435a..5d2b988 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -31,39 +31,31 @@ } const struct soc_amd_gpio gpio_common[] = { - /* Output disabled, pull up/down disabled */ - PAD_CFG_STRUCT(GPIO_49, Function2, PAD_PULL(PULL_NONE)), - PAD_CFG_STRUCT(GPIO_50, Function2, PAD_PULL(PULL_NONE)), - PAD_CFG_STRUCT(GPIO_71, Function0, PAD_PULL(PULL_NONE)), - /* Output enabled, value low, pull up/down disabled */ - PAD_CFG_STRUCT(GPIO_57, Function1, PAD_OUTPUT(LOW)), - PAD_CFG_STRUCT(GPIO_58, Function1, PAD_OUTPUT(LOW)), - PAD_CFG_STRUCT(GPIO_59, Function3, PAD_OUTPUT(LOW)), - /* Output enabled, value high, pull up/down disabled */ - PAD_CFG_STRUCT(GPIO_51, Function2, PAD_OUTPUT(HIGH)), - PAD_CFG_STRUCT(GPIO_55, Function3, PAD_OUTPUT(HIGH)), - PAD_CFG_STRUCT(GPIO_64, Function2, PAD_OUTPUT(HIGH)), - PAD_CFG_STRUCT(GPIO_68, Function0, PAD_OUTPUT(HIGH)), + PAD_GPI(GPIO_49, PULL_NONE), + PAD_GPI(GPIO_50, PULL_NONE), + PAD_GPI(GPIO_71, PULL_NONE), + PAD_GPO(GPIO_57, LOW), + PAD_GPO(GPIO_58, LOW), + PAD_GPO(GPIO_59, LOW), + PAD_GPO(GPIO_51, HIGH), + PAD_GPO(GPIO_55, HIGH), + PAD_GPO(GPIO_64, HIGH), + PAD_GPO(GPIO_68, HIGH), }; const struct soc_amd_gpio gpio_apu2[] = { - /* Output disabled, pull up/down disabled */ - PAD_CFG_STRUCT(GPIO_32, Function0, PAD_PULL(PULL_NONE)), + PAD_GPI(GPIO_32, PULL_NONE), }; const struct soc_amd_gpio gpio_apu34[] = { - /* Output disabled, pull up/down disabled */ - PAD_CFG_STRUCT(GPIO_32, Function0, PAD_PULL(PULL_NONE)), - /* Output enabled, value low, pull up/down disabled */ - PAD_CFG_STRUCT(GPIO_33, Function0, PAD_OUTPUT(LOW)), + PAD_GPI(GPIO_32, PULL_NONE), + PAD_GPO(GPIO_33, LOW), }; const struct soc_amd_gpio gpio_apu5[] = { - /* Output disabled, pull up/down disabled */ - PAD_CFG_STRUCT(GPIO_22, Function0, PAD_PULL(PULL_NONE)), - /* Output enabled, value high, pull up/down disabled */ - PAD_CFG_STRUCT(GPIO_32, Function0, PAD_OUTPUT(HIGH)), - PAD_CFG_STRUCT(GPIO_33, Function0, PAD_OUTPUT(HIGH)), + PAD_GPI(GPIO_22, PULL_NONE), + PAD_GPO(GPIO_32, HIGH), + PAD_GPO(GPIO_33, HIGH), }; static void early_lpc_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/56836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie32df9ed2cb6a5670a29cff91e085a3585c8bcf7 Gerrit-Change-Number: 56836 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/gpio_banks/Kconfig: add option for non-soc/ chips
by Felix Held (Code Review) 03 Sep '21

03 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56783 ) Change subject: soc/amd/common/block/gpio_banks/Kconfig: add option for non-soc/ chips ...................................................................... soc/amd/common/block/gpio_banks/Kconfig: add option for non-soc/ chips southbridge/amd/pi/hudson uses the common GPIO bank access code from soc/amd, but doesn't provide all functionality that would be needed to use the full functionality. Add a Kconfig option that switches off some functionality in the common SoC GPIO access code, so that more of the functionality proviced by the common SoC GPIO code can be used in the AMD binaryPI chipset and board code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib10d5d5580aab30a359aa001bb6fc7e9fdb8fc41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56783 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/gpio_banks/Kconfig M src/soc/amd/common/block/gpio_banks/gpio.c M src/southbridge/amd/pi/hudson/Kconfig 3 files changed, 17 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/common/block/gpio_banks/Kconfig b/src/soc/amd/common/block/gpio_banks/Kconfig index 1efb1db..0a1bffe 100644 --- a/src/soc/amd/common/block/gpio_banks/Kconfig +++ b/src/soc/amd/common/block/gpio_banks/Kconfig @@ -5,3 +5,16 @@ Select this option to use the newer style banks of GPIO signals. These are at offsets +0x1500, +0x1600, and +0x1700 from the AcpiMmio base. + +if SOC_AMD_COMMON_BLOCK_BANKED_GPIOS + +config SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE + bool + help + Select this option when selecting the GPIO bank support from AMD + chipsets outside the soc/ subtree that only support a subset of the + features available on the chipsets inside the soc/ subtree. When this + option is selected, no SMI or SCI event can be configured by the GPIO + code. + +endif # SOC_AMD_COMMON_BLOCK_BANKED_GPIOS diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 8f84cb6..b3c1ac1 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -171,8 +171,9 @@ static const struct soc_amd_event *gev_tbl; static size_t gev_items; int gevent_num; - const bool can_set_smi_flags = !(CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && - ENV_SEPARATE_VERSTAGE); + const bool can_set_smi_flags = !((CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && + ENV_SEPARATE_VERSTAGE) || + CONFIG(SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE)); set_gpio_mux(g->gpio, g->function); diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index fa60d17..c959e28 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -18,6 +18,7 @@ select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS + select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE select SOC_AMD_COMMON_BLOCK_PCI_MMCONF config EHCI_BAR -- To view, visit https://review.coreboot.org/c/coreboot/+/56783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib10d5d5580aab30a359aa001bb6fc7e9fdb8fc41 Gerrit-Change-Number: 56783 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/gpio_banks/Kconfig: add option for non-soc/ chips
by Martin Roth (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56783 ) Change subject: soc/amd/common/block/gpio_banks/Kconfig: add option for non-soc/ chips ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib10d5d5580aab30a359aa001bb6fc7e9fdb8fc41 Gerrit-Change-Number: 56783 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Sep 2021 15:49:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/device/Kconfig: introduce the AMD_DGPU_WITHOUT_EEPROM symbols
by Nico Huber (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Mike Banon. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57319 ) Change subject: src/device/Kconfig: introduce the AMD_DGPU_WITHOUT_EEPROM symbols ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: How is the situation different from that for nvidia? -- To view, visit https://review.coreboot.org/c/coreboot/+/57319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I424f93961c9d4a856dd6f5285417597cb117084d Gerrit-Change-Number: 57319 Gerrit-PatchSet: 2 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: awokd(a)danwin1210.me Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 15:42:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot tables: Add type-c port info to coreboot table
by Nico Huber (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57069 ) Change subject: coreboot tables: Add type-c port info to coreboot table ...................................................................... Patch Set 16: (3 comments) File payloads/libpayload/include/sysinfo.h: https://review.coreboot.org/c/coreboot/+/57069/comment/35523ee9_08a56639 PS16, Line 49: /* The orientation of the signal follows the orientation of the CC lines. */ : #define SYSINFO_TYPEC_ORIENTATION_FOLLOW_CC 0 : : /* The orientation of the signal is fixed to follow CC1 */ : #define SYSINFO_TYPEC_ORIENTATION_NORMAL 1 : : /* The orientation of the signal is fixed to follow CC2 */ : #define SYSINFO_TYPEC_ORIENTATION_REVERSE 2 Shouldn't this be part of `coreboot_tables.h`? https://review.coreboot.org/c/coreboot/+/57069/comment/c44353e4_3e5f64bd PS16, Line 172: struct { : uint8_t usb2_port_number; : uint8_t usb3_port_number; : uint8_t sbu_orientation; : uint8_t data_orientation; Can we re-use the struct from `coreboot_tables.h`? File src/lib/coreboot_table.c: https://review.coreboot.org/c/coreboot/+/57069/comment/d7d7db14_68139065 PS16, Line 263: rec->size = sizeof(*rec); Doesn't this need to include the ports? -- To view, visit https://review.coreboot.org/c/coreboot/+/57069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Gerrit-Change-Number: 57069 Gerrit-PatchSet: 16 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 15:41:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/pcengines/apu2/gpio_ftns.h: add comment about GPIO numbers
by Felix Held (Code Review) 03 Sep '21

03 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56808 ) Change subject: mb/pcengines/apu2/gpio_ftns.h: add comment about GPIO numbers ...................................................................... mb/pcengines/apu2/gpio_ftns.h: add comment about GPIO numbers The mapping of the package GPIO numbers to the GPIO numbers on the GPIO controller isn't a 1:1 one, so add a comment about that to avoid confusion. Also change the comment style to match the style guide. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie30bf5483ea2e2516d7e3fdd21ea9338362e526e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56808 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/pcengines/apu2/gpio_ftns.h 1 file changed, 6 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h index 95c744f..6386220 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.h +++ b/src/mainboard/pcengines/apu2/gpio_ftns.h @@ -5,11 +5,12 @@ int get_spd_offset(void); -// -// Based on PC Engines APU2C and APU3A schematics -// http://www.pcengines.ch/schema/apu2c.pdf -// http://www.pcengines.ch/schema/apu3a.pdf -// +/* + * Based on PC Engines APU2C and APU3A schematics + * http://www.pcengines.ch/schema/apu2c.pdf + * http://www.pcengines.ch/schema/apu3a.pdf + * Beware that the GPIO pin numbers on the package don't match the internal GPIO numbers + */ #define GPIO_22 0x09 // MODESW (APU5) #define GPIO_32 0x59 // MODESW (SIMSWAP2 on APU5) #define GPIO_33 0x5A // SIMSWAP (SIMSWAP3 on APU5) -- To view, visit https://review.coreboot.org/c/coreboot/+/56808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie30bf5483ea2e2516d7e3fdd21ea9338362e526e Gerrit-Change-Number: 56808 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/pcengines/apu2/romstage: use proper GPIO configuration API
by Felix Held (Code Review) 03 Sep '21

03 Sep '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56784 ) Change subject: mb/pcengines/apu2/romstage: use proper GPIO configuration API ...................................................................... mb/pcengines/apu2/romstage: use proper GPIO configuration API Also remove the unused amdblocks/acpimmio.h include in gpio_ftns.c. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: If121941c8a6ba88913653192740997aeef426548 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56784 Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/pcengines/apu2/gpio_ftns.c M src/mainboard/pcengines/apu2/romstage.c 2 files changed, 44 insertions(+), 54 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c index 28b9a74..1fd6fda 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.c +++ b/src/mainboard/pcengines/apu2/gpio_ftns.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <amdblocks/acpimmio.h> #include <gpio.h> #include "gpio_ftns.h" diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 09a0309..9b1435a 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -2,6 +2,8 @@ #include <stdint.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/gpio_banks.h> +#include <amdblocks/gpio_defs.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <gpio.h> @@ -28,63 +30,52 @@ pm_write8(0xea, 1); } -static void pin_input(gpio_t gpio, u8 iomux_ftn) -{ - iomux_write8(gpio, iomux_ftn); - gpio_input(gpio); -} +const struct soc_amd_gpio gpio_common[] = { + /* Output disabled, pull up/down disabled */ + PAD_CFG_STRUCT(GPIO_49, Function2, PAD_PULL(PULL_NONE)), + PAD_CFG_STRUCT(GPIO_50, Function2, PAD_PULL(PULL_NONE)), + PAD_CFG_STRUCT(GPIO_71, Function0, PAD_PULL(PULL_NONE)), + /* Output enabled, value low, pull up/down disabled */ + PAD_CFG_STRUCT(GPIO_57, Function1, PAD_OUTPUT(LOW)), + PAD_CFG_STRUCT(GPIO_58, Function1, PAD_OUTPUT(LOW)), + PAD_CFG_STRUCT(GPIO_59, Function3, PAD_OUTPUT(LOW)), + /* Output enabled, value high, pull up/down disabled */ + PAD_CFG_STRUCT(GPIO_51, Function2, PAD_OUTPUT(HIGH)), + PAD_CFG_STRUCT(GPIO_55, Function3, PAD_OUTPUT(HIGH)), + PAD_CFG_STRUCT(GPIO_64, Function2, PAD_OUTPUT(HIGH)), + PAD_CFG_STRUCT(GPIO_68, Function0, PAD_OUTPUT(HIGH)), +}; -static void pin_low(gpio_t gpio, u8 iomux_ftn) -{ - iomux_write8(gpio, iomux_ftn); - gpio_output(gpio, 0); -} +const struct soc_amd_gpio gpio_apu2[] = { + /* Output disabled, pull up/down disabled */ + PAD_CFG_STRUCT(GPIO_32, Function0, PAD_PULL(PULL_NONE)), +}; -static void pin_high(gpio_t gpio, u8 iomux_ftn) -{ - iomux_write8(gpio, iomux_ftn); - gpio_output(gpio, 1); -} +const struct soc_amd_gpio gpio_apu34[] = { + /* Output disabled, pull up/down disabled */ + PAD_CFG_STRUCT(GPIO_32, Function0, PAD_PULL(PULL_NONE)), + /* Output enabled, value low, pull up/down disabled */ + PAD_CFG_STRUCT(GPIO_33, Function0, PAD_OUTPUT(LOW)), +}; + +const struct soc_amd_gpio gpio_apu5[] = { + /* Output disabled, pull up/down disabled */ + PAD_CFG_STRUCT(GPIO_22, Function0, PAD_PULL(PULL_NONE)), + /* Output enabled, value high, pull up/down disabled */ + PAD_CFG_STRUCT(GPIO_32, Function0, PAD_OUTPUT(HIGH)), + PAD_CFG_STRUCT(GPIO_33, Function0, PAD_OUTPUT(HIGH)), +}; static void early_lpc_init(void) { - // - // Configure output disabled, pull up/down disabled - // + program_gpios(gpio_common, ARRAY_SIZE(gpio_common)); + + if (CONFIG(BOARD_PCENGINES_APU2)) + program_gpios(gpio_apu2, ARRAY_SIZE(gpio_apu2)); + + if (CONFIG(BOARD_PCENGINES_APU3) || CONFIG(BOARD_PCENGINES_APU4)) + program_gpios(gpio_apu34, ARRAY_SIZE(gpio_apu34)); + if (CONFIG(BOARD_PCENGINES_APU5)) - pin_input(GPIO_22, Function0); - - if (CONFIG(BOARD_PCENGINES_APU2) || - CONFIG(BOARD_PCENGINES_APU3) || - CONFIG(BOARD_PCENGINES_APU4)) { - pin_input(GPIO_32, Function0); - } - - pin_input(GPIO_49, Function2); - pin_input(GPIO_50, Function2); - pin_input(GPIO_71, Function0); - - // - // Configure output enabled, value low, pull up/down disabled - // - if (CONFIG(BOARD_PCENGINES_APU3) || - CONFIG(BOARD_PCENGINES_APU4)) { - pin_low(GPIO_33, Function0); - } - pin_low(GPIO_57, Function1); - pin_low(GPIO_58, Function1); - pin_low(GPIO_59, Function3); - - // - // Configure output enabled, value high, pull up/down disabled - // - if (CONFIG(BOARD_PCENGINES_APU5)) { - pin_high(GPIO_32, Function0); - pin_high(GPIO_33, Function0); - } - - pin_high(GPIO_51, Function2); - pin_high(GPIO_55, Function3); - pin_high(GPIO_64, Function2); - pin_high(GPIO_68, Function0); + program_gpios(gpio_apu5, ARRAY_SIZE(gpio_apu5)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/56784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If121941c8a6ba88913653192740997aeef426548 Gerrit-Change-Number: 56784 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/pcengines/apu2/romstage: use proper GPIO configuration API
by Felix Held (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Piotr Król. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56784 ) Change subject: mb/pcengines/apu2/romstage: use proper GPIO configuration API ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Works well, no issues detected by our testing suites. Felix you may add […] thanks for testing this patch! -- To view, visit https://review.coreboot.org/c/coreboot/+/56784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If121941c8a6ba88913653192740997aeef426548 Gerrit-Change-Number: 56784 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 15:40:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/pcengines/apu2/romstage: use proper GPIO configuration API
by Felix Held (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Felix Held, Piotr Król. Hello build bot (Jenkins), Michał Żygowski, Piotr Król, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56784 to look at the new patch set (#3). Change subject: mb/pcengines/apu2/romstage: use proper GPIO configuration API ...................................................................... mb/pcengines/apu2/romstage: use proper GPIO configuration API Also remove the unused amdblocks/acpimmio.h include in gpio_ftns.c. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: If121941c8a6ba88913653192740997aeef426548 --- M src/mainboard/pcengines/apu2/gpio_ftns.c M src/mainboard/pcengines/apu2/romstage.c 2 files changed, 44 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/56784/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If121941c8a6ba88913653192740997aeef426548 Gerrit-Change-Number: 56784 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Skip returning default leaf value as `0`
by Subrata Banik (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, Angel Pons, Kyösti Mälkki. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57305 ) Change subject: arch/x86: Skip returning default leaf value as `0` ...................................................................... Patch Set 3: (1 comment) File src/arch/x86/cpu_common.c: https://review.coreboot.org/c/coreboot/+/57305/comment/3543c469_dd16f536 PS2, Line 115: return DETERMINISTIC_CACHE_PARAMETERS_CPUID_IA; > I don't mind. Thanks Angel -- To view, visit https://review.coreboot.org/c/coreboot/+/57305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee33b39298e7821ac5280d998172b58a70c8715b Gerrit-Change-Number: 57305 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 15:38:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit September 2021