coreboot-gerrit September 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/alderlake: Enable Irms UPD for ADL
by Sridhar Siricilla (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: V Sowmya, Maulik V Vaghela, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Vinay Kumar, Balaji Manigandan, Kane Chen, Ronak Kanabar, Srinidhi N Kaushik, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56330 ) Change subject: soc/intel/alderlake: Enable Irms UPD for ADL ...................................................................... Patch Set 12: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/56330/comment/9883598b_a607aed1 PS12, Line 617: s_cfg->Irms[i] = 1; Can you please enable IRMS as part of VR domain config function {fill_vr_domain_config()}? -- To view, visit https://review.coreboot.org/c/coreboot/+/56330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice5c775ef9560503109957a1ed994af1d287aafc Gerrit-Change-Number: 56330 Gerrit-PatchSet: 12 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 03 Sep 2021 13:19:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Enable thermal control functionality for tpch
by Sumeet R Pawnikar (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57098 to look at the new patch set (#5). Change subject: mb/google/brya: Enable thermal control functionality for tpch ...................................................................... mb/google/brya: Enable thermal control functionality for tpch Enable thermal control functionality for tpch device on brya device. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I6a35a101599bb811fcddaabab5296f8c6c12af31 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/57098/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/57098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a35a101599bb811fcddaabab5296f8c6c12af31 Gerrit-Change-Number: 57098 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/dptf: Introduce new thermal control mechanism for pch d...
by Sumeet R Pawnikar (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57096 to look at the new patch set (#6). Change subject: drivers/intel/dptf: Introduce new thermal control mechanism for pch device ...................................................................... drivers/intel/dptf: Introduce new thermal control mechanism for pch device Introduce new thermal control mechanism for pch device under dptf. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I035d2844b9ba6a9532ae006fc1c43e34cb94328a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/drivers/intel/dptf/Kconfig M src/drivers/intel/dptf/dptf.c M src/drivers/intel/dptf/dptf.h 3 files changed, 57 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/57096/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/57096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I035d2844b9ba6a9532ae006fc1c43e34cb94328a Gerrit-Change-Number: 57096 Gerrit-PatchSet: 6 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add tpch device information under dptf
by Sumeet R Pawnikar (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57097 to look at the new patch set (#6). Change subject: soc/intel/alderlake: Add tpch device information under dptf ...................................................................... soc/intel/alderlake: Add tpch device information under dptf Add tpch device information for FIVR functionality under dptf for alderlake soc based platform. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Iad8e8bc0b7a104bbe582bc477936d0d00087f1d1 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/alderlake/dptf.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/57097/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/57097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad8e8bc0b7a104bbe582bc477936d0d00087f1d1 Gerrit-Change-Number: 57097 Gerrit-PatchSet: 6 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add PMC IPC commands for FIVR
by Sumeet R Pawnikar (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57095 to look at the new patch set (#5). Change subject: soc/intel/common: Add PMC IPC commands for FIVR ...................................................................... soc/intel/common: Add PMC IPC commands for FIVR Add PMC IPC commands information for FIVR control functionality. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Iccb43b7ba4f0765499bf1844efbbb526bd671a8f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/pmc_ipc.h 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/57095/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/57095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccb43b7ba4f0765499bf1844efbbb526bd671a8f Gerrit-Change-Number: 57095 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/dptf: Introduce new thermal control mechanism for pch d...
by Sumeet R Pawnikar (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57096 ) Change subject: drivers/intel/dptf: Introduce new thermal control mechanism for pch device ...................................................................... Patch Set 5: (5 comments) Patchset: PS5: > Any plans to support GFC0, GFC1, GEMI, SEMI, GFCS, GFCS ? We will add support for these in next different patch set. File src/drivers/intel/dptf/dptf.c: https://review.coreboot.org/c/coreboot/+/57096/comment/dd52ea36_ba0f5757 PS5, Line 7: #include <soc/intel/common/block/include/intelblocks/pmc_ipc.h> > `#include <intelblocks/pmc_ipc. […] Ack https://review.coreboot.org/c/coreboot/+/57096/comment/e8958f55_0920fa72 PS5, Line 200: int > nit: […] Ack https://review.coreboot.org/c/coreboot/+/57096/comment/a0761cbc_c7617385 PS5, Line 211: acpigen_emit_byte(RETURN_OP); : acpigen_write_package(0); : acpigen_write_package_end(); > Why does this return a value? I don't see the kernel driver expecting any return value from these me […] We need this return value to resolve any kind of EVAL failure in DPTF ESIF shell. This is the same way it's handled in FSP code as well. https://review.coreboot.org/c/coreboot/+/57096/comment/11fe61c9_e12dff13 PS5, Line 237: acpigen_pop_len > acpigen_write_device_end() Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/57096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I035d2844b9ba6a9532ae006fc1c43e34cb94328a Gerrit-Change-Number: 57096 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 12:44:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Refactor the SMBIOS type 17 write function
by Angel Pons (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56628 ) Change subject: arch/x86: Refactor the SMBIOS type 17 write function ...................................................................... Patch Set 11: (4 comments) File src/device/dram/spd.c: https://review.coreboot.org/c/coreboot/+/56628/comment/47780440_80ac8068 PS11, Line 49: uint8_t Why not use enum types instead of plain integer types? It's easy to forget which enum goes with which variable. (Also applies to other cases like this in this patch) https://review.coreboot.org/c/coreboot/+/56628/comment/ea295f19_d644cbe7 PS11, Line 171: sizeof(struct spd_info) sizeof(*info) https://review.coreboot.org/c/coreboot/+/56628/comment/69df4029_aae82748 PS11, Line 171: (struct spd_info *) cast not needed https://review.coreboot.org/c/coreboot/+/56628/comment/5cd8057e_30f4cfbc PS11, Line 171: malloc Why not let the caller pass a pointer to a `struct spd_info` instead? This way, there's no need to deal with dynamic memory in here. -- To view, visit https://review.coreboot.org/c/coreboot/+/56628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Gerrit-Change-Number: 56628 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Sep 2021 12:43:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/gooey: Add fw_config probe for ALC5682-VD & VS
by Henry Sun (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Paul Menzel, Stanley Wu, Paul Fagerburg, Karthik Ramasubramanian. Henry Sun has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57367 ) Change subject: mb/google/dedede/var/gooey: Add fw_config probe for ALC5682-VD & VS ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/57367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib458cf47909a2d7a65f086c5f30f85a16f78d589 Gerrit-Change-Number: 57367 Gerrit-PatchSet: 2 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Allen Cheng <allen.cheng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 12:41:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Skip returning default leaf value as `0`
by Angel Pons (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, Subrata Banik, Kyösti Mälkki. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57305 ) Change subject: arch/x86: Skip returning default leaf value as `0` ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/arch/x86/cpu_common.c: https://review.coreboot.org/c/coreboot/+/57305/comment/6bdef675_60f0fc52 PS2, Line 115: return DETERMINISTIC_CACHE_PARAMETERS_CPUID_IA; > @Angel, looks like Tim also +2'ed this. […] I don't mind. -- To view, visit https://review.coreboot.org/c/coreboot/+/57305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee33b39298e7821ac5280d998172b58a70c8715b Gerrit-Change-Number: 57305 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 12:28:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: skylake DDR4 boards: Set `CaVrefConfig` to 2
by Angel Pons (Code Review) 03 Sep '21

03 Sep '21

Attention is currently required from: Nico Huber, Frans Hendriks, Matt DeVillier, Arthur Heymans, Michael Niewöhner, Patrick Rudolph, Wim Vervoorn. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57262 ) Change subject: skylake DDR4 boards: Set `CaVrefConfig` to 2 ...................................................................... Patch Set 3: (1 comment) File src/mainboard/kontron/bsl6/romstage.c: https://review.coreboot.org/c/coreboot/+/57262/comment/c5f419cb_288a66a6 PS3, Line 40: memory_params->CaVrefConfig = 2; > Hmmm, I was much surprised to see that we didn't query Kontron about this […] If you have schematics, it's very easy to check what the correct value is. I wrote a very long comment in CB:52110 that should explain what to look for. With `CaVrefConfig` set to 0 on DDR4, MRC still adjusts write Vref correctly, but sometimes skips configuring CA (Command/Address) Vref for channel 1. I didn't observe any significant differences in my tests on 1DPC (DPC = DIMM Per Channel) configurations, as CA margins are pretty large. However, there could be issues with 2DPC configurations (margins aren't as good). TL;DR: I don't expect this change to make any noticeable difference, especially on this particular board. -- To view, visit https://review.coreboot.org/c/coreboot/+/57262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idab77daff311584b3e3061e9bf107c2fc1b7bdf1 Gerrit-Change-Number: 57262 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Fri, 03 Sep 2021 12:27:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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coreboot-gerrit September 2021