Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57096 )
Change subject: drivers/intel/dptf: Introduce new thermal control mechanism for pch device ......................................................................
Patch Set 5:
(5 comments)
Patchset:
PS5:
Any plans to support GFC0, GFC1, GEMI, SEMI, GFCS, GFCS ?
We will add support for these in next different patch set.
File src/drivers/intel/dptf/dptf.c:
https://review.coreboot.org/c/coreboot/+/57096/comment/dd52ea36_ba0f5757 PS5, Line 7: #include <soc/intel/common/block/include/intelblocks/pmc_ipc.h>
`#include <intelblocks/pmc_ipc. […]
Ack
https://review.coreboot.org/c/coreboot/+/57096/comment/e8958f55_0920fa72 PS5, Line 200: int
nit: […]
Ack
https://review.coreboot.org/c/coreboot/+/57096/comment/a0761cbc_c7617385 PS5, Line 211: acpigen_emit_byte(RETURN_OP); : acpigen_write_package(0); : acpigen_write_package_end();
Why does this return a value? I don't see the kernel driver expecting any return value from these me […]
We need this return value to resolve any kind of EVAL failure in DPTF ESIF shell. This is the same way it's handled in FSP code as well.
https://review.coreboot.org/c/coreboot/+/57096/comment/11fe61c9_e12dff13 PS5, Line 237: acpigen_pop_len
acpigen_write_device_end()
Ack