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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57219 )
Change subject: drivers/intel/fsp/Makefile: error out when FSP files aren't specified
......................................................................
Patch Set 5:
(1 comment)
File src/drivers/intel/fsp2_0/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/57219/comment/841261b0_be1cd1a7
PS5, Line 114: $(warning ADD_FSP_BINARIES isn't selected even though this SoC uses the FSP.)
: $(warning The resulting image likely won't boot successfully.)
> I'd say we want a warning but not like this. We already have such […]
i agree that it would be much more useful to have the warning at the end of the build. removed that part from this patch
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Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: drivers/intel/fsp/Makefile: error out when FSP files aren't specified
......................................................................
drivers/intel/fsp/Makefile: error out when FSP files aren't specified
Error out when the FSP binaries that are supposed to be added aren't
specified.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Suggested-by: Nico Huber <nico.h(a)gmx.de>
Change-Id: Ie5f2d75d066f0b4e491e9c8420b7a0cbd4ba9e28
---
M src/drivers/intel/fsp2_0/Makefile.inc
1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/57219/6
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57359 )
Change subject: mb/google/brya/variants/gimble: add GPP_B4 and GPP_D11 to early_gpio_table
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57359/comment/164f2e40_0fb833ce
PS2, Line 9: needs extra time to run boot process
> Hi Furquan, […]
From bootblock (early GPIO table) to depthcharge is probably ~800ms, but ramstage (normal GPIO table) to depthcharge is probably closer to ~300ms.
1) Please double-check required power-on time (and other power sequencing requirements)
2) Ensure that this does not violate any minimum power-off times for the storage device as well (time between a reboot making the GPIOs go hi-Z and before they are driven again in bootblock here).
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Change subject: mb/google/brya/variants/gimble: Enable SaGv support
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57357/comment/1f97ac2d_6911319c
PS2, Line 9: This patch enables SaGv support for gimble.
Have you boot tested it?
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Change subject: mb/google/brya/variants/gimble: add GPP_B4 and GPP_D11 to early_gpio_table
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57359/comment/c5d48ce5_13d991aa
PS2, Line 9: needs extra time to run boot process
> How much is the total required time? Did you check the datasheet?
Hi Furquan,
We have asked vendor to this question, but they don't have about this datasheet.
Do you want to know how long it takes to boot into OS ?
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Change subject: mb/google/brya/variants/gimble: Enable SaGv support
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57357/comment/1c8cb43a_511b44fe
PS2, Line 9: This patch enables SaGv support for gimble.
> Why can it be enabled?
Hi Paul,
The ADL-P reference board has enabled SaGv and on Gimble, we also need to enable it.
https://partnerissuetracker.corp.google.com/issues/198531517
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Change subject: drivers/intel/dptf: Introduce new thermal control mechanism for pch device
......................................................................
Patch Set 6:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57096/comment/3e971d52_7c8c5d39
PS1, Line 7: tpch: Introduce new thermal control mechanism for pch device
> drivers/intel/tpch:
Done
https://review.coreboot.org/c/coreboot/+/57096/comment/726419fd_505a5ce1
PS1, Line 9: Introduce new thermal control mechanism for pch device.
> Please elaborate.
Done
File src/drivers/intel/tpch/tpch.c:
https://review.coreboot.org/c/coreboot/+/57096/comment/9ca14f21_e4dfc50e
PS1, Line 14: static void tpch_write_hid(bool is_eisa, const char *hid)
: {
: if (is_eisa)
: acpigen_emit_eisaid(hid);
: else
: acpigen_write_string(hid);
: }
> if this driver ends up merging with the regular DPTF drive, this function is moot, there is `dptf_wr […]
Done
https://review.coreboot.org/c/coreboot/+/57096/comment/850b3c69_5b6611d8
PS1, Line 55: acpigen_write_scope("\\_SB");
: acpigen_write_device(acpi_device_name(dev));
> if TPCH is added to the DPTF participants, then you can add support in `scope_of` to handle this.
Ack
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57095
to look at the new patch set (#5).
Change subject: soc/intel/common: Add PMC IPC commands for FIVR
......................................................................
soc/intel/common: Add PMC IPC commands for FIVR
Add PMC IPC commands information for FIVR control functionality.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: Iccb43b7ba4f0765499bf1844efbbb526bd671a8f
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/soc/intel/common/block/include/intelblocks/pmc_ipc.h
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/57095/5
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57096
to look at the new patch set (#6).
Change subject: drivers/intel/dptf: Introduce new thermal control mechanism for pch device
......................................................................
drivers/intel/dptf: Introduce new thermal control mechanism for pch device
Introduce new thermal control mechanism for pch device under dptf.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I035d2844b9ba6a9532ae006fc1c43e34cb94328a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/drivers/intel/dptf/Kconfig
M src/drivers/intel/dptf/dptf.c
M src/drivers/intel/dptf/dptf.h
3 files changed, 57 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/57096/6
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