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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57219 )
Change subject: drivers/intel/fsp/Makefile: error out when FSP files aren't specified
......................................................................
Patch Set 6:
(1 comment)
File src/drivers/intel/fsp2_0/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/57219/comment/1ee3a059_43c79cdc
PS5, Line 114: $(warning ADD_FSP_BINARIES isn't selected even though this SoC uses the FSP.)
: $(warning The resulting image likely won't boot successfully.)
> You can add the warnings at the end of the build with something like this: […]
done in CB:57368
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57368 )
Change subject: drivers/intel/fsp2_0: add warning when ADD_FSP_BINARIES isn't selected
......................................................................
drivers/intel/fsp2_0: add warning when ADD_FSP_BINARIES isn't selected
Platforms that rely on the FSP for parts of the hardware initialization
likely won't boot successfully when no FSP binaries are added during the
build, so print a warning at the end of the build in this case.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Suggested-by: Nico Huber <nico.h(a)gmx.de>
Suggested-by: Martin Roth <martinroth(a)google.com>
Change-Id: I6efc184ecc4059818474937fd31574f703c9bdc6
---
M src/drivers/intel/fsp2_0/Makefile.inc
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/57368/1
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index 80dc93b..2b432f8 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -110,8 +110,17 @@
ifeq ($(call strip_quotes,$(CONFIG_FSP_S_FILE)),)
$(error No FSP-S binary file specified.)
endif # CONFIG_FSP_S_FILE
+else # CONFIG_ADD_FSP_BINARIES
+build_complete:: warn_no_fsp_binaries
endif # CONFIG_ADD_FSP_BINARIES
+PHONY+=warn_no_fsp_binaries
+warn_no_fsp_binaries:
+ printf "\n\t** WARNING **\n"
+ printf "ADD_FSP_BINARIES isn't selected even though this SoC relies on the FSP.\n"
+ printf "The resulting image won't contain the FSP binaries and likely won't boot\n"
+ printf "successfully.\n"
+
subdirs-y += ppi
endif
--
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Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56725 )
Change subject: mb/google/guybrush: Document USB mapping in devicetree
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Ping on review.
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Change subject: soc/amd/common/include/lpc: add definitions for LPC LDRQ control bits
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Any update on this?
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56784 )
Change subject: mb/pcengines/apu2/romstage: use proper GPIO configuration API
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
oh, missed submitting CB:56783 before this one; that patch is also submitted now and the tree builds again
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56783 )
Change subject: soc/amd/common/block/gpio_banks/Kconfig: add option for non-soc/ chips
......................................................................
soc/amd/common/block/gpio_banks/Kconfig: add option for non-soc/ chips
southbridge/amd/pi/hudson uses the common GPIO bank access code from
soc/amd, but doesn't provide all functionality that would be needed to
use the full functionality. Add a Kconfig option that switches off some
functionality in the common SoC GPIO access code, so that more of the
functionality proviced by the common SoC GPIO code can be used in the
AMD binaryPI chipset and board code.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ib10d5d5580aab30a359aa001bb6fc7e9fdb8fc41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56783
Reviewed-by: Martin Roth <martinroth(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/common/block/gpio_banks/Kconfig
M src/soc/amd/common/block/gpio_banks/gpio.c
M src/southbridge/amd/pi/hudson/Kconfig
3 files changed, 17 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
diff --git a/src/soc/amd/common/block/gpio_banks/Kconfig b/src/soc/amd/common/block/gpio_banks/Kconfig
index 1efb1db..0a1bffe 100644
--- a/src/soc/amd/common/block/gpio_banks/Kconfig
+++ b/src/soc/amd/common/block/gpio_banks/Kconfig
@@ -5,3 +5,16 @@
Select this option to use the newer style banks of GPIO signals.
These are at offsets +0x1500, +0x1600, and +0x1700 from the AcpiMmio
base.
+
+if SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
+
+config SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE
+ bool
+ help
+ Select this option when selecting the GPIO bank support from AMD
+ chipsets outside the soc/ subtree that only support a subset of the
+ features available on the chipsets inside the soc/ subtree. When this
+ option is selected, no SMI or SCI event can be configured by the GPIO
+ code.
+
+endif # SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c
index 8f84cb6..b3c1ac1 100644
--- a/src/soc/amd/common/block/gpio_banks/gpio.c
+++ b/src/soc/amd/common/block/gpio_banks/gpio.c
@@ -171,8 +171,9 @@
static const struct soc_amd_event *gev_tbl;
static size_t gev_items;
int gevent_num;
- const bool can_set_smi_flags = !(CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) &&
- ENV_SEPARATE_VERSTAGE);
+ const bool can_set_smi_flags = !((CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) &&
+ ENV_SEPARATE_VERSTAGE) ||
+ CONFIG(SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE));
set_gpio_mux(g->gpio, g->function);
diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig
index fa60d17..c959e28 100644
--- a/src/southbridge/amd/pi/hudson/Kconfig
+++ b/src/southbridge/amd/pi/hudson/Kconfig
@@ -18,6 +18,7 @@
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
+ select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
config EHCI_BAR
--
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Change subject: soc/amd/common/block/gpio_banks/Kconfig: add option for non-soc/ chips
......................................................................
Patch Set 2: Code-Review+2
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